Nack Digital Equalizer
Final Report
Craig Petersen
Kevin Wong
Andrew Nguyen
Nguyen Nguyen
CPSC 483 – 502
Dr. Mahapatra
© December 2000
Acknowledgements
Our group would like to take this time to thank the following people for their help during
the implementation of our project:
Dr. Rabi Mahapatra, Instructor
John Wisinger, Teaching Assistant
Jonathan Jones, Teaching Assistant
Joseph Sims, Teaching Assistant
2
Table of Contents
Chapter 1: Abstract and Introduction…………………………4
Chapter 2: LED (Digital Display) Circuit…..………………….5
Chapter 3: Serial Interface……………………………………...8
Chapter 4: Main Equalizer Circuitry……………….………...13
Chapter 5: Data Format Between Components………….…...16
Chapter 6: The 5-band equalizer – Functionality…….17
Chapter 7: The Columnar LED display………………………20
Chapter 8: Software - PC Software and Communication……21
Appendices………………………………………………………22















A. Bandmaster Circuit - VHDL and State Machine
B. Band Select Circuit -VHDL and State Machine
C. LED - VHDL and State Machine
D. DB – Verilog Code
E. FREQ – Verilog Code
F. Data Load – Verilog Code
G. UART Control – Verilog Code
H. Seven Segment LED Data Sheet
I. LM3916 Dot/Bar Display Driver Manual
J. TEA6360 Equalizer IC
K. I2C Bus Manual
L. 16550 UART Data Manual
M. MAX 232 Data Sheet
N. Software Code in Visual Basic for PC Interface
O. Project Pictures
3
Chapter 1: Abstract and Introduction
Abstract:
In today’s society, the use of digital electronics is growing very rapidly. One such
area is in the music and audio field. For this reason, our group has chosen to create a
fully programmable digital equalizer that can be interfaced with either a home PC or
stereo system. The equalizer will allow a user to adjust a 5-band range of frequencies
that will allow for the greatest listening satisfaction.
Introduction:
Because of the increasing use of digital techniques in consumer audio equipment, the
need to develop an audio device for application is beneficiary. Our group has
developed a digitally controlled graphic equalizer, called NACK, which is potentially
an audio device for application in car stereo set, TV audio system and music centers.
The NACK offers substantial digital control steps for audio frequency responses
within the cut/boost resolution. The equalizer device contains a number of fixedfrequency bandpass/notch filters with a gain control for each filter.
Resonances and nulls in the frequency response of an audio system are easily
compensated with proper adjustment of the equalizer. Its 5-band structure contains
enough resistant variables for a stereo, 5-band equalizer with 1 dB steps covering a 12
dB range. The NACK is configured such that a high degree of flexibility remains in
the overall equalizer design, without compromising the quality of the analog signal
path. The digital sections of a finished equalizing instrument will include a
microprocessor, pushbutton controls, a display and any software manipulation to
drive the equalizer.
4
Chapter 2: LED (Digital Display) Circuit
This schematic is the circuitry for the LED (digital display) of the decibel level output
from the user’s set preference when a band is selected. The main chip being used is the
state machine (LED) which determines which number needs to be outputted to the LED
indicator. The circuit also has a D-Flip-Flop which is used to debounce the button that is
being pushed and is clocked with a 7.5 Hz clock signal. The clock signal is generated
from the 15 Hz oscillator and then a two bit counter is used to divide that clock in half to
the appropriate 7.5 Hz signal. The outputs are then fed into the FPGA to the appropriate
signals that are hooked up to the hardware version on the breadboard to control what is
seen on the level indicator. We will now go into a little more detail on the complete
operation of this circuit.
The first seven segment display is the band selector. When a user presses the button the
numeric display will cycle through the numbers, starting with one, and continuing
through five. After reaching five, the display starts over, displaying one, and so on.
Since our equalizer supports up to five different bands, these numbers indicate which
band the user has currently selected. This component is shown below, Figure 2.1, and the
code can be seen at in the appendices at the end of our report.
Figure 2.1 - Band Selector
The next piece display on our board is for the decibel level output indicator. When the
circuit is first initialized, the display is default to 0, indicating no adjustment on that band
is selected (0 dB). If the user presses the red button on our board, the numeric display
will output numbers indicating that the dB level is increasing in 2.4 increments.
Therefore the dB level will go from 0 to 2.4, 4.8, 7.2, 9.6 and then 12. After reaching 12,
our maximum level of gain, the circuit will stay at 12 until the user decreases the gain. If
the user presses the black button, this signals to the circuit to decrease the dB level.
During this mode of operation, the user can decrease its gain level down until –12 dB is
reached.
5
The other seven-segment display is simply used for the sign indicator. When the user
decreases the dB level so that it is negative, a negative sign will appear in that display. If
the dB gain is 0 or above, the LED will simply be blank indicating that the dB range is
positive. This signal is sent out to the through the SIGN output shown below. One other
thing to note is the DOT output. This signal lights up the small period indicating a real
number (ex: 2.4) on the display; of course, when 12 is output to the LED, the DOT will
not be sent indicating the integer value. This circuit is shown below, in Figure 2.2.
Figure 2.2 - dB Level Indicator with SIGN and DOT outputs
Also in our main schematic, we have a chip called ENABLE_CHIP, and is shown below
in Figure 2.3, and in detail in Figure 2.4. To initialize a state machine, an enable signal
must be present. Rather than hooking this signal up to a button to enable it, the
ENABLE_CHIP circuit just takes the very first clock (positive edge) and sends the signal
to initialize the state machine and then goes low; this way, our state machine instantly
initializes when power is applied.
Figure 2.3 – ENABLE_CHIP – Block Diagram
6
Figure 2.4 - ENABLE_CHIP – Internal Representation
When all of these components are put together, we have realized our LED circuitry and
the complete schematic is shown below, in Figure 2.4. Also note the DB and FREQ
chips, these will be discussed in a later section.
Figure 2.5 - Complete LED Circuit
7
Chapter 3: Serial Interface
The serial interface built-in to the digital equalizer is used to allow connection between a
desktop computer and the equalizer itself. With this connection, the user can use specially
designed software to control the equalizer and load/save the settings through an easy to
use graphical user interface. The schematic below in figure 3.1 shows the components
used in the serial interface and the connection between each of them.
Figure 3.1 – Serial Interface Schematic
The serial interface consists of two main parts, the actual hardware that built with
TTL/CMOS component, and the FPGA part. For the actual hardware portion of the serial
interface, it consists of two make components, the 16550 Universal Asynchronous
Receiver/Transmitter (UART) – Figure 3.2 and the MAX232 Driver/Receiver – Figure
3.3. The 16550 UART is used to make conversion between serial and parallel data and
vice versa. It also provides the functions of adding/deleting standard asynchronous data
bits. For the equalizer, the UART is setup to handle serial data with 8 data bits, 1 stop bit,
no parity bit, and at a baud rate of 115200bps. Figure 3.4 shows how the data
send/receive serially using the RS232 data format. These settings of the UART are
initialized by the Verilog code programmed into the FPGA, which will be described in
details later in the chapter.
Figure 3.3 – MAX 232
Figure 3.2 – 16550 UART
8
Figure 3.4 – RS232 Data Format
The MAX232 Driver/Receiver – Figure 3.3 is another part of the main hardware
component. In RS232 logic, a voltage potential of -3V~-25V is used to represent the high
logic level and a voltage potential of 3V~25V is used to represent the low logic level.
Since the UART, FPGA, and most of the common hardware component used TTL logic,
the MAX232 Driver/Receiver is used to convert the signal from RS232 logic to TTL
logic. Figure 3.5 shows the picture representation of how this conversion is performed.
Figure 3.5 – RS232/TTL Logic Conversion
The FPGA portion of the serial interface performs the initialization of the UART and
receive/transmit data. This is done by a verilog code, which is programmed into the
FPGA. Depending on the data communication setting used for the application, the verilog
code first performs the initialization of the UART. After the initialization process, the
program will wait and listen on two control line, the RxRDY from the UART which
inform the program to receive data from the UART to the FPGA, and the MWREQ from
other FPGA component which inform the program to transmit data from the FPGA to the
UART. Figure 3.6 shows the component module created in Xilinx Schematic Editor.
9
Figure 3.6 – UART Control Module
The verilog code of the UART Control is available in the Appendix. The following is the
description of each input and output pins of this module.
Control Pins:
CLK – Input clock signal which trigger the module.
RESET – Input signal to reset the module.
UART Connection Pins:
A[2:0] – Address line to select the register on the UART.
DIN[7:0] – Data line to receive data from the UART.
DOUT[7:0] – Data line to transmit data to the UART.
WBUF – Turn on the write buffer within the FPGA (See Full Schematic)
RBUF – Turn on the read buffer within the FPGA (See Full Schematic)
WR – Command the UART to transmit data.
RD – Command the UART to receive data.
TXRDY – Inform the module that the transmit buffer on UART is full.
RXRDY – Inform the module that data is available on the UART receive buffer.
MR – To perform the master reset the UART.
FPGA Internal Connection Pins:
MEMIN[7:0] – Data line with data receive from the UART
MEMOUT[7:0] – Data line with data transmit to the UART
MWREQ – To inform the module to transmit data from MEMIN to the UART
MWACK – Command other FPGA module that data from MEMIN is transmitted.
MRREQ – Command other FPGA module to read data from MEMOUT.
MRACK – To inform the module that other FPGA module is done sending data.
DSR – Use to check for serial connection.
SERIALRDY – To inform other FPGA module that the serial connection is ready.
Figure 3.7 show the full connection on how this verilog code module is used and
connected to other component and the UART.
10
Figure 3.7 – Full Schematic on UART Control Module Connection
Since the data line on the 16550 UART can be used as both input and output pins, and
I/O PAD module is used in the FPGA to allow the physical connection to perform both
input and output functions. Since a buffer is needed for each input and output connection
of the FPGA, and an I/O buffer is not available as a standard module for the FPGA, two
tri-state buffers are used to create a module which can be used as a I/O Buffer. Figure 3.8
shows the module of the I/O buffer created in the Xilinx Schematic Editor, and Figure 3.9
shows the schematic of this I/O buffer.
Figure 3.8 – I/O Buffer
Figure 3.9 – I/O Buffer Schematic
11
The following is the detail descriptions of each input and output pins of the I/O Buffer
module.
W – Enable/Disable the write (output) buffer
R – Enable/Disable the read (input) buffer
OUT – Data line for data sending out from the FPGA
IN – Data line for data receiving by the FPGA
PAD – Internal connection to the IOPAD module.
The serial interface interacts with other FPGA components mainly with the UART
Control module. The SERIALRDY pin informs other components that the serial
connection is established and ready for communication. With this connection, whenever
data is received by the module from the UART, it will raise the control pin MWREQ,
which stand for Memory Write Request. When other FPGA module received this signal,
it should allocate location to read the data from the data pin MOUT. After the data is
received, that specific module should send out the signal to the control pin MWACK of
the UART Control module to inform the module that data transmission is completed.
When some FPGA module wants to send out data to the serial line, that module should
raise the signal to the control pin MRREQ, which stand for Memory Read Request. The
data should be set on the data line MIN when this request is made. With this signal, the
UART Control module will read the data from MIN, and send the data out serially. Also,
the module will set the control line MRACK to inform the other FPGA module that the
data is sent.
12
Chapter 4: Main Equalizer Circuitry
The main schematic for our equalizer circuitry is shown in Figure 4.3. It mainly
comprised of two main chips, the BANDMASTER and the DATA_LOAD.
The fundamental building block for the 5-band equalizer is the use of its SDA and SCL
since they own the main access to the equalizer chip as the I2C bus control. These two
signal lines only offer serial communication, the need of producing serial bits is crucially
required. Effort to do this is given to the equalizer state machine and its DATA_LOAD
circuit. The equalizer state machine serves as the producer of parallel bits in this case
while the DATA_LOAD is the consumer. The consuming DATA_LOAD is indeed far
more a consumer. Its ability to produce serial data asynchronous to the chip clock is
somewhat incredible. Below is sequence of bits needed for the SDA I2C bus of which the
address of the chip is the slave address bits, the band selection designated at the
subaddress bits and the decibel selection specified at 8 data bits while ack is acknowledge
bit from the chip.
1 start bit
8 slave address bits
ack
8 subaddress bits
ack
8 data bits
1 stop bit
The equalizer state machine is simply a state machine producing parallel sequences of
bits required by equalizer I2C bus as controlling bits for its state (status). Its only
capability is to give out sequences of bits in parallel, which are not what the SDA needs.
It also provides the user the flexibility of switching to any other bands and decibels from
current position. The subaddress bits solidify band selections, and the data bits support
decibel choices of which the correctly specified 8 bits are required. Wrong values do not
make any transition occur. Right order of input from 8-bit band to 8-bit decibel as shown
in the figure is needed. The slave address bits are not required as input from the user
since they are always the same and static for the chip. Changing to any other state of
band and/or decibel always gives out the figure pattern since the equalizer chip only
accepts that pattern.
The first main circuit in our schematic is the BANDMASTER circuit. This circuit is
comprised using the state machine. Its basic operation is to accept the DATA (input) and
SUB (subaddress) along with the CLK signal. The EN input is simply used to enable the
state machine and is connected to an ENABLE_CHIP which was described earlier. The
FLAG input is used as a signal indicating that the user has selected the proper band, the
proper band level increase (or decrease). After pushing the button on the breadboard, the
signal is then input to flag and the operation begins to send out the data bits to the
DATA_LOAD chip (which will be described next). It also sends out a RDY signal
indicating that the data is loaded on the bus lines and is ready to be read. The
BANDMASTER circuit is shown below, in Figure 4.1, and the state machine can be
viewed in the appendix at the end of our report.
13
Figure 4.1 – BANDMASTER block circuit
The other main chip in our circuit is the DATA_LOAD. This chip serves as our serial
output to our equalizer chip on our breadboard. Basically is accepts data from the
BANDMASTER into the DATA1, SLAVE and SUBADD lines in parallel, to be sent out
serially on the IC^2 bus, as described above. The CLK is simply a clock signal generated
by the oscillator in our schematic, namely a 16 HZ clock frequency. The button input is
simply a signal sent from the BANDMASTER indicating that all the data it has been set
up and is ready to be loaded into our DATA_LOAD. Once the signal is asserted
(BUTTON), the verilog code initializes and sends out the data bits serially, through the Z
output which is then connected to the SDA leg on our equalizer chip. The DATA_LOAD
chip is shown below in Figure 4.2, and the verilog code can be seen in our appendix.
Figure 4.2 – DATA_LOAD
As noted earlier, the entire schematic is seen in Figure 4.3. You may also note that the
two main bus lines, DATA1 and SUB are sent into the circuit coming from the outputs of
the LED circuit, in which SUB is the band level selected, and DATA1 is the dB level.
14
Figure 4.3 – Main Equalizer Circuit
15
Chapter 5: Data Format Between Components
In order for each component/module that we created to communicate with each other, a
data format must be set. With this data format standardize, every component can be
connected directly without any difficulties and can communicate with each other easily.
This data format is similar to other industry standard like RS232 or I2C. For the digital
equalizer, the data format is relatively simple, which consists for 8-bits. These 8 bits will
then send parallel through an 8-bits data bus that connect between each component.
The main control related to the equalizer is the selection of band frequency and the dB
level. For the band frequency, this equalizer will have 5 different band, which can be
represented in binary number as 000, 001…011, 100. As a result, 3 bits out of the 8 data
bits is used to represent the band frequency. For the dB level, the equalizer provides a
range selection of –12dB to 12dB with 5 steps in each direction. 1 bit out of the 8 data
bits is used to represent the sign of the dB level, and the remaining 4 bits will be used to
represent the number of steps in the dB level. Figure 5.1 shows a picture representation of
the data format.
Most
Significant
Bit
Freq Band
Least
Significant
Bit
Sign (+/-)
dB Level (in steps)
Figure 5.1 Equalizer Data
Example:
Data Bit Pattern
00010010
01100001
Band Frequency
Band 0
Band 3
Sign (+/-)
- (negative)
+ (positive)
16
dB Level (in steps)
2 Steps
1 Steps
Chapter 6: The 5-band equalizer IC - Functionality
The 5-band stereo equalizer is an I2C-bus controlled tone processor for audio
applications. It offers the possibility of sound control as well as equalization of sound
pressure behavior of different rooms or loudspeakers. It features on five different filters
for each channel of which each filter defines a center frequency, bandwidth and
maximum boost and cut. The choice for these is through its I2C control bus. There are
five steps of selection and one extra step for the linear position. At maximum gain of 12
dB the typical step resolution is 2.4 dB. Therefore the typical
gain factors for 12 dB application are as follows:
step 1 = 2.4 dB
step 2 = 4.8 dB
step 3 = 7.2 dB
step 4 = 9.6 dB
step 5 = 12.0 dB
The control of the different filters is obtained by selecting the appropriate subaddress
byte while the position of the boost part and the cut part is independently controllable via
data byte.
The best quality of the filter has its maximum in the maximum position (steps 5), if boost
(cut on step 0) or cut (boost on step 0) is used. The quality factor decreases also with the
step number (variable quality factor). This mode of the control pattern is according to
Figure 6.3.
Different control is necessary if to achieve a constant quality factor over the whole
control range. For boost with a constant quality factor over the boost range position +5 is
selected and boost control is then performed using cut. This control technique is applied
to the cut range with position -5 selected and the boost is varied. The cut part has to
follow the boost part in each filter for economic reasons. So the signal is first amplified
and then attenuated.
This has to be taken into account for the internal level diagram in case of constant quality
factor. This may result in a mode between constant Q and non-constant Q mode; for
example for the position +2 it is not necessary to amplify by step +5 and then attenuate
by -3 step. The combination of step +4 and step -2 to reach
position +2 is a good result (referred to quasi constant quality factor). The main equalizer
chip is shown below, in Figure 6.1, and the more detailed implementation of the IC is
shown in Figure 6.2. In figure 6.3, we have given the IC’s filter control with constant
and quasi-constant quality factor.
17
Figure 6.1 – TEA6360 Equalizer IC
Figure 6.2 – Detailed Version of the TEA6360 Equalizer IC
18
Figure 6.3 – Filter Control with Constant Quality Factor
19
Chapter 7: The Columnar LED Display
The columnar section of our project is basically used for visual effects. We believed that
by adding five rows of lights all bouncing up and down in conjunction with the frequency
being played by the CD player would be visually appealing to the user. This part of our
project was based on National Semiconductors LM3916 Dot/Bar display driver, which
can be seen below in Figure 7.1.
Basically, we implemented our design using five individual chips. Then, we connected
ten LEDs (3 red, 3 yellow, and 4 green) to pins 1, and 10 through 18 to give the
“bouncing” effect. Then, each chip’s input (pin 5 – SIG), is then connected to the
specific frequency from our main equalizer chip, giving us the five bands needed. The
V(led) is set to approximately 5 Volts to drive the LEDs, and V(ref) voltage can be used
to adjust the brightness of the LEDs. One may also note the use of the capacitor, C1.
This is used if the LED legs are longer than six inches, which ours were not so it was
optional. A more in depth description can be found in the appendices if more information
is needed.
Figure 7.1 – Columnar LED Driver IC
20
Chapter 8: PC Software and Communication
With the serial interface, the digital equalizer can be connected to the PC which has a
serial port. Using specially designed software, the equalizer can be controlled through the
PC with the serial connection. Figure 9.1 show the program flow chart of the software.
Figure 8.1 – Software Flow Chart
The software used on the PC to control the equalizer is written in Visual Basic. The
software will first search for the available serial COM port and attempt to connect to the
equalizer. After the connection is established, an equalizer control user interface will
show up to allow the user to control the equalizer. This can be done by sliding the 5
different scroll bars on the user interface, where each one represent each band of
frequency. Figure 9.2 show a sample output of the control user interface. With each
change in value, the software will send out the data, following the data format specified
in Chapter 5, to the serial port, which connected to the equalizer. The program will also
check for the connection between the equalizer and the PC. If the connection is lost, the
program will inform the user and stop all of it process until the connection is established
again.
Figure 8.2 – Software Program
21
22