4.3. Bus and Memory Transfers
4.3.1. BUS
If a computer has 16 registers, each holding 32 bits, how many wires are needed to connect every
register to every other? (162) For a large number of wide registers, the wires could end up taking
most of the space in the circuit.
A BUS is a single shared set of wires connecting all registers.
4.3.1.1. BUS with Multiplexers
Figure 4-3, bus system for 4 registers using multiplexers.
Bus, 4 8-bit registers connected for input and output. Use decoder/demux to drive load input on
registers. Wire one MUX. Clock speed is limited by the propagation delay through the MUX and
wires.
Only one register's contents can be on the bus for a given clock cycle. Which of the following are
legal?



A ← B, C ← D
A ← C, D ← C
B ← D, B ← A
Book error: No R1 in the diagram.
BUS ← C, A ← BUS
Can be written as:
A ← C
Multiplexers must be driven to select register C t time units before the clock pulse that loads A,
where t is the propagation delay of the multiplexers.
4.3.1.2. BUS with 3-state Buffers
3-state gates
3-state buffers can be used instead of multiplexers. A 3-state buffer is a combinational circuit
that acts like a simple switch: It either passes the input signal to the output (C=1), or blocks the
electrical current (C=0). The latter case is called high impedance state.
I ------|>-------- O
|
C -------+
3-state buffers can be used to connect or disconnect register outputs to/from the bus. A single
decoder can control a large number of 3-state buffers. The outputs of the 3-state buffers can be
tied directly together, provided that the circuit guarantees that all but one will be in highimpedance state at any given time. Using a decoder to control them guarantees this.
4.3.2. Memory Transfer
The internal bus connects only registers within the CPU, so how do we get data to and from
memory?
The address register (AR) is used to select a memory address, and the data register (DR) is used
to send and receive data. Both these registers are connected to the internal bus. DR is a bridge
between the internal BUS and the memory data BUS.
Memory can also be connected directly to the internal BUS in theory.
Diagram showing connections to memory unit.
M[AR] ← DR
DR ← M[AR]
Instruction and Instruction Code
We all know that without our instructions a computer can do nothing. Hence we need to instruct the
computer to perform a specific operation.
The collection of bits that instruct the computer to perform a specific operation is called an instruction
code.
Operation part is the most basic part of an instruction code. The operation code of an instruction is a
group of bits that define such operations as add, subtract, multiply, shift and complement.
The total number of operations available in the computer determines the number of bits required for
the operation code of an instruction. The operation code must consist of at least n bits for a given 2n (or
less) distinct operations.
An 'operation' is a binary code, that instruct the computer to perform a specific operation. The control
unit gets the instruction from memory and interprets the operation code bits. It then issues a sequence
of control signals to initiate micro-operations in internal computer registers. For every operation code,
the control issues a sequence of micro-operations required for the hardware implementation of the
specified operation.
This operation should be performed on some data stored in processor registers or on the data stored in
the memory. Hence an instruction code must specify both the operation and the registers or the
memory words where the operands are to be found, as well as the registers or the memory word where
the operands be stored.
Memory words can be specified in instruction codes by their address. Processor registers can be
specified by assigning to the instruction another binary code of K bits that specifies one of 2K registers.
There are many variations for arranging the binary code of instructions. Each computer has its own
particular instruction code format called its Instruction Set.
Register are used to quickly accept, store, and transfer data and instructions that are being used
immediately by the CPU, there are various types of Registers those are used for various purpose. Among
of the some Mostly used Registers named as AC or Accumulator, Data Register or DR, the AR or Address
Register, program counter (PC), Memory Data Register (MDR) ,Index register,Memory Buffer Register.
These Registers are used for performing the various Operations. While we are working on the System
then these Registers are used by the CPU for Performing the Operations. When We Gives Some Input to
the System then the Input will be Stored into the Registers and When the System will gives us the
Results after Processing then the Result will also be from the Registers. So that they are used by the CPU
for Processing the Data which is given by the User. Registers Perform:1) Fetch: The Fetch Operation is used for taking the instructions those are given by the user and the
Instructions those are stored into the Main Memory will be fetch by using Registers.
2) Decode: The Decode Operation is used for interpreting the Instructions means the Instructions are
decoded means the CPU will find out which Operation is to be performed on the Instructions.
3) Execute: The Execute Operation is performed by the CPU. And Results those are produced by the
CPU are then Stored into the Memory and after that they are displayed on the user Screen.
Types of Registers are as Followings
MAR stand for Memory Address Register
This register holds the memory addresses of data and instructions. This register is used to access data
and instructions from memory during the execution phase of an instruction. Suppose CPU wants to store
some data in the memory or to read the data from the memory. It places the address of the-required
memory location in the MAR.
Program Counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 microprocessors,
and sometimes called the instruction address register, or just part of the instruction sequencer in some
computers, is a processor register
It is a 16 bit special function register in the 8085 microprocessor. It keeps track of the the next memory
address of the instruction that is to be executed once the execution of the current instruction is
completed. In other words, it holds the address of the memory location of the next instruction when the
current instruction is executed by the microprocessor.
Accumulator Register
This Register is used for storing the Results those are produced by the System. When the CPU will
generate Some Results after the Processing then all the Results will be Stored into the AC Register.
Memory Data Register (MDR)
MDR is the register of a computer's control unit that contains the data to be stored in the computer
storage (e.g. RAM), or the data after a fetch from the computer storage. It acts like a buffer and holds
anything that is copied from the memory ready for the processor to use it. MDR hold the information
before it goes to the decoder.
MDR which contains the data to be written into or readout of the addressed location. For example, to
retrieve the contents of cell 123, we would load the value 123 (in binary, of course) into the MAR and
perform a fetch operation. When the operation is done, a copy of the contents of cell 123 would be in
the MDR. To store the value 98 into cell 4, we load a 4 into the MAR and a 98 into the MDR and perform
a store. When the operation is completed the contents of cell 4 will have been set to 98, by discarding
whatever was there previously.
The MDR is a two-way register. When data is fetched from memory and placed into the MDR, it is
written to in one direction. When there is a write instruction, the data to be written is placed into the
MDR from another CPU register, which then puts the data into memory.
The Memory Data Register is half of a minimal interface between a micro program and computer
storage, the other half is a memory address register.
Index Register
A hardware element which holds a number that can be added to (or, in some cases, subtracted from)
the address portion of a computer instruction to form an effective address. Also known as base register.
An index register in a computer's CPU is a processor register used for modifying operand addresses
during the run of a program.
Memory Buffer Register
MBR stand for Memory Buffer Register. This register holds the contents of data or instruction read from,
or written in memory. It means that this register is used to store data/instruction coming from the
memory or going to the memory.
Data Register
A register used in microcomputers to temporarily store data being transmitted to or from a peripheral
device.
Computer instructions
When referring to the computer processor, an instruction is a segment of code that contains steps that
need to be executed by the computer processor.
An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related
to programming, including the native data types, instructions, registers, addressing modes, memory
architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the
set of opcodes (machine language), and the native commands implemented by a particular processor.
Classification of instruction sets
A complex instruction set computer (CISC) has many specialized instructions, which may only be rarely
used in practical programs. A reduced instruction set computer (RISC) simplifies the processor by only
implementing instructions that are frequently used in programs; unusual operations are implemented as
subroutines, where the extra processor execution time is offset by their rare use. Theoretically
important types are the minimal instruction set computer and the one instruction set computer but
these are not implemented in commercial processors. Another variation is the very long instruction
word (VLIW) where the processor receives many instructions encoded and retrieved in one instruction
word.
General Register Organization
Memory access is very time-consuming, especially on today's computers, which typically have
many wait-states. Compounding the technological limitations on memory speed is the fact than
RAM memory banks are getting bigger. Bigger memory units means longer propagation delays
in decoding the address.
Memory access is also expensive in terms of the instruction code size necessary to accommodate
32 or 64-bit addresses.
If many CPU registers are available for heavily used variables and intermediate results, we can
avoid memory references much of the time, thus vastly increasing program execution speed, and
reducing program size.
In a general-register organization such as this one, any two registers can be inputs to the ALU, and the
results from the ALU can be stored in any register. When all registers are interchangeable, the
architecture is orthogonal, or symmetric. An orthogonal processor is ideal for programmers, because
they can use any register for any purpose. This is the other end of the spectrum from an accumulatorbased architecture.
Stack Organization
8.3.1. The Stack Data Structure
A stack is a LIFO (last-in, first-out) list. There are exactly two operations that can be performed
on a stack.
Diagram of a stack


A push operation adds a new item to the top of the stack.
A pop operation removes an item from the top of the stack.
// sp points to next available element on the stack
// sp is initialized to 0
int
{
push(int stack[], int sp, int value)
if ( sp == STACK_SIZE )
return STACK_FULL;
else
stack[sp++] = value;
return SUCCESS;
}
int
{
pop(int stack[], int sp)
if ( sp == 0 )
return STACK_EMPTY;
else
return stack[--sp];
}
8.3.2. Stack Implementation
Register stack (Mano section is confusing)
Memory stack
8.3.3. Uses for Stacks
8.3.3.1. Subprogram Calls
Stacks are used heavily in subprogram calls for saving the return address, passing arguments, and
as space for local variables.
8.3.3.2. Reverse Polish Notation
Infix notation: a * b + c * d
Infix is hard to evaluate programmatically. Polish mathematician Lukasiewicz invented prefix
notation.
Infix: a + b
Prefix (Polish): + a b
Postfix (Reverse Polish): a b +
When converting to postfix, operands should remain in the same order.
Postfix can be evaluated by scanning right to left and using a stack.
ab*cd*+
Convert to RPN and evaluate: (a + b) * c / d * a - c * f
Reduced instruction set computing
Reduced instruction set computing, or RISC (pron.: /ˈrɪsk/), is a CPU design strategy based on the insight
that simplified (as opposed to complex) instructions can provide higher performance if this simplicity
enables much faster execution of each instruction. A computer based on this strategy is a reduced
instruction set computer, also called RISC. The opposing architecture is known as complex instruction
set computing, i.e. CISC.
Various suggestions have been made regarding a precise definition of RISC, but the general concept is
that of a system that uses a small, highly-optimized set of instructions, rather than a more specialized
set of instructions often found in other types of architectures. Another common trait is that RISC
systems use the load/store architecture,[1] where memory is normally accessed only through specific
instructions, rather than accessed as part of other instructions like add.
Although a number of systems from the 1960s and 70s have been identified as being forerunners of
RISC, the modern version of the design dates to the 1980s. In particular, two projects at Stanford
University and University of California, Berkeley are most associated with the popularization of the
concept. Stanford's design would go on to be commercialized as the successful MIPS architecture, while
Berkeley's RISC gave its name to the entire concept, commercialized as the SPARC. Another success from
this era were IBM's efforts that eventually lead to the Power Architecture. As these projects matured, a
wide variety of similar designs flourished in the late 1980s and especially the early 1990s, representing a
major force in the Unix workstation market as well as embedded processors in laser printers, routers
and similar products.
Well-known RISC families include DEC Alpha, AMD 29k, ARC, ARM, Atmel AVR, Blackfin, Intel i860 and
i960, MIPS, Motorola 88000, PA-RISC, Power (including PowerPC), SuperH, and SPARC. In the 21st
century, the use of ARM architecture processors in smart phones and tablet computers such as the iPad
and Android tablets provided a wide user base for RISC-based systems. RISC processors are also used in
supercomputers such as the K computer, the fastest on the TOP500 list in 2011, and the second at the
2012 list.