Background Statement for SEMI Draft Document 5793
Reapproval of SEMI G75.13-0698 (Reapproved 0706), Test Method for
Measurement of the Leakage Current in Leadframe Tape
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in
reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.
Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant
patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this
context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the
latter case, only publicly available information on the contents of the patent application is to be provided.
Background
SEMI G75.13 is due for 5-year review. At the meeting of the Japan Assembly & Packaging TC Chapter Meeting on
September 29, 2014, the committee agreed to ballot SEMI G75.13 for reapproval without changes.
Review and Adjudication Information
Group:
Date:
Time & Timezone:
Location:
City, State/Country:
Leader(s)/Author(s):
Standards Staff:
Task Force Review
Packaging 5 Year Review Task Force
TBD
TBD
SEMI Japan
Tokyo, Japan
Kazunori Kato (AiT)
aitkato@attglobal.net
Naoko Tejima (SEMI Japan)
81.3.3222.5804
ntejima@semi.org
Committee Adjudication
Japan Assembly & Packaging TC Chapter
2015/01/20
15:00-17:00
SEMI Japan
Tokyo, Japan
Kazunori Kato (AiT)
Masahiro Tsuriya (iNEMI)
Yutaka Koma (Consultant)
Naoko Tejima (SEMI Japan)
81.3.3222.5804
ntejima@semi.org
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Please
contact Standards staff (Naoko Tejima at ntejima@semi.org) for confirmation.
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
SEMI Draft Document 5793
Reapproval of SEMI G75.13-0698 (Reapproved 0706), Test Method for
Measurement of the Leakage Current in Leadframe Tape
1 Summary of Method
1.1 Taped leadframes are molded under normal conditions, and the leakage current between designated leads is
measured before and after submitting the samples to HAST (121°C/2 atm/100% RH) moisture testing.
2 Equipment
2.1 HAST Chamber
2.2 Amperemeter with 10-15 ampere measuring capability
2.3 Power supply capable of 500 volts DC maximum
2.4 Electrostatically and electromagnetically shielded box
3 Sampling
3.1 The sampling is one sample per one lot. The vendor must report the definition of lot if the customer requires it.
4 Preparation of Specimens
4.1 Leadframes shall be cleaned up previous to taping, using a procedure agreed on between vendor and customer.
4.2 Taping Conditions — Temperature, pressure, and dwell time shall be agreed on between vendor and customer.
NOTE 1: A typical taped 40 pin DIP leadframe is shown in Figure 1, and relevant information for this frame is tabulated in
Table 1.
Figure 1
Typical Taped 40 Pin DIP Leadframe
Table 1 Relevant Information for 40 Pin DIP Leadframe
Leadframe Attribute
Leadframe thickness
Specification
0.25 mm
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 1
Doc. 5793  SEMI
LETTER (YELLOW) BALLOT
DRAFT
Document Number: 5793
Date: 3/15/2016
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
Leadframe material
Alloy 42
Leadframe manufacturing process
Stamping
Plating
None/Silver/Others
Surface treatment
To be agreed between tape user and supplier.
NOTE 2: The surface state of Alloy 42 is stable compared with Cu alloy, which is oxidized easily.
4.3 The leadframes shall be molded using molding compounds and cured with post mold curing conditions agreed
on between vendor and customer. The untaped leadframe shall be prepared with the same procedure as a control.
4.4 Trim the leads according to a procedure agreed on between vendor and customer.
5 Procedure
5.1 Setup the test circuit as shown in Figure 2.
Figure 2
Test Circuit for Measurement of Leakage Current
5.2 Place the first molded sample in the shielded box and attach clips to the leads A1 and A2 (see Figure 1).
Measure the initial leakage current at 500 volts maximum.
NOTE 3: The leakage current shall be measured after 5 minutes voltage application.
5.3 Repeat the measurement for all the lead pairs, A2 with A3, B1 with B2, and B2 with B3.
5.4 Place the samples in the HAST chamber and run the test.
5.5 After the tester has been automatically cooled to room temperature, remove the samples.
5.6 Measure the leakage current between the same lead pairs mentioned in §§ 5.2 and 5.3.
5.7 Repeat the HAST exposure and measure the cur-rent leakage.
5.8 Calculation
5.8.1 Maximum and minimum leakage current shall represent the test results.
5.8.2 Calculate the average result for all of the test points at each test stage.
5.8.3 Obtained data should be converted to 100 volts basis or as agreed on between vendor and customer.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 2
Doc. 5793  SEMI
LETTER (YELLOW) BALLOT
DRAFT
Document Number: 5793
Date: 3/15/2016
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
6 Related Documents
6.1 ASTM Specification1
ASTM D 257 — Test Methods for D-C Resistance or Conductance of Insulating Materials
6.2 JIS Specification2
JIS K 6911 — Testing Methods for Thermosetting Plastics
NOTICE: SEMI makes no warranties or representations as to the suitability of the standard(s) set forth herein for
any particular application. The determination of the suitability of the standard(s) is solely the responsibility of the
user. Users are cautioned to refer to manufacturer’s instructions, product labels, product data sheets, and other
relevant literature respecting any materials or equipment mentioned herein. These standards are subject to change
without notice.
By publication of this standard, Semiconductor Equipment and Materials International (SEMI) takes no position
respecting the validity of any patent rights or copyrights asserted in connection with any item mentioned in this
standard. Users of this standard are expressly advised that determination of any such patent rights or copyrights, and
the risk of infringement of such rights are entirely their own responsibility.
1
American Society for Testing and Materials, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania 19428-2959, USA.
Telephone: 610.832.9585, Fax: 610.832.9555; Website: www.astm.org
2
Japanese Standards Association, 1-24, Akasaka 4 Chome, Minato-ku, Tokyo, Japan
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document
development) activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 3
Doc. 5793  SEMI
LETTER (YELLOW) BALLOT
DRAFT
Document Number: 5793
Date: 3/15/2016