Silicon Detectors
Alan Honma
CERN
13-24 June, 2002
NATO Advanced Study Institute
on Techniques and Concepts of High Energy Physics
St. Croix, US Virgin Islands
Outline of Lectures
 Lecture
#1
 Introduction
• About the lecturer
• Historical perspective and motivation
• Types of silicon detectors
 Silicon
strip detectors (princples)
• Principles of operation
• Performance
 Lecture
#2
• Radiation damage
 Silicon
strip detectors (practical)
• Fabrication of sensors
• Construction of detector modules
• Read-out electronics
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
2
Outline of Lectures
 Lecture
#3
 Silicon
strip detectors (practical)
• Examples of usage in HEP experiments
 Other
•
•
•
•
Alan Honma
types of silicon detectors
Pixel devices
Pad devices
Drift devices
Future trends?
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
3
Introduction: about the lecturer
A
brief CV
• BS Univ. of Michigan
• MS, PhD Stanford Univ. Thesis: Strange meson resonances (LASS
fixed target experiment at SLAC)
• PostDoc at Queen Mary College (U London) - worked at CERN on the
UA1 experiment (W,Z), hadron calorimeter, trigger system, missing
energy analysis
• Research scientist at U. Victoria (Canada) - worked at SLAC on the
SLD experiment, liquid argon calorimeter, drift chamber electronics
• Research scientist at U. Victoria (Canada) - worked at CERN on OPAL
(LEP), silicon strip microvertex upgrades, single photon analysis, briefly
on ATLAS liquid argon hadronic calorimeter.
• Staff scientist, CERN - working on CMS silicon strip tracker : many
different aspects of module production
Yes, I like hardware...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
4
Introduction: Historical perspective (1)
 First
use of silicon detectors in HEP experiments
• Silicon (large cell-type) sensors around since 50’s for energy
measurements
• Precision position measurements up until 70’s done with emulsions or
bubble chambers  limited rates and no triggering!
• Traditional gas detectors: limited to 50-100m point resolution
• First silicon usage for precision position measuring (late 70’s):
– secondary vertex tagging (charm) in fixed target experiments
– segmented sensors (strips) with fine pitch
– first silicon pixel device used in early 80’s (NA32) charm experiment
• Why wasn’t silicon used earlier?
– Needed micro-lithography technology  cost
– Small signal size (need low noise amplifiers)
– Needed read-out electronics miniaturization (transistors, ICs)
After this, the use of silicon detectors quickly took off...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
5
Introduction: Historical perspective (2)
 First
silicon usage in collider experiments
• Initially avoided due to excessive material (electronics) in active volume
• Advances in electronics miniaturization and low mass composite
structures allowed its use
• Late 80’s: Mark II (SLC) and in the 90’s all 4 LEP experiments (ALEPH,
DELPHI, L3, OPAL)
• First pixel detector at collider (SLC) in early 90’s (SLD experiment)
• Usage of silicon limited to small region near interaction point (2-3 layers
around beam pipe): both silicon and electronics were very expensive
 Current
usage of silicon detectors
• Basically all currently operating HEP collider experiments (FNAL p-pbar
collider, HERA, B-factories at Cornell, SLAC and KEK) as well as all
those in construction (LHC) use silicon vertex detectors.
• Many fixed target experiments and non-HEP experiments (RHIC, space
physics) are using them as well.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
6
Introduction: Historical perspective (3)
 Next
generation of collider experiments pushing the limits of
the technology
• High radiation environment prevent usage of gas detectors near
interaction point (r<1m)
• New developments in radiation-hard silicon and electronics allow
use of silicon strip devices for r>20cm
• Silicon pixel devices to be used for r<20cm
• Reduced cost of silicon and electronics allowing large area
detectors
HEP silicon detector technology has greatly benefited from
the revolutionary progress in the microelectronics industry
(large area silicon wafer processing, CCDs, CMOS devices,
radiation hard processes, high density interconnects...)
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
7
Introduction: Types of silicon detectors
 Strip
•
•
•
•
•
devices
High precision (< 5m) 1-D coordinate measurement
Large active area (up to 10cm x 10cm from 6” wafers)
Inexpensive processing (single-sided devices)
2nd coordinate possible (double-sided devices)
Most widely used silicon detector in HEP
 Pixel
devices
• True 2-D measurement (20m pixel size)
• Small areas but best for high track density environment
 Pad
strip
pixel/pad
devices (“big pixels or wide strips”)
• Pre-shower and calorimeters (charge measurement)
 Drift
devices
drift
• Just starting to be used
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
8
Silicon strip devices: Principles of operation (1)
Although many of the concepts apply to all 4 types of silicon devices, we will
concentrate primarily on silicon strip devices.
 Basic
motivation: charged particle position measurement
• Use ionization signal (dE/dx) left behind by charged particle passage
+ __
+
+ __
+
Note: there is also non-ionizing energy
losses e.g. displacement of lattice
atoms, this is the mechanism of
radiation damage to be discussed later.
• Use the drift chamber analogy: ionization produces electron-ion pairs,
use an electric field to drift the electrons and ions to the oppositely
charged electrodes.
• In a solid semiconductor, ionization produces electrons-hole pairs. For
Si need 3.6 eV to produce one e-h pair. In pure Si, e-h pairs quickly
recombine  need to drift the charges to electrodes … but how?
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
9
Principles of operation (2)
 p-n
junction (diode)
• Exploit the properties of a p-n junction to collect the ionization charges
p
+
+
+
+
+
+
+ –
+
+
+
+– + ++
In a p-type semiconductor,
positive free charge carriers
(holes) are obtained by adding
impurities of acceptor ions like
Boron (type III in the periodic
table, having 3 valence electrons,
so in the silicon lattice has 1
acceptor electron site).
Alan Honma

–
+

–

–
–
–


–
–
+
n
In an n-type semiconductor,
negative free charge carriers
(electrons) are obtained by adding
impurities of donor ions like
Phosphorus (type V in the periodic
table, having 5 valence electrons, so
in the silicon lattice has 1 donor
electron).
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
10
Principles of operation (3)
 p-n
When brought together to form
a junction, there appears a
gradient of electron and hole
densities resulting in a
diffusive migration of majority
carriers across the junction.
The migration leaves a region
of net charge of opposite sign
on each side, called the spacecharge region or depletion
region (depleted of charge
carriers). The electric field set
up in the region prevents
further migration of carriers.
Alan Honma
p
junction (diode) - continued
+
+
++ +
+
+
+
+
+– + +
–
n


–
+

–


–
–
–


–
–
+
Dopant
concentration
Space charge
density
Carrier
density
Electric
field
Electric
potential
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
11
Principles of operation (4)
 p-n
junction (diode) - continued
• In the depletion region, e-h pairs won’t as easily recombine but will
drift away from each other due to the field.
• If we make the p-n junction at the
surface of a silicon wafer with the bulk
being n-type (you could also do it the
opposite way), we then need to extend
the depletion region throughout the n
bulk to get maximum charge collection.
• This can be achieved by applying a
reverse bias voltage. Remember, this is
a diode, a forward bias would result in
current flow.
p
p
p
n
–
h+ e-
+
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
12
Principles of operation (5)
 Properties
of the depletion zone
• Depletion width is a function of the bulk
resistivity , charge carrier mobility  and the
magnitude of the reverse bias voltage Vb:
w=
2Vb
–
Vb
+
Depletion zone
w
d
undepleted zone
where  = 1/qN for doped materiel and N is the doping concentration
(q is always the charge of the electron)
• The voltage needed to completely deplete a device of thickness d is called
the depletion voltage, Vd
Vd = d2 / (2)
• Thus one needs a higher voltage to fully deplete a low resistivity material.
• One also sees that a higher voltage is needed for a p-type bulk since the
carrier mobility of holes is lower than for electrons (450 vs 1350 cm2/ V·s)
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
13
Principles of operation (6)
 Properties
of the depletion zone (cont)
• The capacitance is simply the parallel plate capacity of the depletion
zone. One normally measures the depletion behaviour (finds the
depletion voltage) by measuring the capacitance versus reverse bias
voltage.
C=A
 / 2Vb
capacitance vs voltage
1/C2 vs voltage
Vd
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
14
Principles of operation (7)
 Charge
collection
• Need to isolate strips from each other
and collect/measure charge on each
strip  high impedance bias
connection (resistor or equivalent)
• Usually want to AC couple input
amplifier to avoid large DC input
currents
• Both of these structures are often
integrated directly on the silicon sensor.
Bias resistors via deposition of doped
polysilicon, and capacitors via metal
readout lines over the implants but
separated by an insulating dielectric
layer (SiO2 , Si3N4). more on this later...
Alan Honma
–
+
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
h+ e-
15
Principles of operation (8)
 Magnitude
of collected charge
• Usually specified in terms of
minimum ionizing deposition:
Most probable charge ≈ 0.7 mean
Mean charge
dE/dx)Si = 3.88 MeV/cm, for
300m thickness  116 keV
This is mean loss, for silicon
detectors use most probable loss
(0.7 mean)  81 keV
3.6eV needed to make e-h pair
Max collected charge  22500 e
(=3.6fC)
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
16
Principles of operation (9)
 Charge
collection time, diffusion
• Drift velocity of charge carriers v=E, so drift time, td = d/v = d/E
• Typical values: d=300 m, E= 2.5kV/cm, e= 1350 cm2 / V·s, h= 450
cm2 / V·s, so td(e)= 9ns , td(h)= 27ns
• Diffusion of charge “cloud” caused by scattering of drifting charge
carriers, radius of distribution after time td:
=
2Dtd , where D is the diffusion constant, D=kT/q
• Same radius for e and h since td  1/
• Typical charge radius:  ≈ 6m, could
exploit this to get better position resolution
due to charge sharing between adjacent
strips (using centroid finding), but need to
keep drift times long (low field).
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
17
Principles of operation (10)
 Double-sided
detectors
Obvious question: why not get a 2nd coordinate
by measuring the position of the (electron)
charge collected on the opposite face?
p
p
p
n
• This is possible and is often done but is not as simple as it might seem.
• Problem: unlike the face with the p-strips, nothing prevents charge to
spread horizontally on the back face.
I did not mention that in order to have the same potential on the entire back surface
and to make good electrical contact, one usually makes the back surface even more
highly doped n-type than the bulk. Then one puts an aluminium layer on top of that
to give an assured low resistance contact. By make highly doped n-type strips rather
than a uniform surface, and making the electrical contact to these strips, one can
make the field lines go to the strips, hence localize the charge. The n-strips are
usually oriented orthogonal to the p-strips to get the optimum 2nd coordinate.
However, in some cases a non-orthogonal stereo angle is used.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
18
Principles of operation (11)
 Double-sided
detectors (cont)
n-strips alone are still not sufficient to isolate the charge due
to an electron accumulation layer effect. This effect is due to
the presence of electrons at the Si-SiO2 layer between the nstrips (even if one avoids putting an oxide layer there, one
would form on its own if exposed to air). The electrons
accumulate at this surface since they are the majority
carriers. In general one puts an oxide over the silicon
between strips in order to passivate (protect) the surface.
p+
Highly doped regions are
usually denoted with a +
superscript.
• Put p-strips in between the n-strips.
• Put “field plates” (metal over oxide) over the n-strips and
apply a potential on the plates to repel the electrons.
Alan Honma
p+
n-bulk
n n n
To “break” the accumulation layer one can:
Both of these methods have been successfully used to isolate
the n-strips
p+
n-bulk
n n  n
p+
p+
n-bulk
n n  n
+
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
+
+
19
Principles of operation (12)
 Other
issues (1): leakage currents
Two main sources of (unwanted) current flow in reversed-biased diode:
• Diffusion current, charge generated in the undepleted zone adjacent to
the depletion zone which diffuse into the depletion zone (otherwise they
would quickly recombine)
The diffusion current should be negligible in a fully depleted device due to the
very small undepleted regions
• Generation current Jg, charge generated in the depletion zone by
defects or contaminants
Jg  exp(-b/kT) Exponential dependence on temperature due to thermal
dependence of e-h pair creation by defects in bulk. Rate
is determined by nature and concentration of defects.
The generation current is the major contribution to the leakage current in a typical
silicon strip device. Large leakage currents can result in high read-out noise. Thus high
purity, low defect devices are desirable. Temperature is also a major factor.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
20
Principles of operation (13)
 Other
issues (2): surface currents and edge effects
We have treated the silicon strip device as having infinite area, but it has edges.
What happens at the edges?
Single guard ring structure
• Voltage drop between biasing ring and edge,
top edge at backplane voltage.
• Typically n-type implants put around edge of
the device and a proper distance maintained
between p bias ring and edge ring.
• Usually one or more “guard” rings (often left
floating) to help assure continuous potential
drop over this region.
• Defects or oxide charge build-up in this region
could lead to additional leakage current
contributions.
Alan Honma
Multi-guard ring structure
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
21
Principles of operation (14)
 Other
issues (3): Breakdown
Example of breakdown:
Ileak vs Vbias
• If one increases the bias voltage,
eventually the field is high enough to
initiate avalanche multiplication, charge
carriers have enough energy to produce
more e-h pairs. This usually occurs around
30V/m (compared to a typical operating
field of <1V/m). Local defects and
inhomogeneities could result in fields
approaching the breakdown point.
• Breakdown can occur through the bulk, at
the edge regions (usually surface
breakdown), and also between any
Good sensor design (edge regions and
structure dimensions) as well as high
structures with sufficiently different
quality processing needed to avoid
potentials.
breakdown problems.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
22
Principles of operation (15)
 Other
issues (4): Strip defects
• “Noisy” strips: usually high DC leakage current but sometimes seen
as large fluctuations in current. Can be due to defects, damage or
incorrect processing.
• Shorts between strips and from strip to other structures (biasing ring).
• “Opens”: interruption of strip or no contact between metal and implant.
 Other
•
•
•
•
Alan Honma
strip properties of note:
Interstrip capacitance (charge loss, increased noise)
Interstrip resistance (charge loss, increased noise)
Capacitance to the backplane (charge loss , increased noise)
Line resistance for metal and/or implant (increased noise)
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
23
Performance (1)
 Position
resolution: strip pitch and read-out pitch
If one treats the detected charge in a binary way (threshold discrimination), the
resolution is simply:
 = p / 12 , so for a typical strip pitch of 50m, get  = 7.2m.
As mentioned earlier, if the charge distribution is shared between adjacent strips,
can use centroid finding to improve this resolution. However, since typical charge
distribution sizes are of order 5-10 m this implies quite fine strip pitch. In fact it
is not practical to make sensors of pitch less than 20m and most are greater.
Test devices have been made that have achieved  < 3.0m (using read-out
pitch of 25 m), this is near the limit on precision determined by diffusion and
statistical fluctuations of the ionizing energy deposition.
Read-out electronics pitch limit is 50m and time/cost constraints often argue for
even larger read-out pitches. Fortunately there is a trick to preserve resolution
with larger read-out pitch...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
24
Performance (2)
 Position
resolution: capacitive charge division
If one reads out only every nth strip but preserves the signal magnitude, the charge
gets shared such that the centroid resolution is nearly that obtained by reading out
every strip. The limitation is that some signal is lost (capacitive coupling to the
backplane) and noise is a bit higher (more input capacitance) and one loses two
track separation capability.
This is clearly an economic solution in the case of low occupancy and has been
used extensively. It does require a good signal/noise ratio, our next topic.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
25
Performance (3)
 Signal
to noise ratio (S/N)
• Why is it important?
noise distribution
Landau distribution
with noise
Landau distribution has significant
low energy tail which becomes even
lower with noise broadening.
One usually has low occupancy in silicon sensors  most channels have no
signal. Don’t want noise to produce fake hits so need to cut high above noise tail
to define good hits. But if too high you lose efficiency for real signals. The
centroid determination is aalso degraded by poor signal to noise.
 Signal
• Basic signal produced is ≈22500e
• Typical losses of 5-10% depending on the nature of the chosen
electrical network (AC coupling capacitor, stray capacitances and
resistances) and front-end electronics.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
26
Performance (4)
 Noise
• Usually expressed as equivalent noise charge (ENC) in units of
electron charge e. Here we assume the use of a CR-RC amplifier
shaper circuit (explained later) as is most commonly used.
• Main sources:
– Capacitive load (Cd ). Often the major source, the dependence is a function of
amplifier design. Feedback mechanism of most amplifiers makes the amplifier
internal noise dependent on input capacitive load. ENC  Cd
– Sensor leakage current (shot noise). ENC  √ I
– Parallel resistance of bias resistor (thermal noise). ENC  √( kT/R)
– Total noise generally expressed in the form (absorbing the last two sources into
the constant term a): ENC = a + b·Cd
– Noise is also very frequency dependent, thus dependent on read-out method
• Implications on detector design:
– Strip length, device quality, choice of bias method will affect noise.
– Temperature is important for both leakage current noise (current doubles for
T≈7˚C) and for bias resistor component
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
27
Performance (5)
 Example
of noise
• Some typical values for LEP silicon strip modules (OPAL):
– ENC = 500 + 15 ·Cd
– Typical strip capacitance is about 1.5pF/cm, strip length of 18cm so
Cd=27pF
so ENC = 900e. Remember S=22500e
 S/N ≈ 25/1
• Some typical values for LHC silicon strip modules (CMS):
– ENC = 425 + 64 ·Cd
– Typical strip capacitance is about 1.2pF/cm, strip length of 12cm so
Cd=14pF
Capacitive term is much worse for LHC in large
so ENC = 1300e.
 S/N ≈ 17/1
 Common
part due to very fast shaping time needed (bunch
crossing of 25ns vs 22s for LEP)
mode noise: “noise” common to many or all channels in the
read-out chip, usually “pick-up” rather than noise, which is usually considered a
random process.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
28
Radiation damage (1)
In many of the operating experiments and those in construction, the radiation
environment will be such that the properties of the silicon strip detectors will be
directly altered by radiation damage. We will look at some of these effects. Most
issues apply to all types of silicon detectors (not just strips). Point defect
 Non-ionizing
energy loss (NIEL)
• Most serious for silicon strip devices is lattice
displacement damage of silicon atoms
(atomic displacement, nuclear interactions)
• For EM radiation need E>250KeV (low
probability), produces point defects
• For n and charged hadrons, damage starts at
low energy, can cause a large region of
damage. This is non-ionizing energy loss.
Cluster damage
Thus hadron collider (FNAL, RHIC, LHC) and high intensity hadron beam fixed
target experiments are most at risk.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
29
Radiation damage (2)
• Damage creates large numbers of new donor and acceptor states.
– Change of charge density in space-charge (depletion) region.
– More generation-recombination centres  increased leakage current.
– New energy levels available to trap the carriers (lowered mobility).
 Effects
on depletion voltage
• n-type silicon becomes increasing p-type until the substrate undergoes
type inversion, and then becomes increasingly p-type with further
irradiation. Note: p-type simply become more p-type.
• Since depletion voltage for a p+-n silicon
Depletion voltage versus fluence
device goes as: Vdep  1/  Neff
– Neff , the effective doping concentration, the
charge density in the depletion region
• The change of Neff as a function of the
fluence  (integrated dose) is shown.
Thus the depletion voltage also decreases
until inversion and then increases.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
30
Radiation damage (3)
Note:  usually quoted as the fluence giving damage equivalent to the fluence of 1
MeV neutrons (in particles per unit area) since particle types have different levels of
damage. Thus one must take into account the damage factor corresponding to the
type of radiation received.
• Interesting effect: after irradiation, the
observed damage (of all 3 types) is found to
diminish, the rate of this “healing” is highly
temperature dependent. The effect is called
annealing and is in part due to true annealing,
the repair of lattice defects. Annealing occurs
faster at higher temperatures.
• But for Neff, two annealing effects: “beneficial”
with short time scale, and “reverse” annealing
with long time scale. Reverse annealing
causes damage to increase!
Alan Honma
Change in Neff vs annealing time
beneficial
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
reverse
31
Radiation damage (4)
• Annealing effects lead to the
following situation for a running
silicon detector in LHC:
– Must keep the detector cold (-10˚C
or less) most of the time to avoid
reverse annealing.
– Can allow a short period at 20˚C
after each years run for beneficial
annealing.
Note also that choice of resistivity effects
final Vdep after irradiation.
These bulk damage effects are only significant at
fluences of  > 1012 n/cm2. Work is ongoing on
methods to reduce these effects (oxygenated Si).
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
32
Radiation damage (5)
 Effects
on leakage current
• Leakage current as function of fluence:
Ileak = ,  is known as the damage constant
• For Ileak there is only beneficial and no reverse annealing effect.
• Thermal runaway: A bad side-effect of the increased leakage
current is the danger of thermal runaway. This effect consists of the
irradiated device heating up from resistive heating due to the
increased leakage current. If this heat cannot be evacuated
efficiently, the increased heat will lead to higher leakage current
(since it is strongly dependent on the temperature). This can
quickly run away uncontrollably.
 Effects
on charge collection
• The increased number of trapping states in the depletion region
leads to a decrease of charge collection (signal). The magnitude of
the effect is about a 10% loss of signal for  = 21014 n/cm2.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
33
Radiation damage (6)
 Damage
from ionization energy loss
• Bulk damage from ionization is negligible
• Surface damage can be significant
• Main problem in silicon is increased positive charge accumulation
at oxide interface. This affects interstrip capacitance (noise factor),
breakdown behaviour, and other structures depending on nearsurface effects (isolation strips, biasing structures).
 Summary
•
•
•
•
of main radiation damage effects for sensors
Increase of leakage current (noise, thermal runaway)
Decrease of charge collection (signal
Increase of bias voltage needed (possible breakdown)
Increase of capacitance (noise)
You must choose your device parameters appropriately and one must consider
the evolution of the device with radiation.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
34
Sensor fabrication (1)
Terminology note: The term “sensor” will denote a silicon strip device made
from a single wafer, as the term “detector” often refers to the ensemble of
sensors used in an experiment. Wafer always refers to the circular substrate of
silicon from which the device is built.
The production steps required to produce a silicon strip sensor are very
similar to those used to produce many of the integrated circuits (“chips”)
used in everyday electronics (memory chips, processors). For the steps
listed below, many are done by separate companies, although in some
cases a single company has the in-house capability for all steps.
 Silicon
crystal (“ingot”) production
 Slicing into wafers, lapping, etching and polishing
 Wafer processing
 Dicing (cutting) sensor from wafer
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
35
Sensor fabrication (2)
 Crystal
production (Float zone method)
1)
Start with very pure quartzite sand (usually from an Australian
beach!), clean and further purify by chemical processes. Melt,
and add the tiny concentration of phosphorus (boron) dopant to
make n(p) type silicon (remember, dopant concentration
determines resistivity). Pour in mold to make a polycrystalline
silicon cylinder.
2)
Using a single silicon
crystal seed, melt the
vertically oriented
cylinder onto the seed
using RF power:
Alan Honma
Single
crystal
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
36
Sensor fabrication (3)
 Crystal
production (2)
3)
Result is a single crystal
of silicon (“ingot”)!
4)
Alternative method (widely used for microelectronics grade
silicon wafers): CZ method invented by Czochralski. “Draw”
out the single crystal from a crucible of liquid silicon using a
seed. However, high resistivity silicon is more reliably obtained
with FZ method. CZ method can more easily obtain larger
diameter ingots.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
37
Sensor fabrication (4)
 Slicing,
1)
lapping, etching and polishing
Ingot is sliced into wafers of
thickness 300-500m with
diamond encrusted wire or disc
saws.
2) Lapping (grinding away large
imperfections), etching (more
removal of impurities and
imperfections), and polishing
are needed to attain the desired
wafer thickness and to ensure a
surface with minimal defects.
Alan Honma
diamond
disc saw
lapping
machine
polishing
machines
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
38
Sensor fabrication (5)
 Wafer
1)
processing (1)
n-Si
SiO2
2)
3)
Start with n-doped silicon wafer,
 ≈ 1-10 kcm
Oxidation at 800 - 1200C
Photolithography (= mask align + photo-resist layer + developing)
followed by etching to make windows in oxide
UV light
etch
mask
Photo-resist
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
39
Sensor fabrication (6)
 Wafer
processing (2)
B
Doping by ion implantation (or by diffusion)
4)
As
5)
p+
Annealing (healing of crystal lattice) at 600 C
p+
n+
Al
6)
Photolithography followed by Al metallization
over implanted strips and over backplane
usually by evaporation.
 Most simple DC-coupled silicon strip detector
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
40
Sensor fabrication (7)
 Wafer
n+
processing: double-sided sensors
n+
n+
7)
p+
p+
8)
Al
9)
For double-sided devices, “back” side must
also be polished. Implant n+ strips instead of
full backplane.
Add p+ “blocking” strips (they often don’t
need any biasing connection). Note the many
extra photolithographic steps needed.
Al metallization over implanted back-side
read-out strips.
 Most simple double-sided silicon strip sensor
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
41
Sensor fabrication (8)
 Wafer
processing: strip biasing structures
Note: cut is now parallel to strip instead of perpendicular
Al contact to common bias bus
polysilicon
Polysilicon resistor biasing: doped,
non-single crystal (poly) silicon using
length to width aspect ratio to get
desired resistance.
p+
n+
gap
p+
Al contact to common bias bus
p+
gate electrode
p+
Bias bus
p+
poly
resistor
p-strip
“Punch-through” biasing: gap between end of p-strip and a
p-type implanted bias ring. Voltage difference between two
p implants needed for current flow (typically a few volts).
“Effective” series resistance is very high for low currents.
FoxFET (Field oxide FET) biasing: same as punch-through
but with a gate electrode to control voltage properties of gap.
 Same or similar techniques to bias backside strips of double-sided
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
42
Sensor fabrication (9)
 Wafer
processing: integrated AC coupling capacitors
In many cases, cannot tolerate DC currents into read-out amplifier, so a series AC
coupling capacitor is needed. Need a large capacitance so as not to lose the small
signal charge (need >100pF), but often have very little space.
Use sandwich of aluminium strip over oxide
layer over p-strip to make the capacitor. It
turns out that an oxide thickness of 0.1-0.2m
is required. Same technique can be used on
backside of double-sided device.
AC-coupled polysilicon resistor
biased sensor
Al read-out strip
Controlled
oxide
thickness
p+
n+
Problem: very difficult to make perfect oxide insulator over such a large surface.
Most common defects are called “pinholes”, a short (or low resistive connection)
through the oxide. A technique of putting an additional very thin layer of silicon
nitride (Si3N4) has been used successfully to combat this problem.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
43
Sensor fabrication (10)
 Wafer
processing: double-metal layers
It is sometimes the case that one wants to route the signals differently from the metal
lines on or over the strips, for instance to read out the signal of the n-strips of a
double-sided sensor which are oriented orthogonal to the p-strips. To route those
strips to the same edge of the sensor one could make another metal layer with
orthogonally oriented strips above an insulation layer. One then needs “vias”,
electrical contact holes in the insulation layers just where the appropriate lines cross.
Lower
metal
layer
Upper
metal
layer
Insulation layer
Double-metal layer
construction
Vias
In principle no problem. In practice one has to worry about “pinholes”, failed vias,
the increased capacitance, and cross-talk to all other channels.
Watch out for too many processing steps
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
44
Sensor fabrication (11)
 Wafer
processing: Passivation
• Passivation is the application of a layer of SiO2 or other suitable
material (polyimide is very common) to protect the surfaces not
needing to be electrically contacted from physical damage, chemical
interactions, and other environmental effects (humidity).
 Wafer
processing: Cleaning
• A cleaning step is usually performed to remove any residual
chemicals left from the processing steps.
 Wafer
processing: Testing
• In general device testing is then performed in order to see the quality
of the devices on the wafer. This is often done prior to cutting out the
individual devices because if many device are made on a single
wafer, much time will be spent aligning each device on the probe
station.
• Test structures are often included on the wafer design in order to test
specific properties of the processing and design (see next slide).
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
45
Sensor fabrication (12)
 Wafer
processing: Dicing
CMS silicon strip sensor from 6” wafer
• Individual sensors are usually cut
from the wafer using a diamond
disc saw. Width of cut is about 50
microns.
• A “scribe and break” method has
also been used.
• As dicing should not effect most
structures (except for the edges),
only limited (e.g. total leakage
current) or no further testing is
usually performed.
Test structures
 Sensors ready to be packed and shipped. Not without danger: have
heard of many instances of destroyed sensors after shipping!
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
46
Construction of detector modules (1)
We consider here the “module”, the basic building block of a silicon tracking
detector. Many of the issues below also apply to the support infrastructure
(mechanics, cooling, electrical) also contained in the active detection volume.
 Module
concept
Modular design: try to make identical sub-units. Units consist of:
• mechanical support structure
• sensors
• front-end electronics and signal
routing (connectivity)
 Constraints
• Low mass (multiple scattering)
• Rigid, strong
• Low coefficient of thermal
expansion (CTE)
• Good thermal conduction
Alan Honma
•
•
•
•
Restricted space
Low cost (!)
Radiation hard
Works at low temperatures
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
47
Construction of detector modules (2)
 Mechanical
support structure (frame)
Exotic materials often needed to meet the conflicting requirements:
• Carbon-fibre, graphite composite
materials: low mass, high strength, high
thermal conductivity, low CTE, often
used in aircraft industry (cost factor).
• Hexcel, foams used for rigidity
Module frame in
graphite
• For applications where the support infrastructure is in the active
detection volume (all collider experiments and some fixed target)
 minimize material. Use low Z metals (beryllium, aluminium) for
beam pipe, support fixtures, thermal contacts and cooling system
when possible.
• Components are usually glued together.
• Difficulties come from need for radiation hardness, for operation at
large temperature extremes and for efficient cooling of electronics.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
48
Construction of detector modules (3)
 Sensor
design choices
Sensor design must first follow physics requirements, still many choices:
•
•
•
•
Geometrical shape
Thickness
Read-out and implant pitch
p or n bulk silicon, resistivity
•
•
•
•
Double-sided or single-sided
Type of biasing structure
AC or DC coupling
Double-metal read-out?
In many cases there are conflicting design trade-offs between these
choices. One finds that economics (limited project budget) often forces
decision direction. Examples of trade-offs:
Choice
Pro
Double-sided sensor Less material for two
read-out coordinates
500m thickness
Alan Honma
More signal
Con
Processing cost about 3x
that for single-sided
Higher bias voltage
required, more material
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
49
Construction of detector modules (4)
 Front-end
electronics and connectivity (1)
• Often several sensors have their strips connected together in series (saves on
electronics channels, OK when occupancy is low) to make multi-sensor
modules. These connections are done by wire bonding (more on this later).
NOMAD module: 12 sensors serially
chained to read-out on one end!
• To connect sensor to read-out chips, simplest scheme is direct wire bonding.
This is rarely practical unless pitch is very similar.  Use a “pitch adapter”, fanout circuit on glass or other substrate. This matches the sensor pitch to that of
read-out chip.
Read-out chip positions
Aluminium line on circuit
sensor
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
50
Construction of detector modules (5)
 Front-end
electronics and connectivity (2)
• Front-end read-out electronics are usually in the form of ASIC (application
specific integrated circuits) chips mounted on a hybrid circuit that provides
power lines, control signals and read-out connectivity. This hybrid circuit has
often been made on a ceramic substrate with thick-film gold deposition
techniques.
400 front-end ASICs on 8” wafer (IBM)
Ceramic hybrid
APV25 (CMS)
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
51
Construction of detector modules (6)
 Front-end
electronics and connectivity (3)
• For applications where the electronics is in the
active detection volume  low Z materials
wherever possible: Al instead of Cu, kapton
rather than glass, ceramics or FR4 (standard
circuit board material).
• Recent developments with copper/kapton
circuits have made them a popular low mass
(and low cost) alternative.
ATLAS flexible kapton hybrid circuit. Note also
that hybrid is mounted directly over one of the two
chained silicon sensors. A thermal challenge!
• For connection of front-end to back-end electronics (signals, controls, power,
monitoring), if not in active volume, no problem. If in active volume, this can be
the largest contribution to the material budget (low noise electronics need good
grounding and low impedance power connections  thick conductors).
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
52
Construction of detector modules (7)
 Assembly
of modules into a detector
• Modules are mounted onto a
low-mass structure. Good
thermal contact with cooling
system required. Finally, cabling
of services.
Carbon fibre
cylinder
Aluminium cooling tubes
CMS prototype structure
Alan Honma
ALEPH 1998
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
53
Front-end electronics (1)
The final performance result of the silicon detector system is directly linked to the
optimal choice of amplifier and read-out method as well as to the sensor design. In
addition, the read-out electronics is often more difficult to fabricate than the
sensors and often has caused significant project delays. It is worthwhile to look in
more detail at some of the more relevant design choices and methods of
implementation of the front-end electronics.
 Review
of signal input to the front-end (FE) electronics
• signal collection time: < 30ns
• signal magnitude: 22500e for one MIP(minimum ionizing particle)
 Noise
contributions from:
• Cdet
• Rbias
• Ileak
Cbypass
Rseries
Rbias
Ileak
Alan Honma
Amplifier effective input load
Vbias
Cdet
Ccoupling
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
54
Front-end electronics (2)
 Typical
amplifier circuit (CR-RC shaper):
preamp
differentiator
High-pass filter
 Choice
integrator
Low-pass filter
of amplifier design will be determined by:
• Bunch crossing rate  differentiation/integration time constants
• Types of particles (MIP depositions or more?)
• Density of particles (2 track resolution, occupancy)
 After
amplifier, must decide read-out architecture:
• Binary - hit / no hit (comparator circuit)
• Digital - fast ADC conversion of input charge
• Analogue - send out analogue level proportional to input charge
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
55
Front-end electronics (3)
• Comparison of read-out methods
method
Pro
Con
Binary (bipolar)
Fast, rad hard, possibly
cheaper, minimal data out
Non-standard process, hard
to debug, pulse info lost
Digital(CMOS)
Not subject to analogue
output problems, have
pulse info, low data vol.
Most complex, power
consumption,wait for
conversion
Analogue(CMOS)
Least manipulation of
data, have pulse info
Have to deal with analogue
signal (noise, gain), high data
volume
• Other issues/choices: multiplexing, pipelining, zero suppression,
baseline subtraction, waveform transforms (“deconvolution”), electrical
or optical signal transport, radiation hardness, power consumption, cost.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
56
Front-end electronics (4)
 Technology
issues
• Latest 0.25m CMOS technology proven to be radiation hard, a major
impediment to previous CMOS devices. This has strengthened the
CMOS position for silicon read-out chips since this is an industry
standard and is much less expensive than custom CMOS or bipolar.
• Still there are trade-offs between CMOS and bipolar in terms of power
consumption, speed and manufacturability.
• There are also practical considerations for any technology choice:
– Difficulty of design and predictability of outcome
– Turn-around for prototyping and series production
– High cost of prototyping
 Other
ASICs often needed close to the FE chips:
• Multiplexers, controllers, buffer/drivers, optical converters, timing and
triggering. Some of these are standard chips, some are highly custom.
• Many of the same choices and issues here as for FE chip.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
57
Front-end electronics (5)
 Other
ASICs (cont):
• Standard packaging of ASICs recommended (as compared to bare die)
–
–
–
–
 Hybrid
Not expensive, industry standards for bonding and packaging
Less handling problems
Easier testing
Easier mounting (standard surface mount component)
circuit technology options “standard”
• PCB (G10/FR4) - cheap, many producers
• Thick film gold on ceramic (alumina, aluminium nitride, beryllia) expensive but reliable
• Copper/kapton, flex circuits - smaller feature sizes than others, getting
very inexpensive due to consumer electronics (cell phones, etc)
• Mix of kapton and standard PCB - easy to merge these technologies
• The hybrid circuit must also adapt to the mechanical and thermal
properties of the module which in many cases is exceedingly difficult.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
58
Front-end electronics (6)
 Connectivity
technology: some of the possibilities
• High density interconnects (HDI):industry standard and custom cables,
usually flexible kapton/copper with miniature connectors.
• Soldering still standard for surface mount components, packaged chips
and some cables. Conductive adhesives are often a viable low
temperature alternative, especially for delicate substrates.
• Wire bonding: the standard method for connecting sensors to each
other and to the front-end chips. Usually employed for all connections
of the front-end chips and bare die ASICs. A “mature” technology (has
been around for about 40 years).
OPAL (LEP) module
~200 wire bonds
Alan Honma
4 x 640 wire bonds
Total ~2700 wire bonds
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
59
Front-end electronics (7)
• Wire bonding (cont)
Electron micrograph of bond “foot”
– Uses ultrasonic power to vibrate needle-like
tool on top of wire. Friction welds wire to
metallized substrate underneath.
– Can easily handle 80m pitch in a single row
and 40m in two staggered rows (typical FE
chip input pitch is 44m).
– Generally use 25m diameter aluminium
wire and bond to aluminium pads (chips) or
gold pads (hybrid substrates).
– Heavily used in industry (PC processors)
but not with such thin wire or small pitch.
View through microscope of wire bonds
connecting sensor to fan-out circuit
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
60
Front-end electronics (8)
 Connectivity
technology: some of the possibilities (2)
• TAB (tape automated bonding): variant
to wire bonding, using same machines
but different tool to make the “bond”. In
this case a thin metallized kapton (or
other thin flexible substrate) finger is
welded to a substrate. A new and as
yet not very common technique.
• Bump bonding, flip-chip technique:
similar to soldering but with very fine
pitch connections. One chip is “welded”
to another face to face with points of
connections having “bumps” of solderlike metal or conductive adhesive.
Essential technique for pixel detector
connections where a dense array of
connections is required.
Alan Honma
Metallized
kapton
finger
Read-out chip
Solder
bump
Pixel detector chip
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
61
Front-end electronics (9)
 Other
“downstream” data acquisition electronics
• Data transmission (optical or electrical  grounding, material budget
issues)
• ADC conversion (if not already done)
• Multiplexing, triggering, buffering, ...
These electronics are often similar or identical to those for other
detector systems in an experiment.
 Other
•
•
•
•
•
Alan Honma
vital electronic systems needed for silicon detector
Control system
Monitoring system
Power supply system
Radiation protection system (sometimes must be very fast: <1s)
Safety system (interacting with all the above): usually considered part
of “slow controls”, this system must have a very fast reaction time.
Example: fast reaction to cooling failure in LHC (thermal runaway).
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
62
Silicon detectors in HEP experiments
Silicon detectors have become a standard part of HEP experiments
needing high resolution tracking information:
• FNAL p-pbar collider
– CDF(strip)
– D0 (strip)
– BTeV (pixel, strip)
• B-factory colliders
– Babar (strip)
– Belle (strip)
– Cleo-3 (strip)
• HERA ep collider
– H1 (strip)
– Zeus (strip)
Alan Honma
• RHIC heavy ion
collider
–
–
–
–
STAR (strip, drift)
PHENIX (strip, pad)
PHOBOS (strip, pad)
BRAHMS (strip)
• Fixed target
–
–
–
–
HERA-B (strip)
HERMES (strip)
COMPASS (strip)
others
• Space
–
–
–
–
–
–
AMS (strip)
GLAST (strip)
PAMELA (strip)
AGILE (strip)
NINA (strip)
others
• LHC pp collider
–
–
–
–
ALICE (strip, drift, pixel)
LHCb (strip)
ATLAS (strip, pixel)
CMS (strip, pixel, pad)
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
63
Usage of silicon in current experiments
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
64
Cleo III
An interesting example ...
Silicon microvertex
61 half ladders, 447 silicon Wafers
Layer 1 = 16cm long
Layer 4 = 53cm long
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
65
Cleo III
• Double-sided n-type silicon wafer by
Hamamatsu
• 2 x 511 channels, sensor 53.2 x 27 x 0.3 mm
• Strip spacing 50 m r-f, 100 m z.
• DC coupled read-out strips
• p-side (z) is double metal read-out.
Hourglass design of metal layer overlap.
• n-side (r-f) with p-stop isolation, atoll
design, p-stops punch-through biased.
p-side (z)
n-side (r-f)
n+
p+
carbon fibre
support cylinder
(0.26% Xo)
CVD Diamond v-beams for mechanical
support of modules
200-300m thick, < 0.1% Xo !
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
66
Cleo III
Very high density flex circuit
between sensor and read-out chip
Bias resistor and AC coupling
capacitors on separate chip
Low noise front-end chip
ENC = 145 e + 5.5 e /pF
Back-end chip: ADC, comparator
BeO substrate
Excellent performance: S/N > 19
However … there seems to be
radiation damage to the silicon.
Low track finding efficiency starting
in inner layer and now getting worse
and spreading outward. Effect not
understood (surface damage??).
 CLEO-c plans to replace silicon
with a low-mass drift chamber!
Alan Honma
Hit Map,Layer 1
wafer
sensor
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
67
CMS
Going to extremes...
The CMS Pixel Vertex
4 107 pixels
Outer barrel
Outer
barrel
 Currently
the Most Silicon
Endcaps
Inner barrel
• Inner 3 layers: silicon pixels
• Rest of tracker: silicon strip
• 2 orders of magnitude more
silicon surface than before
• Most challenging operating
environments (LHC)
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
68
Numbers in CMS Silicon
strip tracker
CMS
 Radiation
environment
• Max:  ≈ 1.6  1014 n/cm2
• This governs choice of many
parameters of the silicon
• All materials must be rad hard
• Must keep entire volume (24 m3!) of
silicon detector cold: -10˚C
• The cold environment introduces
many difficulties for the mechanics
 Sensor
•
•
•
•
Alan Honma
440 m2 of silicon wafers
210 m2 of silicon sensors
24328 sensors
15232 modules
9,648,128 strips (electronics channels)
75,376 read-out chips
26,000,000 wirebonds
14 sensor geometries
Strip length from 9 to 21 cm
Pitch ranges from 80 to 205 m
10 tracking layers
design
Single-sided 300 or 500m thick
p+ strips on n
Integrated AC coupling capacitors
Polysilicon resistor biasing
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
69
CMS
 Module
construction
As simple as possible: CF frame,
1 or 2 sensors, fan-out circuit,
front-end electronics hybrid
Automate as much as possible:
automatic probe station, robotic
precision module assembly system,
automatic wire bonding machines
Module assembly robot: ~ 6 modules/hr
Large-scale but lightweight mechanics
and support infrastructure
Still, it’s not going to be easy...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
70
Other types of silicon detectors: pixel (1)
 Silicon
pixel devices (a very brief and sketchy view)
The benefit of pixel detectors is quite obvious in a high multiplicity
environment: the combinatorial problem of coordinate matching in
single coordinate devices quickly gets out of hand. The first silicon pixel
devices for high energy physics were built from CCD chips. Since then
a variety of different technologies have arisen:
– CCDs (now exist in different varieties)
– Monolithic active pixel sensors (MAPS)
– Hybrid active pixel sensors (HAPS)
• CCD pixel detectors
Derived from the CCDs used for cameras, but need more active
thickness (cameras need just a micron depth to get a good signal). One
needs to grow additional layers of silicon on substrate (called epitaxial
layers) with certain properties in order to get deeper charge collection.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
71
Other types of silicon detectors: pixel (2)
• CCD pixel detectors (2): Still the active depth is usually quite small (typically
15m) so the ionization signal is small. The charge is kept isolated in the pixel
and then shifted as shown:
p channels and gates (MOS structures)
are used to isolate the charge.
By changing the potential on the gates in one out of 3
rows at a time, one can achieve a “bucket brigade”
effect of shifting the charge to the next “well”
without it spreading.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
72
Other types of silicon detectors: pixel (3)
• CCD pixel detectors (3): Due to the small signal, the noise must be kept low
which can be achieved by cooling to about 200˚K for charged particle
detectors. There still remains the problem of reading out the charge. When the
row of charge packets arrive at the edge of the chip, one can buffer and send
the signal out to other chips for further manipulation (convert to binary,
sparsification, etc).
Note that the wells are always alive so you are always subject to collecting
charge even if it comes “out of time”. Also the clocking speed is limited so one
cannot clear out the “event” faster than a certain time. This limitation makes
CCDs unsuitable for high rate applications like general purpose vertex
detection at LHC. However, for lower rate applications (linear colliders, some
fixed target experiments) this is ideal.
The SLD silicon pixel vertex detector: the
first pixel detector in a collider experiment
had 20m x 20m pixels and achieved about
4m resolution.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
73
Other types of silicon detectors: pixel (4)
• Monolithic active pixel sensors (MAPS): This uses a thin active layer like
the CCD (epitaxial layer). Unlike a CCD, this does not shift the charge but
collects it directly on a circuit grown on the pixel surface. Only minimal logic is
in the pixel, so on-chip digitization and sparsification must be done at the edge
of the chip (edge logic). Pixel size can be as small as 20m x 20m. This is a
fairly new technology under active development.
• Hybrid active pixel sensors (HAPS): Basically this is a strip sensor with the
strips further segmented into pixels. In order to read-out the collected charge,
the read-out chip must have the same “pixellation” as the sensor. The read-out
chip is then bump-bonded onto the pixel sensor, the number of connections
(bumps) equal to the number of pixels. The size of the read-out circuit (and
likely limitations in power and heat dissapition) limit the pixel size to about
150m x 150m or larger.
Both CMS and ATLAS are building pixel
detectors following the HAPS scheme.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
74
Other types of silicon detectors: pixel (5)
• An example of a HAPS: ATLAS
Three disk
layers
Three barrel layers
The ATLAS Pixel Vertex
2m2 , 8 107 pixels
MCC
Control chip
Flex
Hybrid
sensor
bumps
FE chip
FE chip
C-C support
ATLAS bump bonded module
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
75
Other types of silicon detectors: pad
 Silicon
pad detectors
• The same principle as strip detectors just
wider and shorter strips. Often the
biasing and read-out lines are routed to
the edge using a double metal layer.
• The only concern is the large input capacitance if one uses large pad
sizes. However, these devices are often used for calorimeter read-out
(ex. ALEPH and OPAL Si-W calorimeters) or high accuracy
electromagnetic calorimeter pre-shower detectors (CMS) in which
case the signals are very large so input capacitance noise is less of
an issue.
• Other uses are in situations not needing high precision but have
unusual geometries (annular) or environments (high radiation) that
may not be possible with other tracking methods (gas tracking
chambers). Reduced cost of silicon has made this more attractive.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
76
Other types of silicon detectors: drift
 Silicon
drift devices
• Both side p-strips put to negative
potential. Electrons drift parallel to
substrate surface to n-pad anode.
• Need voltage divider network for pstrips (like in drift chambers) to
provide a uniform drift field.
p+
p+ p+ p+
p+ p+
n+
p+ p+
p+ p+ p+
p+ p+
• Need to ensure good material uniformity, low defect rates, good
drift field homogeneity, precise voltage dividing on p-strips and
good temperature control.
• Spatial resolutions of 40-50m from the drift time and 20-30m
from the anode segmentation have been achieved.
Has not been used much in HEP but has recently been implemented
for STAR at RHIC and for ALICE at LHC.
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
77
Future trends
• Studies of oxygenated silicon and other extremely rad hard possibilities
for the SuperLHC
• Further development of MAPS pixel devices
• Reducing pixel size of HAPS pixel devices
• Developments in CCD pixel devices: faster, more on-chip processing
• New detection technologies: example “3-D detectors” (S. Parker et al)
n+
p+
- 300 um
+
p n
50 um
Si thickness
Charge collection distance
Depletion voltage
Alan Honma
300- 500m
50-100m
5-10V
depletion
Uses deep reactive ion etching
Good signal after ≈ 2 1015 n/cm2
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
78
References and acknowledgements
• Many excellent references on the subject:
– Semiconductor radiation detectors : device physics / Lutz, Gerhard ; . - Berlin
: Springer , 1999 . - 353 p .
– Vertex detectors : the state of the art and future prospects / Damerell, C J S ;
23rd SLAC Summer Institute on Particle Physics: the Top Quark and the
Electroweak Interaction, Stanford, CA, USA, 10 - 21 Jul 1995 - SLAC, Stanford,
CA, 1997.
– " Silicon Microstrip Detectors ", A.Peisert, in " Instrumentation in High Energy
Physics ", F.Sauli (ed), World Scientific, (1992).
– H. Spieler, “Semiconductor Detectors”, UC Berkeley Physics 198 course
notes, http:///www.-physics.lbl.gov/~spieler
– Nucl. Instr. And Meth., A473 (2001), No.1&2. (Vertex 2000 conference
proceedings).
– Mitsubishi Materials Corporation, website on silicon fabrication,
http://www.msil.ab.psiweb.com/english/msilhist0-e.html
– Semiconductor sensors / Sze, S.M.; New York : Springer, 1994.
• Thanks to
– Speakers at recent conferences (especially Vertex 2001)
– Colleagues in OPAL, CMS, CERN...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
79
Conclusions
 Silicon
•
•
•
•
strip detectors
Built on simple p-n junction diode principle, now a “mature” technology
Widespread use and cost drop thanks to microelectronics industry
Many options and design possibilities
Replaces wire chambers in high radiation
 Other
silicon detectors
• Pixels have replaced strips in region closest to interaction point and
have become the “hottest” area of development in HEP silicon
• Pads devices still useful in calorimetry and lower resolution tracking
• Drift devices are now being used, we will see how well they work
Silicon detectors remain an exciting and interesting field of
development and application for high energy physics experiments.
You are invited to join in...
Alan Honma
NATO Advanced Study Institute, St. Croix US Virgin Islands, 13-24 June, 2002
80