Vivado Hello World Tutorial
Embedded Processor Hardware Design
September 9, 2013
VIVADO TUTORIAL 1
Table of Contents
Requirements .............................................................................................................3
Part 1: Building a Zynq-7000 Processor Hardware ........................................................3
Introduction ................................................................................................................................................................3
Step 1: Start the Vivado IDE and Create a Project .......................................................................................3
Step 2: Create an IP Integrator Design .............................................................................................................5
Customize Instantiated IP ........................................................................................................................................ 9
Use Block Designer Assistance .............................................................................................................................10
Step 4: Generate HDL Design Files ................................................................................................................. 14
Step 7: Implement Design and Generate Bitstream ................................................................................ 15
Step 8: Export Hardware to SDK ..................................................................................................................... 17
Export to SDK...............................................................................................................................................................17
Part 2: Build Zynq-7000 Processor Software .............................................................. 18
Step 1: Start SDK and Create a Software Application ............................................................................. 18
Step 2: Run the Software Application............................................................................................................ 21
Add a Breakpoint .......................................................................................................................................................26
Step 3: Executing the Software ........................................................................................................................ 27
2 VIVADO TUTORIAL
Requirements
The following is needed in order to follow this tutorial:
 Vivado w/ Xilinx SDK (tested, version 2013.2)
 Zedboard (tested, version D)
Part 1: Building a Zynq-7000 Processor Hardware
Introduction
In this part of the tutorial you create a Zynq-7000 processor based design and
instantiate IP in the processing logic fabric (PL) to complete your design. Then you
take the design through implementation, generate a bitstream, and export the
hardware to SDK.
If you are not familiar with the Vivado Integrated Development Environment Vivado
(IDE), see the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).
Step 1: Start the Vivado IDE and Create a Project
1. Start the Vivado IDE (FIGURE 1) by clicking the Vivado desktop icon or by
typing vivado at a terminal command line.
Figure 1: Getting Started Page
VIVADO TUTORIAL 3
2. From the Getting Started page, select Create New Project. The New Project
wizard opens (FIGURE 2).
3. Click Next
Figure 2: Create New Project Wizard
4. In the Project Name dialog box, type the project name and location. Ensure
that Create project subdirectory is checked, and then click Next.
5. In the Project Type dialog box, select RTL Project, then click Next.
6. In the Add Sources dialog box, ensure that the Target language is set to
VHDL, then click Next.
7. In the Add Existing IP dialog box, click Next.
8. In the Add Constraints dialog box, click Next.
9. In the Default Part dialog box select Boards and choose “ZedBoard Zynq
Evaluation and Development Kit”. Make sure that you have selected the
proper Board Version to match your hardware because multiple versions of
hardware are supported in the Vivado IDE. Click Next.
10. Review the project summary in the New Project Summary dialog box before
clicking Finish to create the project.
4 VIVADO TUTORIAL
Step 2: Create an IP Integrator Design
1. In the Flow Navigator, select Create Block Design.
Figure 3: Create Block Design from Flow Navigator
2. In the Create Block Design popup menu, specify a name for your IP
subsystem design.
Figure 4: Create Block Design Dialog Box
VIVADO TUTORIAL 5
3. Right-click in the Vivado IP integrator diagram window, and select Add IP.
Figure 5: Add IP Option
4. Alternatively, you can click the Add IP link in the IP integrator diagram area.
Figure 6: Add IP Link in IP Integrator Canvas
The IP Catalog opens.
5. In the search field, type zynq to find the ZYNQ7 Processing System IP, and
then press Enter on the keyboard.
Figure 7: The IP Integrator IP Catalog
Because you selected the ZedBoard when you created the project, the Vivado
IP integrator configures the design appropriately.
6 VIVADO TUTORIAL
In the Tcl Console, you see the following message:
create_bd_cell -type ip -vlnv
xilinx.com:ip:processing_system7:5.2 processing_system7_1
INFO: [PS7-6] Configuring Board Preset zed. Please wait ......
There is a corresponding Tcl command for all actions performed in the IP
integrator block diagram. Those commands are not shown in this document.
See the Tcl Console for information on those commands.
6. In the IP integrator diagram header, click Run Block Automation.
Figure 8: Run Block Automation on Zync
The Run Block Automation dialog box opens, stating that the FIXED_IO and
DDR interfaces will be created for the Zynq core.
7. Click OK.
Figure 9: Zync7 Run Block Automation Dialog Box
VIVADO TUTORIAL 7
After running block automation on the Zynq processor, the IP integrator
diagram should look as follows:
Figure 10: Zynq Processing System after Running Block Automation
8. Now you can add peripherals to the processing logic (PL). To do this, rightclick in the IP integrator diagram, and select Add IP.
9. In the search field, type gpi to find the AXI GPIO IP, and then press Enter to
add the AXI GPIO IP to the design.
10. Repeat the action, typing axi bram to find and add AXI BRAM Controller,
and typing block to find and add Block Memory Generator. The Block Design window matches FIGURE 11. The relative positions of the
IP will vary.
Figure 11: Block Design after Instantiating IP
8 VIVADO TUTORIAL
Customize Instantiated IP
1. Double-click the Block Memory Generator IP, or right-click and select
Customize Block (FIGURE 12).
Figure 12: Customize Block Option
The Re-customize IP dialog box opens. 2.
2. On the Basic tab of the dialog box, set:
 Mode to BRAM Controller
 Memory Type to True Dual Port RAM
Click OK.
Figure 13: Set Mode and Memory Type
The AXI BRAM Controller provides an AXI memory map interface to the
Block Memory Generator.
VIVADO TUTORIAL 9
3. Connect the Block Memory Generator to the AXI4 BRAM Controller by
clicking the connection point and dragging a line between the IP.
Figure 14: Connected AXI BRAM Controller and Block Memory Generator
The AXI BRAM Controller provides an AXI memory map interface to the
Block Memory Generator.
Use Block Designer Assistance
Block Designer Assistance helps connect the AXI GPIO and AXI BRAM Controller to
the Zynq-7000 PS.
1. Click Run Connection Automation and then select /axi_gpio_1/s_axi to
connect the BRAM controller and GPIO IP to the Zynq PS and to the external
pins on the ZedBoard (FIGURE 15).
Figure 15: Run Connection Automation
The Run Connection Automation dialog box opens and states that it will
connect the master AXI interface to a slave interface.
In this case, the master is the Zynq Processing System IP (FIGURE 16).
10 VIVADO TUTORIAL
Figure 16: Run Connection Automation Message
Click OK.
This action instantiates an AXI Interconnect IP as well as a Proc Sys Reset IP
and makes the interconnection between the AXI interface of the GPIO and the
Zynq-7000 PS.
2. Select Run Connection Automation again, and the /axi_gpio_1/gpio
shown in FIGURE 17.
Figure 17: axi_gpio Selection
The Run Connection Automation dialog box includes options to hook up to
the GPIO port. 4.
3. Select leds_8bits (FIGURE 18).
Figure 18: Select Board Interface Options
VIVADO TUTORIAL 11
4. Click OK. This step also configures the IP so that during netlist generation,
the IP creates the necessary Xilinx Design Constraints (XDC).
5. Click Run Connection Automation again, and select the remaining option
/axi_bram_ctrl_1/S_AXI (FIGURE 19).
Figure 19: axi_bram_ctrl Selection
This completes the connection between the Zynq7 Processing System and the
AXI BRAM Controller.
The IP integrator subsystem looks like FIGURE 20. Again, the relative
positions of the IP can differ slightly.
Figure 20: Zynq Processor System
6. Click the Address Editor tab to show the memory map of all the IP in the
design.
In this case, there are two IP: the AXI GPIO and the AXI BRAM Controller. The
IP integrator assigns the memory maps for these IP automatically. You can
change them if necessary.
12 VIVADO TUTORIAL
7. Change the range of the AXI BRAM Controller to 64K, as shown in FIGURE 21.
Figure 21: axi_bram_ctrl to 64k Range
8. Save your design by pressing Ctrl-S, or select File > Save Block Design.
9. Click the Address Editor tab to make sure that the memory mappings for the
GPIO and BRAM controller have been auto populated.
10. From the toolbar, run Design-Rules-Check (DRC) by clicking the Validate
Design button (FIGURE 22). Alternatively, you can do the same from the
menu by:

Selecting Tools > Validate Design from the menu.

Right-clicking in the Diagram window and selecting Validate Design.
Figure 22: Validate Design Button
The Validate Design Successful dialog box opens (FIGURE 23).
Figure 23: Validate Design Message
11. Click OK.
VIVADO TUTORIAL 13
Step 4: Generate HDL Design Files
You now generate the HDL files for the design.
1. In the Source window, right-click the top-level subsystem design and select
Generate Output Products (FIGURE 24). This generates the source files for
the IP used in the block diagram and the relevant constraints file.
Figure 24: Generate Output Products Option
2. The Manage Output Products dialog box opens. Click OK.
3. In the Sources window, select the top-level subsystem source, and select
Create HDL Wrapper to create an example top-level HDL file (FIGURE 25).
4. Click OK when the Create HDL Wrapper dialog box opens.
Step 5: Assign Signals to Debug
Figure 25: Create HDL Wrapper
Figure 31: Create HDL Wrapper
14 VIVADO TUTORIAL
Step 5: Assign Signals to Debug
Now assign the signals to debug in the hardware.
Step 7: Implement Design and Generate Bitstream
1. In Flow Navigator, click Generate Bitstream to implement the design and
generate a BIT file.
Note: If the system requests to re-synthesize the design before implementing,
click No. The previous step of saving the constraints caused the flow to mark
synthesis out-of-date. Ordinarily, you might want to re-synthesize the design
if you manually changed the constraints, but for this tutorial, it is safe to
ignore this condition (FIGURE 26).
Figure 26: Generate Bitstream
You might see a dialog box stating no implementation results are available.
2. Click Yes.
Figure 27: No Implementation Results Available Dialog Box
VIVADO TUTORIAL 15
3. After the design implementation, click Open Implemented Design, (FIGURE
28).
Figure 28: Bitstream Generation Completed
4. You might get a warning that the implementation is out of date. Click Yes.
Figure 29: Implementation Is Out-of-Date Dialog Box
16 VIVADO TUTORIAL
Step 8: Export Hardware to SDK
In this step, you export the hardware description to SDK. You use this in Part 2.
The IP integrator block diagram, and the Implemented design, must be open to Conclusion
export the design to SDK.
Export to SDK
IMPORTANT: For the Digilent driver to install, you must power on and connect the
board
to the
host PC before
launching
1. In
the Flow
Navigator,
click Open
BlockSDK.
to invoke the IP integrator design (FIGURE 47).
Conclusion
Export to SDK
Conclusion
SDKNavigator, click Open Block to invoke the IP integrator
1.Export
In theto
Flow
design
(FIGURE 30).
1. In the Flow Navigator, click Open Block to invoke the IP integrator design (FIGURE 47).
Export to SDK
1. In the Flow Navigator, click Open Block to invoke the IP integrator design (FIGURE 47).
Figure 47: IP Integrator: Open Block Design
Now you are ready to export your design to SDK.
2. From the main Vivado File menu,
Export Open
Hardware
for SDK (FIGURE 48).
Figure select
47: IP Integrator:
Block Design
Figure 30: IP Integrator - Open Block Design
Figure 47: IP Integrator: Open Block Design
Now you
ready
to export
your design
SDK. to SDK.
Now
youare
are
ready
to export
yourtodesign
2. From
the main
Vivado
File menu,
Hardware for SDK (FIGURE 48).
Now you
are ready
to export
your select
designExport
to SDK.
2. 2.From
the main Vivado File menu, select Export Hardware for SDK (FIGURE
From the main Vivado File menu, select Export Hardware for SDK (FIGURE 48).
31).
Figure 48: Export Hardware for SDK
Figure 48: Export Hardware for SDK
The Export Hardware for SDK dialog
box
opens.
Figure 48:
Export
Hardware for SDK
Figure 31: Export Hardware for SDK
The Export Hardware for SDK dialog box opens.
If you want
to go on to Lab 2 then ensure that Export Hardware, Include Bitstream, and
The
Export
Hardware
forLab
SDK
box
opens.
If
you
want
to Hardware
go on(F
to
2 dialog
then
ensure
that box
Export
Hardware,
Include
Bitstream,
and option
The
for
SDK
dialog
ensure
Export
Launch SDK Export
are
checked
IGURE
49).
Otherwise,
youopens,
can leave
the that
Launch
SDK
Launch
SDK
are
checked
(F
IGURE
49).
Otherwise,
you
can
leave
the
Launch
SDK
option
If you want toInclude
go on to Bitstream,
Lab 2 then ensure
Export Hardware,
Bitstream,
and 32).
Hardware,
andthat
Launch
SDK areInclude
checked
(FIGURE
unchecked.
unchecked.
Launch SDK are checked (FIGURE 49). Otherwise, you can leave the Launch SDK option
unchecked.
Figure 49: Export Hardware for SDK
Figure 49: Export Hardware for SDK
Conclusion
Conclusion
Figure
forSDK
SDK
Figure49:
32:Export
Export Hardware
Hardware for
VIVADO TUTORIAL 17
In this lab you have:
In this lab you have:
Conclusion
Embedded Processor Hardware Design
Embedded Processor Hardware Design
2013.2) June 19, 2013
In this labUG940
you (vhave:
UG940
(v 2013.2) June 19, 2013
www.xilinx.com
www.xilinx.com
34
34
Chapter 3
Part 2: Build Zynq-7000 Processor Software
In this portion of the tutorial you will build an embedded software project that
prints “Hello World” to the serial port.
Lab 2: Using SDK and the Vivado IDE
Logic
Analyzer
Step 1: Start
SDK and
Create a Software Application
1. If you are doing this lab as a continuation of Part 1 then SDK should have
launched
in a separate window (if you checked the Launch SDK option while
Introduction
exporting hardware). You can also start SDK from the Windows Start menu
You can run this lab after Lab 1. Make sure that you followed all the steps in Lab 1 before
by proceeding.
clicking on Start > All Programs > Xilinx Design Tools > Vivado 2013.2
> SDK > Xilinx SDK 2013.2. When starting SDK in this manner you need to
ensure that you in the correct workspace.
Step 1: Start SDK and Create a Software Application
If youdo
arethat
doing by
this clicking
lab as a continuation
1 then SDK
should have launched
in a
2. You1. can
on Fileof>LabSwitch
Workspace
> Other
in SDK. In
separate window (if you checked the Launch SDK option while exporting hardware). You can
the Workspace
Launcher
dialog
box
in
the
Workspace
field,
point
to
the
also start SDK from the Windows Start menu by clicking on Start > All Programs > Xilinx
SDK_Export
folder
where
had
exported
your hardware from lab 1.
Design Tools
> Vivado
2013.2you
> SDK
> Xilinx
SDK 2013.2.
Usually,
this
is
located
at
When starting SDK in this manner you need to ensure that you in the correct workspace.
..\project_name\project_name.sdk\SDK\SDK_Export.
2. You can do that by clicking on File > Switch Workspace > Other in SDK. In the Workspace
Now
Launcher dialog box in the Workspace field, point to the SDK_Export folder where you had
exported your hardware from lab 1. Usually, this is located at
you
can create a hello world application.
..\project_name\project_name.sdk\SDK\SDK_Export.
Now you can create a peripheral test application.
3. Select File > New > Application Project (FIGURE 33).
3. Select File > New > Application Project (FIGURE 50).
Figure 33: File->New->Application Project
Figure 50: File >New > Application Project
New Project dialog box opens
Embedded Processor Hardware Design
UG940 (v 2013.2) June 19, 2013
18 VIVADO TUTORIAL
www.xilinx.com
36
4. In the Project Name field, type Zync_Design, and click Next (FIGURE 34).
Figure 34: SDK Application Project
VIVADO TUTORIAL 19
Step 1: Start SDK and Create a Software Application
5. From
Available
Templates,
select Peripheral
Test World
(FIGURE (FIGURE
52) and click
5.the
From
the Available
Templates,
select Hello
34)Finish.
and click
Finish.
Figure
52: SDK New Project Template
Figure 35: SDK New Project Template
When
the program
finish compiling,
see the
following
When the
program
finishes compiling,
you seeyou
the will
following
(FIGURE
53). (FIGURE 36).
Figure 36: SDK Message
Figure 53: SDK Message
20 VIVADO TUTORIAL
Embedded Processor Hardware Design
UG940 (v 2013.2) June 19, 2013
www.xilinx.com
38
Step 2: Run the Software Application
Now, you must run the hello world application on the ZedBoard. To do so, you need
to configure the JTAG port. Make sure that your hardware is powered on and a
Digilent Cable is connected to the host PC. Also, ensure that you have a USB cable
connected to the UART port of the ZedBoard.
1. Click Xilinx Tools and select Configure JTAG Settings (FIGURE 37).
Figure 37: Configure JTAG Settings
2. In the Configure JTAG Settings dialog box, select the Type as Auto Detect,
and click OK (FIGURE 38).
Figure 38: Configure JTAG Settings
VIVADO TUTORIAL 21
3. Next, download the bitstream into the FPGA by selecting Xilinx Tools >
Program FPGA (FIGURE 39).
Figure 39: Program FPGA
This opens the Program FPGA dialog box.
4. Ensure that the path to the bitstream that you created in Step 7 of Lab 1 is
correct and then click Program.
Note: The DONE LED on the board turns blue if the programming is
successful.
5. Select and right-click the Zynq_Design application.
6. Select Debug As and Debug Configurations (FIGURE 40).
22 VIVADO TUTORIAL
Figure 40: Launch on Hardware
7. In the Debug Configurations dialog box, right-click Xilinx C/C++ Application
(GDB) and select New.
VIVADO TUTORIAL 23
Figure 41: Debug Configuration Dialog Box
8. In the Debug Configurations dialog box, click Debug.
Figure 42: Run Debug Configurations
9. The Confirm Perspective Switch dialog box opens. Click Yes.
Figure 43: Confirm Perspective Switch Dialog Box
24 VIVADO TUTORIAL
10. Set the terminal by selecting the Terminal 1 tab and clicking the Settings
button (FIGURE 44).
Figure 44: Settings Button
11. Use the following settings for the ZedBoard (FIGURE 45). Click OK.
The Port should be the
port for the Cypress
USB-to-Serial.
Figure 45: Terminal Settings
12. Verify the Terminal connection by checking the status at the top of the tab
(FIGURE 46).
Figure 46: Terminal Connection Verification
VIVADO TUTORIAL 25
13. In the Debug tab, expand the tree, and select the processor core on which the
program is to be run (FIGURE 47).
Figure 47: Processor Core to Debug
14. If it is not already open, select ../src/helloworld.c, line 41, and double
click that line to open the source file.
Add a Breakpoint
You add a breakpoint on line 43.
1. Select Navigate > Go To Line (FIGURE 48).
Figure 48: Go to Line
26 VIVADO TUTORIAL
2. In the Go To Line dialog box, type 43.
3. Double click on the left pane of line 43, which adds a breakpoint on that line
of source code (Figure 49).
Figure 49: Add a Breakpoint
Step 3: Executing the Software
This step will take you through executing the code up to and past the break point.
1. Click the Resume button or press F8
2. Click the Step Over button or press F6
3. You should see “Hello World” in the terminal if everything worked correctly
(FIGURE 50).
Figure 50: Terminal Output
VIVADO TUTORIAL 27