Integrated Tool Suite for
Post Synthesis FPGA Power
Consumption Analysis
Matthew French, Li Wang
University of Southern California, Information Sciences Institute
Tyler Anderson, Michael Wirthlin
Brigham Young University
French 207
Slide 1
MAPLD 2005
Power Tools: Goals
• Push power analysis, visualization, and
optimization to front of the tools chain:
– Analyze power consumption at logic simulation
with two levels of accuracy
• Pre-place-and-route, using heuristic
estimates based on fanout
• Back-annotated with precise post-placeand-route RC data
– Visualize by providing intuitive views to help
the designer rapidly find and correct inefficient
circuits, operating modes, data patterns, etc.
– Optimize systems by automatically identifying
problem paths and suggesting improvements
FPGA Tool Flow
• Benefits
–
–
–
–
Closer to logical level and design entry
Power profiling during functional simulation
Early estimation before place and route
Automatic specific resource utilization power
details
– Facilitates high level design alternative
exploration
French 207
Slide 2
Proposed
Power Tool
Entry Point
Current
Power Tool
Entry Point
MAPLD 2005
Tool Backbone: JHDL & EDIF Parser
• Leverage JHDL simulation Environment with EDIF Parser circuit manipulation
• JHDL
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–
–
–
Java-based structural design tool for FPGAs
Circuits described by creating Java Classes
Design libraries provided for several FPGA families
http://www.jhdl.org
• JHDL design aides
– Logic simulator & waveform viewer
– Circuit schematic & hierarchy browser
– Module Generators
• Circuit designer does not need to know Java!
• EDIF Parser
–
–
–
–
–
–
Supports multiple EDIF files
Virtex2 libraries and memory initialization
Support for “black boxes”
No JHDL wrapper required
http://splish.ee.byu.edu/reliability/edif/
Verified: Synplicity, Synplcity Pro, Coregen,
System Generator, Chipscope
French 207
Slide 3
3rd Party
Tools
JHDL Environment
JHDL
Data
Structure
EDIF
Netlist
EDIF
Parser
EDIF Parser
EDIF
Data
Structure
Manipulation
Tools
MAPLD 2005
Power Visualization Tool
•
Two views:
–
–
•
Integrated “cross-probing” with
existing JHDL tools
–
–
–
•
•
•
Instantaneous vs. cumulative power
consumption over time
Sorted tree view of “worst offenders”
Unified Environment
Allows Experimentation
Smart Re-use of CPU Memory
Help rapidly identify inefficient
circuits and operating modes
Per-cell / per-bit granularity
Simulation trigger on power
specification
Cross Probing
French 207
Slide 4
MAPLD 2005
Post Synthesis Level Power
Modeling
• Power Modeling
– Quiescent power based on total circuit size
– Dynamic Power
Power   (%toggle)( FreqClock )(CapComponent  CapWire)
• Toggle Rates (Data Dependant)
• Components Used
• Routing Interconnect
– Actual quiescent and dynamic power not known
until circuit is placed and routed
• Leverage existing JHDL tool environment
Component
Cap
(pF)
Component
Cap
(pF)
FF
1.21
LUT
1.0
SRL
3.0
LD
1.0
INV
1.0
AND
1.0
RAM
1.0
MULT
17.2
DLL
40.0
IBUF
1.0
– Toggling rates derived from simulator
BUFG
6.0
BRAM
59.0
• Will lose glitching information
– Components known from EDIF or JHDL primitives Xpower Component Capacitance
• Component capacitance imported from
Interconnect
Cap (pF)
Xpower
– How to model routing interconnect?
Long Line
11.8
• Do not have exact routing information at
Hex Line
0.59
synthesis
Double Line
0.44
• Routing tools can pick different route each
iteration
Direct Connect
0.29
– Interconnect length and combinations vary
Xpower Interconnect Capacitance
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Slide 5
MAPLD 2005
Capacitance vs Fanout
• Fanout model
well correlated
• Secondary fit
line
corresponds
to Macros
• High variance
at low fanout
• Achieving
4.3% average
error, 16%
variance
• Explored
device
utilization
models as well
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Placement
Macros
Slide 6
MAPLD 2005
Resulting Power Tool Flow
.ncd
Map
Source
Code
VHDL
Verilog
JHDL
Synthesis
Xilinx Tool
Flow
Bitgen
.pwr
EDIF
Virtex II
Power
Model
EDIF
Parser
JHDL
French 207
.ncd
Place &
Route
Xpower
To
Target
Routed
Circuit
Model
Power Analysis &
Visualization
Slide 7
Power
Tools
MAPLD 2005
Power Optimization Approach
• Influence Xilinx Place&Route tools for power
efficiency
– Minimize clock/wire lengths of high power nets
• Use power analysis tools to identify hot-spots and
generate constraints
– Timing constraints on non-clock signals
– Location constraints on sink flip-flops of clock signals
• Timing Constraints
– Over-constrain timing for power
– Achieving up to 12% power reduction
Timing
Constraint
(ns)
Placement
Constraint
(X,Y)
• Location Constraints
– Pares clock tree
– Achieving up to 23% power reduction
– Several placement strategies
• Not violating original circuit
timing specifications
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Unconstrained
Slide 8
Constrained
MAPLD 2005
Conclusions
• Post-synthesis level power modeling is feasible
– Some accuracy trade-offs inevitable
– Quicker power results enable
• Capability to determine power specifications early in
the design flow
• Feedback on design-level circuit power ramifications
• Tighter feedback loop to designer for more design
iterations
• Optimization
– Preliminary results encouraging
– Tools do not alter original circuit functionality & use COTS
inputs
– Developing optimization algorithms & routines
• Tools are open source: http://rhino.east.isi.edu
• This research made possible by a grant from
the NASA Earth-Sun System Technology Office
French 207
Slide 9
MAPLD 2005