• Describe the various tools that encompass Xilinx
Embedded Development Kit (EDK)
• Rapidly architect an embedded system containing an
IBM PowerPC
 processor and Xilinx-supplied IP cores
• Create and Integrate your own custom peripheral
• Develop and debug software applications with the
Eclipse-based Software Development Kit (SDK)
Introduction 2

The course consists of the following modules:
• EDK Overview
• PowerPC Hardware Design
– Basic Hardware System
• Hardware Design Using EDK
– Adding IP to a Hardware Design
• Adding Your Own IP to the System
• Debugging with SDK
Introduction 3

OPB
Bus
PLB
Bus
PPC
PLB2OPB
PLB BRAM
Cntlr
PLB BRAM
Cntlr
PLB BRAM
PLB BRAM
UART
GPIO
MY IP
Timer
INTC
ICON
IBA
DIP SW
Push Buttons
LEDs
Introduction 4

VHDL or Verilog
C Code
Standard Embedded
SW Development Flow
Embedded
Development Kit
Standard FPGA
HW Development Flow
Code Entry and Compile the
?
Load Software
Into FLASH
Debugger
2
Board Support
Package
System Netlist
Data2MEM
3 Compiled BIT
Download Combined
Image to FPGA
HDL Entry
Instantiate the
‘System Netlist’ the FPGA
1 ?
Download Bitstream
Into FPGA
Chipscope
RTOS, Board Support Package
EDK Intro 5

EDK Tool Flow
MHS
Hardware
Platform Generation
EDK SW
Libraries
LibGen
.a
Embedded Software
Development
Application
Source
.c, .h, .s
Compiler (GCC)
.o
Linker (GCC)
IP Library or User Repository
Drivers,
MDD
MPD, PAO
PCore
HDL
PlatGen
System and
Wrapper VHD
ISE system.BMM
UCF system.BIT
NGC
NGDBuild
NGD
MAP
NCD, PCF
PAR
NCD
BitGen
ELF BitInit system_BD.BMM
download.CMD
download.BIT
iMPACT
CompEDKLib
IP Models
CompXLib
ISE Models
SimGen
Behavioral
VHD Model
SimGen
Structural
VHD Model
SimGen
Testbench
Stimulus
Timing
VHD Model
Simulation
Simulation
Generator
EDK Intro 6

EDK Intro 7

Hardware
Flow
Software
Flow data2MEM download.bit
GPIO
MicroBlaze
™/
PPC
Arbiter
UART
EDK Intro 8

– Input files → system_bd.bmm
, system.bit
, executable.elf
– Output file → download.bit
– This invokes the BitInit tool, which initializes the instruction memory of the processor
– The instruction memory may be initialized with a bootloop, bootloader, or an actual application
– Now the hardware and the software flows come together. This stage also calls the hardware and software flow tools if required
EDK Intro 9

– Input file → download.bit
– This downloads the download.bit
file onto the target board using the Xilinx iMPACT tool in batch mode
– XPS uses the etc/download.cmd
file for downloading the bitstream
• The download.cmd file contains information such as the type of cable is used and the position of the FPGA in a
JTAG chain
EDK Intro 10

– MDD = Microprocessor Driver Description
– MHS = Microprocessor Hardware Specification
– MPD = Microprocessor Peripheral Description
– MSS = Microprocessor Software Specification
– PAO = Peripheral Analyze Order
– BBD = Black Box Definition
– BMM = Block RAM Memory Map
EDK Intro 11

– LibGen = Library Generator. Uses MSS file, copies device drivers source files and generates software libraries for the defined system
– PlatGen = Platform Generator. Uses the MHS and
MPD files to create an implementation netlist of a bus-based sub-system
– SimGen = Simulation Generator. Uses MHS file to configure and generate a simulation netlist pointing to various simulation model types, such as SWIFT, BFM, netlist, RTL, etc.
EDK Intro 12

Microprocessor Peripheral Definition file provides default parameter settings in XPS
## MPD file created automatically for design OPB_SEMAPHORE
BEGIN opb_pwm, IPTYPE=PERIPHERAL
Parameters override generics in VHDL
## Parameter list for the generics entity OPB_PWM is generic (
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFA000";
PARAMETER C_OPB_AWIDTH = 32, DT = integer
PARAMETER C_OPB_DWIDTH = 32, DT = integer
C_MAX_RESOLUTION : integer range 4 to 32 := 16
PARAMETER C_HIGHADDR = 0xFFFF80FF, DT = std_logic_vector
PARAMETER C_NO_CHANNELS = 4, DT = integer
PARAMETER C_MAX_RESOLUTION = 16, DT = integer
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL
BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE

Microprocessor Peripheral Definition file provides default connections in XPS
## Port list for the signals
## Global signals
PORT OPB_Clk = "", DIR = in, SIGIS=CLK, BUS=SOPB
PORT OPB_Rst = OPB_Rst, DIR = in, BUS=SOPB
## OPB signals
PORT OPB_ABus = OPB_ABus, DIR = in, VEC = [0:31],
BUS=SOPB
PORT OPB_BE = OPB_BE, DIR = in, VEC = [0:3],
BUS=SOPB
PORT OPB_RNW = OPB_RNW, DIR = in, BUS=SOPB
PORT OPB_select = OPB_select, DIR = in, BUS=SOPB
PORT OPB_seqAddr = OPB_seqAddr, DIR = in, BUS=SOPB
PORT OPB_DBus = OPB_DBus, DIR = in, VEC = [0:31],
BUS=SOPB
PORT PWM_DBus = Sl_DBus, DIR = out, VEC = [0:31],
BUS=SOPB
PORT PWM_errAck = Sl_errAck, DIR = out, BUS=SOPB
PORT PWM_retry = Sl_retry, DIR = out, BUS=SOPB
PORT PWM_toutSup = Sl_toutSup, DIR = out, BUS=SOPB
PORT PWM_xferAck = Sl_xferAck, DIR = out, BUS=SOPB
OPB Bus Signals port (
-- Global signals
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
-- OPB signals
OPB_ABus : in std_logic_vector(0 to 31);
OPB_BE : in std_logic_vector(0 to 3);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_seqAddr : in std_logic;
OPB_DBus : in std_logic_vector(0 to 31);
Slave Signals
PWM_DBus : out std_logic_vector(0 to 31);
PWM_errAck : out std_logic;
PWM_retry : out std_logic;
PWM_toutSup : out std_logic;
PWM_xferAck : out std_logic;
PWM : out std_logic_vector(0 to C_NO_CHANNELS-1)
);
PORT PWM = "", DIR = out, VEC = [0:C_NO_CHANNELS-1]
END

– The MHS file is the Microprocessor Hardware Specification; it specifies processors, hardware peripherals, bus connections, and address spaces for the hardware
– PlatGen takes the MHS file and creates the system and peripheral netlists, HDL wrapper files, BMM file, etc.
– The Data2Mem tool will take the BMM file and create the proper initialization for the block RAM that is assigned to the executable memory space
EDK Intro 15

• What does the LibGen tool do?
– Read MSS file and generate libraries
• What is the difference between system.bit and download.bit files?
– The system.bit file contains only hardware description whereas download.bit file contains both hardware description as well as executable software
EDK Intro 16

– Getting Started with the Embedded Development Kit
– Processor IP Reference Guide
– Embedded Systems Tools Guide
– Xilinx Drivers
• Processor documentation
– PowerPC Processor Reference Guide
– PowerPC 405 Processor Block Reference Guide
– MicroBlaze Processor Reference Guide
• Support Website
– Tech Tips: www.xilinx.com/xlnx/xil_tt_home.jsp
– EDK Website: www.xilinx.com/edk

1. Peripherals are connected to the microprocessor by using the data and address buses
2. Xilinx has implemented IBM's CoreConnect
 bus architecture
3. On-chip Peripheral Bus (OPB) version 2.1 of the
CoreConnect architecture is designed for easy connection of on-chip peripheral devices
4. Any custom peripheral that connects to the OPB bus must meet the principles of the OPB protocol and the requirements of the Platform Generator

The Black Box Definition (BBD) file identifies netlist files used for a user peripheral
• The netlists are copied into the project/implementation directory
• Example of a single file without options
– FILES
– Blackbox.ngc
• Example of multiple file selections without options
– FILES
– blackbox1.ngc, blackbox2.ngc, blackbox3.edn

• There are two ways to integrate your own IP into XPS
– As a blackbox
• Synthesized with XST or a third-party synthesis tool
• Requires MPD and BBD
– As HDL
• Synthesized with the rest of the processor system
• Uses XST
• Requires MPD and PAO

C_FAMILY FILES virtex2
C_RPM C_FPU_TYP
E true full opb_fpu_full.edf virtex2 virtex2p virtex2p virtex virtex true lite true full true lite false full false lite opb_fpu_lite.edf opb_fpu_full.edf opb_fpu_lite.edf opb_fpu_full_noram32x1d.edf, ram32x1ds.edf opb_fpu_lite_noram32x1d.edf, ram32x1ds.edf

Timer
Utility
Bus
Bus Bridge
Communication
Debug
GPIO
Interrupt Controller
Memory Controller fsl, lmb opb opb2opb, opb2dcr, opb2plb opb_spi icon, iba, ila, vio, mdm opb_gpio opb_intc mch_opb_ddr, mch_opb_sdram, opb_bram, opb_ddr, opb_emc, opb_sdram, opb_sysace fit_timer, opb_timer, opb_timebase_wdt bus_split, flipflop, reduced_logic, vector_logic dcr, ocm, plb, fcb fcb2fsl, plb2opb hard_temac, plb_temac
Iba, jtagppc_cntlr plb_gpio dcr_intc dsbram, isbram, pb_ddr, plb_emc, plb_sdram

• The Processor IP
Calculator is an online tool that helps you easily estimate the processor IP core size usage
• www.support.xilinx.com/ ipcenter/processor_cent ral/ppcip/calc.htm
• Try it out!!

• IBM PowerPC  embedded system

• Platform Generator supports the following features for OPB peripherals, and it is a subset of the OPB v2.1 features
– Fully synchronous single-clock edge
– 32-bit address bus, 32-bit data bus
– Single-cycle transfer of data between the OPB master and the OPB slave
– Supports master byte enables
– Supports slave timeout suppress, retry
– No three-state drivers required
• Note that the dynamic bus sizing feature is not supported in OPB v2.1

• The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals

• The OPB bus architecture (v2.1) allows for the addition of peripherals to the system, without changing the existing I/O on either the OPB arbiter or the other existing peripherals
No don’t cares

• Global OPB slave signals
– Slave signals
• <Sln>_xferAck
• <Sln>_errAck
• <Sln>_toutSup
• <Sln>_retry
• <Sln>_DBus
– OPB bus signals
• OPB_select
• OPB_RNW
• OPB_BE
• OPB_seqAddr
• OPB_Abus
• OPB_DBus
OPB
Slave
<Sln>_xferAck
<Sln>_errAck
<Sln>_toutSup
<Sln>_retry
<Sln>_DBus
OPB_select
OPB_RNW
OPB_BE
OPB_seqAddr
OPB_ABus
OPB_DBus
OPB
Bus
Logic

– Ensure that the peripheral complies with Xilinx implementation of the IBM CoreConnect

Bus
Standard
Adding IP 30

The Create and Import Peripheral Wizard can be started after creating a project and using
Hardware

Create or Import Peripheral … or opening an existing project or using Start

Programs

Xilinx Platform Studio 8.2i
Peripheral Wizard

Accessories

Create and Import
Adding IP 31

• Calls four different executables
– Preprocessor (cpp0)
– Language specific c-compiler
• cc1 C-programming language
• cc1plus C++ language
– Assembler
• mb-as (MicroBlaze  processor)
• powerpc-eabi-as (PowerPC  processor)
– Linker and loader
• mb-ld (MicroBlaze processor)
• powerpc-eabi-ld (PowerPC processor)
Software Design 33

Exception Code
Entry Point
Save State
Call Handler
HANDLER
Registered Handler
Restore State
Return to Program
Software Design 34

• Features:
– Time base
– Fixed Interval Timer (FIT)
– Programmable Interval Timer (PIT)
– Watchdog timer
– These timers share the same time-base clock frequency
• Uses:
– Time-of-day
– Data logging
– Peripherals requiring periodic service
– Recover from faulty hardware or firmware
Software Design 35

– A set of software modules combined into the
“libxil.a” library
– Allows you to use the low-level PowerPC  processor core functions
• Enable, disable, and flush caches
• Read/write time-base registers
– Allows you to use IP peripheral-device drivers
• GPIO, PCI controller, UART,…
– Offers glue functionality to link code against standard libraries: Time, sleep, Files, Memory
Software Design 36

• Files: boot.S, boot0.S, crt0.S, eabi.S
– Application entry point at label _boot in boot.S
– _boot is single jump instruction to _boot0
– _boot0 is a few instructions that do a jump to _start in crt0.S
– _start
• Clears .bss and .sbss sections
• Sets up stack on an eight byte alignment
• Initializes time-base registers to zero
• Optionally, enable FPU bit in MSR
• Calls main()
– Calls _eabi to set R13 and R2 registers to point to
.sdata and .sdata2 sections respectively
– Performs user tasks
Software Design 37

• Memory and peripherals
– PPC405 uses 32-bit addresses
0xFFFF_FFFC
• Special addresses
– Every PowerPC™ system should have the boot section starting at
0xFFFF_0000
0xFFFFFFFC
• Default linker options
– Program space occupies a contiguous address space from 0xFFFF0000 to
0xFFFFFFFF
– Stack size: 4 KB
– Heap size: 4 KB
0x0000_0000
Reset Address
PLB/OPB Memory
PLB/OPB Memory
Peripherals

.text
.rodata
.sdata2
.data
.sdata
.sbss
.bss
Address Management 39
Text section
Read-only data section
Small read-only data section (less than eight bytes)
Read-write data section
Small read-write data section
Small uninitialized data section
Uninitialized data section

int ram_data[10] = {0,1,2,3,4,5,6,7,8,9}; /* DATA */ const int rom_data[10] = {9,8,7,6,5,4,3,2,1}; /* RODATA */ int I; /* BSS */ main(){
...
I = I + 10; /* TEXT */
...
}
Address Management 40

foo1.o
.text1
.data1
.bss1
foo2.o
.text2
.data2
.bss2
Address Management 41
Link
Merged
Output
Sections
.text
.data
.bss
Locate
Executable
Image
0xFFFF
Code
0xF000
0xEFFF uninitialized data
0xEF00
0xEEFF
Unused
0x2000
0x1FFF
Initialized data
0x0000

• XPS contains a graphical Linker Script
Generator
• Table-based GUI allows you to define the memory space for any section
• Launch from Software
→ Generate Linker
Script , or from the
Applications Tab, rightclick on <project> →
Generate Linker
Script
Address Management 43

Platform Studio SDK Platform Studio
Generate Hardware
Platform
Generate Software
Platform
Create software
App Project
Add sources
+ Edit
Compile + Link Debug / Profile
Yes Import ELF file,
Download to board
Done?
Debugging 45

1 C/C++ project outline displays the elements of a project with file decorators
(icons) for easy identification
2 C/C++ editor for integrated software creation
3 Code outline displays elements of the software file under development with file decorators (icons) for easy identification
4
Problems, Console,
Properties view lists output information associated with the software development flow
Debugging 46
1
4
2
3

Eclipse CDT powerpc-eabi-gdb
(or) mb-gdb
XMD
Xilinx custom graphical debug interface, started off as a skin on
XMD
Debugging 47 auto-launched gdb remote protocol auto-launched
JTAG / XMD protocol

1
The stack frame for target threads that you are debugging. Each thread in your program is represented as a node in the tree
1
2
2 Variables, Breakpoints, and
Registers views allow for viewing and real-time interaction with the view contents for more powerful debugging potential
3 4
3
4
5
C/C++ editor highlights the location of the execution pointer, along with allowing the setting of breakpoints
5
Code outline and disassembly view provide compiler level insight into the running code
Console view lists output information
Debugging 48

Debugging in XPS
- Download bitstream from
XPS
- Launch XMD
- Provide Target Connection
Options
- Launch GDB (Insight GUI)
- Set GDB Server connection port in GDB
- Download program
- Begin Debugging
Debugging in SDK
- Download bitstream from
XPS
- Launch XMD
- Provide Target Connection
Options
- Launch GDB (Insight GUI)
- Set GDB Server connection port in GDB
- Download program
- Begin Debugging
Debugging 49