EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
1
DIGITAL CIRCUITS AND SYSTEMS
EX1C
1.1
Designing complex combinational circuits:
1-digit BCD adder & subtractor
Cooperative group
TEAM NUMBER: ___________
DUE DATE: ________________
1st review due date: ______________
Instructor general comments:
STATEMENT:
My signature below indicates that I have (1) made an equitable contribution to EX1C as a member of the group,
(2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and
(3) acknowledged by name anyone outside this group who assisted this learning team or any individual member
in the completion of this document.
Today’s date: __________________
Active members
(1) ________________________________________
(2) _________________________________________
(3) _________________________________________
Roles: (reporter, simulator, etc.)
_______________
_______________
_______________
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) _______________________
(2) _______________________
1.2
Abstract
Explain the most significant developments, results or conclusions about the exercise here. Use the remaining
space on this sheet (200 words maximum).
(This section is mandatory. You must complete it to get a mark.)
EETAC - Digital Circuits and Systems
2
CONTENT
EX1C
Designing complex combinational circuits: 1-digit BCD adder & subtractor .................... 1
1.1
Cooperative group ................................................................................................................................... 1
1.2
Abstract ................................................................................................................................................... 1
1.3
Description .............................................................................................................................................. 3
1.4
Topics ...................................................................................................................................................... 4
1.5
Characterisation of circuits using gate-level simulations ........................................................................ 5
1.5.1
Experiment #1: The same RTL architecture in different chips ........................................................ 5
1.5.2
Experiment #2: Different RTL architectures on the same chip ....................................................... 5
1.6
The 1-digit BCD adder-subtractor ........................................................................................................... 6
1.6.1
Understanding the problem ............................................................................................................. 6
1.6.2
Devising a plan ............................................................................................................................... 7
1.6.3
Implementing the plan ..................................................................................................................... 7
1.6.4
Synthesis and electrical characteristics .......................................................................................... 8
1.6.5
Documenting the study time: time invested in planning, developing and testing the project .......... 8
1.7
Problem solution ..................................................................................................................................... 9
1.7.1
Gate-level simulations and comparing synthesised (flat) circuits ................................................... 9
1.7.2
Design of the 1-digit BCD adder and subtractor ............................................................................ 9
1.7.3
Design of the 6-bit binary adder and subtractor ............................................................................. 9
1.7.4
Design of the 6-bit BCD to two’s complement converter ................................................................ 9
1.8
References ............................................................................................................................................. 10
1.9
Study plan to solve the exercise ............................................................................................................ 10
1.10
Topics and activities checklist ............................................................................................................... 11
1.11
Grading grid .......................................................................................................................................... 12
1.12
Questions in solving EX1C ................................................................................................................... 13
1.13
Improvements to the exercise based on the review and correction ....................................................... 14
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
1.3
3
Description
The first aim of this exercise is to perform gate-level simulations to compare the features of the synthesised
circuits produced by the EDA tools. Furthermore, we aim to complete all the design flow phases up to
downloading the configuration files in the target programmable logic devices.
Finally, a specific application of combinational circuits is designed and implemented in a complex
programmable logic device (CPLD) or a field programmable gate array (FPGA), in this case, the 1-digit BCD
adder & subtractor. Other similar complex circuits can be inspected examining previous CSD terms, for
instance: 11_12_Q2, the multiplexed display system for NESYS 2 board; 10_11_Q2, arithmetic and logic unit
(ALU) and binary multipliers.
At this point, you already have to know how to assemble small components into a large structure using VHDL.
This was the purpose of the Part C in EX1B, where for instance, a large binary comparator COMP4 was built
structuring four elemental COMP1 blocs and some extra logic. Therefore, one of the main characteristics of the
proposed design is to learn and reinforce the concepts on how to carefully plan a large design (structure)
consisting of many components. The top-down VHDL-only project, is devised, verified using functional and
gate-level simulations, and implemented into the CPLD on the training board. See the Fig. 1. Remember that all
the small components have to be tested independently (at least functionally), so that its use is reliable in a larger
circuit structure.
Fig. 1 EX1C Flowchart (Visio)to design a large combinational circuit.
The design flow for a complex circuit will be enhanced by using also a gate-level simulation of the final logic
structure synthesised by the EDA tool for the target programmable chip. See the Fig. 2.
EETAC - Digital Circuits and Systems
4
Specifications
VHDL source files
Functional simulation
Synthesis
Gate-level simulation
Constrains: pin assignment
Place & fitting
Chip programming and testing
Ok?
yes
No
End
Fig. 2 Design flow of a large circuit enhanced by gate-level simulations (Visio).
NOTE: Due to this problem-based approach, an open-ended design is presented with many possible valid solutions. Therefore, instructors
have not tried every circuit to be designed and keep in mind that possibly they cannot give you advice or answers to all your questions.
That’s why designing in this way is so interesting; a lot of discussion can be established, and many different circuits can all work correctly
accordingly to their initial specifications.
1.4
Topics
The following topics have been listed based on the specific and cross-curricular learning objectives of the course.
After studying Chapter 1 and successfully completing all the assignments in this task, you will be able to carry
out the following:
------------- Part 1: Gate level simulations and prototyping
1.
2.
3.
4.
5.
6.
Explain the basic architecture of a CPLD or an FPGA and write down their technology differences.
View the synthesised circuits in PLD or FPGA (technology view).
Perform a gate-level (timing) simulation of a logic circuit using a VHDL test bench.
Run a time analysis tool and measure worst case propagation delays.
Compare characteristics of different implementations of the same project.
Run the complete design flow of a project, from conception to the prototype board. CPLD/FPGA pin assignment using
Lattice, Altera or Xilinx demonstration boards.
------------- Part 2: A complex hierarchical design
7.
8.
9.
Two’s complement (2C) binary arithmetic
Conceive a 1-digit BCD adder-subtractor based on 2C binary arithmetic.
Design a VHDL project for the 1-digit BCD adder-subtractor based on elemental blocks as components in a top-down
hierarchical and structured architecture.
10. Assemble all the components together and verify (full design flow)
------------- Part 3: Study time accountability
11. Sum up your study time using a Google Drive spreadsheet which can be embedded as a graphic at your ePortfolio.
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
1.5
5
Characterisation of circuits using gate-level simulations
Unit 1.15 (A, B or C depending on the specific vendor EDA tool) contains a great deal of information on how to
perform gate-level simulations of the flat synthesised circuit. In this section let’s compare the propagation delays
and maximum speed of operation of different implementations of the same truth table.
1.5.1
Experiment #1: The same RTL architecture in different chips
Let’s focus again in the Design 2 of the Circuit_1, the minimised circuit obtained running “Minilog.exe” as
represented in Fig. 3 . The goal is to synthesise it in two different programmable chips, a CPLD and a FPGA,
and measure and compare their characteristics. You already have performed the basic design flow consisting of
the steps (1) to (4):
Basic design flow:
(1) Specify: Truth table and symbol
(2) Plan: The strategy to follow to infer the circuit, structural or behavioural approach
(3) Develop: Start and run a lattice ispLEVER, Altera Quartus II or a Xilinx ISE project. Select the target
programmable chip: sPLD1, CPLD or FPGA.
(4) Verify: Functional simulation using ActiveHDL Lattice Edition / ModelSim Altera Edition/ Xilinx ISE
ISIM. The VHDL description or the ideal circuit is simulated.
Thus now, enhance the design flow adding a gate-level simulation of the synthesised circuit:
Extended design flow:
(5) Verify: Gate-level or timed simulation using ActiveHDL Lattice Edition / ModelSim Altera Edition/
Xilinx ISE ISIM. The real synthesised circuit containing propagation delays is simulated.
(6) Prototype: Using a training board like the ones described in the electronic components section of
the web. Assign pins using the assignment editor spreadsheet. Download the configuration file for
the target chip Perform measurements using laboratory instrumentation (signal generator,
oscilloscope, logic analyser, etc.)
a) For both chips (check the course web for the chip details), perform a gate-level simulation to measure the
maximum frequency of operation. Obtain also data from the timing analyser tool available in the EDA tool.
L = f(S1, S0, A, B)
S(1..0)
A
B
Circuit_1
M = g(S1, S0, A, B)
Fig. 3 Entity to synthesise into a CPLD and a FPGA.
1.5.2
Experiment #2: Different RTL architectures on the same chip
Let’s focus again in the Design 2 and the Design 5 of the Circuit_1 of the previous EX1B. You already have
performed the basic design flow consisting of the steps (1) to (4). So, now, let’s finish the design flow
performing steps (5) and (6) for the same chip (see the web to know which one is the target chip).
1
Proteus-ISIS is also a valid simulation tool when targeting a sPLD like the GAL22V10 (Unit 1.6).
EETAC - Digital Circuits and Systems
6
b) Perform a gate-level simulation to measure the maximum frequency of operation. Obtain also data from the
timing analyser tool available in the EDA tool. Finish the extended design flow to download the
configuration file in the programmable device and carry out laboratory measurements on the training board.
1.6
The 1-digit BCD adder-subtractor
There are several circuits to be designed with different levels of complexity. Thus, start with the top and go into
every single component trying to design it using simpler blocks and elemental components from the library. Be
neat and organised. Firstly, in paper sheets draw a diagram or a logic schematic to represent the block being
designed for documentation and clarification purposes when discussing the architectures with your team mates.
The idea is very simple: Never write VHDL code without having first a graphical representation of the circuit to
be designed. Remember to name all the circuit or schematic signals and ports before attempting to code in
VHDL. Once you already have a circuit structure, start coding it from bottom to top implementing useful blocks
or components with the aim to be used later on in new and more complex designs. Indeed, every component has
to be a project in itself with a simulation and verification procedure included, before attempting to use it in larger
projects.
NOTE: The proposed architecture for the 1-digit BCD adder and subtractor is not the best possible, but
one feasible, organised only for teaching purposes. See the references [2] and [3] for better circuits.
NOTE: The assignment in 1.6 is only a sample of a simple combinational circuit. Your instructor may
replace it for another similar one. Your aim is to analyse the circuit proposed in class following the
indications on the course’s web page.
1.6.1
Understanding the problem
In Fig. 4 there is the schematic that we aim to design. The schematic below is adapted to the LC4128V board
that contains a Lattice CPLD, which has two common-cathode seven-segment displays wired to CPLD pins.
Other training boards have similar displays, switches and buttons.
Fig. 4 A schematic of the 1-digit BCD adder and subtractor.
c)
Study the training board assigned to you by the instructors. Analyse its datasheet and other relevant
materials, and draw a block diagram which includes the programmable chip, input switches and
pushbuttons, and output LED’s or 7-segment displays, to suit the application of the 1-digit BCD adder and
subtractor.
In Fig. 5, there is the proposed internal architecture based on the use of two’s complement (2C) binary
arithmetic.
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
7
d) Read the class notes available on the web and prepare your own examples on how the circuit processes
data. For example, solve all the input and output signals and vectors for:
(-3) + (-6)
(-6) – (-8)
Fig. 5 The proposed internal architecture.
e)
1.6.2
Can you find another type of architecture to solve the problem? For instance, using the nine’s complement
convention. Draw the circuit schematic and find commercial chips that may perform the task.
Devising a plan
The design strategy is going to be a top-down approach. Let’s arrange the internal architecture shown in Fig. 5
for the 1-digit BCD adder subtractor. The idea will be to design each individual component first as a project in
itself, including at least, the component’s functional simulation (so, completing the basic design flow from step
(1) to step (4)). Therefore, up to ten individual projects can be seen here, including the top entity.
f)
1.6.3
Plan the project names and folders. Organise the project within the cooperative group. Assign the project to
different team members and explain who is going to be in charge of each component to be designed.
Implementing the plan
To develop the plan, we are going to use a bottom-up approach; however, we can start capturing the top entity
structure because all the components to be included are already named.
Top entity: One_digit_BCD_Adder_Subtractor
g) Because in a structural design there is no need to have every component implemented, write the VHDL of
the top entity circuit in Fig. 4 and implement it to see that there are no errors in the structure. The internal
architecture of every component may be, for now, for example a set of buffers. Capture the picture of the
RTL view and compare it our Fig. 5. How many VHDL files are required to complete this hierarchical
architecture?
BCD_to_2C_6bit
h) Design the BCD_to_2C_6bit as an individual project which includes a functional simulation to validate it
(see Fig. 1). Use timing diagrams to show signal activity over time and verify truth tables. Thus, follow the
basic design flow:
(1) Specify: Truth table and symbol
(2) Plan: The strategy to follow to infer the circuit, structural or behavioural approach
(3) Develop: Start and run a lattice ispLEVER, Altera Quartus II or a Xilinx ISE project. Select
the target programmable chip: sPLD 2, CPLD or FPGA.
2
Proteus-ISIS is also a valid simulation tool when targeting a sPLD like the GAL22V10 (Unit 1.6).
EETAC - Digital Circuits and Systems
8
(4) Verify: Functional simulation using ActiveHDL Lattice Edition / ModelSim Altera Edition/
Xilinx ISE ISIM. The VHDL description or the ideal circuit is simulated.
Adder_sub_6bit
i)
Design the Adder_sub_6bit as an individual project which includes a functional simulation to validate it
(see EX1B).
Bin_2C_to_BCD_6bit
j)
Design the Bin_2C_to_BCD_6bit as an individual project which includes a functional simulation to
validate it (see Fig. 1). Use timing diagrams to show signal activity over time and verify truth tables.
Hex_7seg
k) Design the Hex_7seg as an individual project which includes a functional simulation to validate it (See the
units, because this circuit was used as a tutorial exercise) Use timing diagrams to show signal activity over
time and verify truth tables.
Tens_sign
l)
Design the Tens_sign as an individual project which includes a functional simulation to validate it. Use
timing diagrams to show signal activity over time and verify truth tables.
Top entity design: One_digit_BCD_Adder_Subtractor
m) Simulate functionally the One_digit_BCD_Adder_Subtractor top project using the test bench file written
from the initial timing diagram.
1.6.4
Synthesis and electrical characteristics
Let’s finish the enhanced design flow adding the step (5) on a gate-level simulation, and the step (6) on
prototyping and laboratory measurements. Synthesise the project for the target chip using the EDA tool from
Lattice, Altera or Xilinx. Examine the summary and be aware of the many chip resources used.
n) Run a gate-level simulation for the whole project One_digit_BCD_Adder_Subtractor using the same test
bench of the functional simulation. Use the RTL and the technology views from the synthesis tool to clarify
and document the design. Considering data and results from the gate-level simulation and the EDA tool
timing analyser, answer this question: Which is the maximum frequency of operation of the
One_digit_BCD_Adder_Subtractor?
o) Once the code has been verified using simulator tools, the design flow continues: (1) assign pins, (2)
synthesise again the logic circuit for the target chip, and (3) downloading the configuration file into the
chip located on the training board in order to check the prototype. Perform laboratory measurements and
verify that it works as expected.
1.6.5
Documenting the study time: time invested in planning, developing and testing the project
p) In case of you have not yet done it in EX1B, add a spreadsheet at your Google Docs and a graphic in your
ePortfolio to sum up systematically your course study time. Follow the tutorial.
Do not modify the text from page 3 to page 8
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
1.7
1.7.1
9
Problem solution
Gate-level simulations and comparing synthesised (flat) circuits
Experiment #1: The same RTL architecture in different chips
Project name and
folder
Projects under
development
./EX1C/Design_1/
Gate-level simulation and
circuit comparisons. The same
architecture in 2 different chips
(See the web for the
project’s name)
Sections
Execution
phase
(, , )
Student engineer
in charge
Execution
phase
(, , )
Student engineer
in charge
a), b)
Experiment #2: Different RTL architectures on the same chip
Project name and
folder
Projects under
development
./EX1C/Design_2/
Gate-level simulation and
circuit comparisons. Different
architectures in the same chip.
(See the web for the
project’s name)
1.7.2
Sections
a), b)
Design of the 1-digit BCD adder and subtractor
Project name and folder
Projects under
development
Sections
./EX1C/
One_digit_BCD_Adder_Subtractor/
Planning the 1-digit
BCD adder and
subtractor.
c), d),
e), f), g)
Execution
phase
(, , )
Student
engineer in
charge
(See the web for the project’s
name)
Here, you have to add headings, summary table and a solution for every component solved. For instance:
1.7.3
Design of the 6-bit binary adder and subtractor
Project name and folder
Projects under
development
Sections
./EX1C/ Adder_sub_6bit/
Design of a 6-bit
binary adder and
subtractor
i)
(See the web for the project’s
name)
1.7.4
Execution
phase
(, , )
Student
engineer in
charge
Execution
phase
Student
engineer in
Design of the 6-bit BCD to two’s complement converter
Project name and folder
Projects under
development
Sections
EETAC - Digital Circuits and Systems
10
(, , )
./EX1C/ BCD_to_2C_6bit /
(See the web for the project’s
name)
1.8
Design of the 6-bit
BCD to two’s
complement
converter
charge
h)
References
Modify or add new references to this section. Follow the same format.
[1]
http://digsys.upc.es. Course wed page where to find a lot of resources for the course. Specially materials
from previous editions.
[2]
Rashmi S. B, Praveen B, and Tilak B. G, “Design of Optimized Reversible BCD Adder/Subtractor”,
IACSIT International Journal of Engineering and Technology, Vol.3, No.3, June 2011
[3]
BCD adder and 9-complement chip datasheets of the old and obsolete MC14560 and MC14561 from
Motorola (Freescale Semiconductor).
[4]
Navabi, Z., "Digital Design and Implementation with Field Programmable Devices", Kluwer Academic
Publishers, 2005, e-book, UPC Library (page 39).
[5]
(Add your own references) (Remember that this is mandatory). There is no way to do this exercise without
studying technical documentation.
1.9
Study plan to solve the exercise
Check the documentation in our web [1] to look at ways to establish a study plan, a task distribution scheme and
other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept
maps, schematics, tables, pictures, etc.
(This section is mandatory. It must be filled to get a mark.)
Here you are a project checklist to help you to keep track on the projects:
EX1C Projects
Project
Gxx
Gate-level
simulation and
circuit comparisons
Project
Project
6-bit binary adder
6-bit binary adder
and subtractor
Circuit_1_minimised Adder_6bit
Onebit_adder
Circuit_Prog_gate
Adder_sub_6bit
Adder_6bit
Onebit_adder
Project
6-bit Two’s
Complement
converter
Two_Comp_6bit
Adder_6bit
Onebit_adder
Project:
6-bit binary to BCD
converter
Bin_BCD_6bit_DM74185
Number of VHDL
files
1
2
3
Test bench file
Circuit_1_tb
Adder_6bit_tb
Adder_sub_6bit_tb
Pere
Pere
Helena
Pere
v
v
v
v
v
v
v
v
v
x
Engineer in
charge
1. Specifications
2. Devise a plan
3. Develop a project
4. Test using a
v
v
v
3
1
Two_Comp_6bit_
Bin_BCD_6bit_DM74185_tb
tb
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
functional
simulation
v
6. Verify using a
gate-level
simulation
7. Pin assignment
and prototype
v
v
v
11
v
v
Marks
1.10 Topics and activities checklist
Topics
1.
Explain the basic architecture of a CPLD or an FPGA
and write down their technology differences.
2. View the synthesised circuits in PLD or FPGA
(technology view).
3. Perform a gate-level (timing) simulation of a logic
circuit using a VHDL test bench.
4. Run a time analysis tool and measure worst case
propagation delays.
5. Compare characteristics of different
implementations of the same project.
6. Run the complete design flow of a project, from
conception to the prototype board. CPLD/FPGA pin
assignment using Lattice, Altera or Xilinx
demonstration boards.
7. Two’s complement (2C) binary arithmetic
8. Conceive a 1-digit BCD adder-subtractor based on
2C binary arithmetic.
9. Design a VHDL project for the 1-digit BCD addersubtractor based on elemental blocks as
components in a top-down hierarchical and
structured architecture.
10. Full design flow of a complex circuit
11. Sum up your study time using a Google Drive
spreadsheet which can be viewed as a graphic at
your ePortfolio.
Activities
a), b)
a), b)
a), b)
b), b)
a), b)
a), b)
c), d), e),
f), g)
h), i), j),
k), l), m)
n), o)
p)
Group
member in
charge
1
2
3
Comments
EETAC - Digital Circuits and Systems
12
1.11 Grading grid
Here you are the way the exercise could be graded. Please, add your own grades at the self-assessment row,
taking into account the number of activities done and the quality of the work presented. Your instructor can
give you a similar grading list accordingly to the actual projects you are asked to develop. Follow the web
pages or your instructor indications.
Gate-level
simulation and
circuit
comparisons
Design_1 (OR)
Design_2
Scores
Self-assessment
Instructor’s
grades
Designing a
commercial
chip (The EX1B
project 4):
A triple 2channel
multiplexer,
type
74HCT4053
a), b)
3p
Designing a specific
component of a
large arithmetic
circuit:
Assembling all the
project
8-bit 2C Adder
/subtractor
i)
4p
3p
n), o)
Total
Here you could explain which projects or sections you have finished and which are not done, so that it becomes
easy to self-assess your work. Remember that the self-assessment is compulsory to get a mark for the exercise.
Fill in the individual assessment and group’s cross-assessment. Double click to open the Excel spreadsheet and
fill in the yellow cells, so that the mean values will be calculated automatically by the embedded formula. The
total individual study time has to be in agreement with the table below.
Student 1
Student 2
Student 3
#DIV/0!
#DIV/0!
#DIV/0!
Total individual study
time (in hours)
Student 1
Student 2
Student 3
Individual mean
grade
Group's mean
study time
#DIV/0!
Annotate the cooperative and individual study time carried out to complete this exercise.
Study time
(in hours)
Group work Classroom and
laboratory sessions
Individual
Out of class
sessions
Student 1
Student 2
Student 3
In this link, you can see an example on how to fill in the tables.
Do not forget to annotate this grading grid before uploading the exercise on your site.
EX1C: Designing complex combinational circuits: 1-digit BCD adder & subtractor
13
1.12 Questions in solving EX1C
Reflect on the development of the exercise and how your cooperative group is coping with the task. Write your
questions, comments, doubts, opinions, etc. here. Add more sheets if necessary to report on your progress or
comments during the exercise. Hand in the exercise before the due date by uploading this “docx” file to your ePortfolio Google site. You can also add here sample questions and answers from your participation in the
course’s blog.
(This section is mandatory. You must complete it to get a mark.)
If you really have solved some of these projects, then you must have many questions that may or may not have
been answered, but it is worth writing them down here as a reminder to answer them later on, or just for keeping
track of the many concepts you are learning. Did you come up with any new ideas for similar designs?
Remember that it is extremely difficult to solve these
exercises (and so pass the course) without asking
questions. We expect from you a positive attitude and
an active participation throughout the entire course.
14
EETAC - Digital Circuits and Systems
1.13 Improvements to the exercise based on the review and correction
This is an optional section in which you can add anything you like based on the corrections. This section must
also be discussed orally with instructors.