Accelerating Design Cycles
Using Quartus II
SignalTap II Embedded Logic Analyzer
Copyright © 2005 Altera Corporation
SignalTap II Agenda
 SignalTap II Overview & Features
 Using SignalTap II Interface
 Advanced Triggering
Copyright © 2005 Altera Corporation
2
SignalTap II ELA
 Captures the Logic State of FPGA Internal
Signals Using a Defined Clock Signal
 Gives Designers Ability to Monitor Buried Signals
 Connects to Quartus II through FPGA JTAG Pins
 Captures Real-Time Data
 Up to 200 Mhz
 Is Available for Free
 Installed with Full Subscription or Web Edition
 Installed with Stand-Alone Programmer
Copyright © 2005 Altera Corporation
3
SignalTap II Device Support
Stratix & Stratix II
Stratix GX
Cyclone & Cyclone II
Excalibur
Mercury
APEX II
APEX 20K/E/C
Copyright © 2005 Altera Corporation
4
How Does It Work?
1. Configure ELA
2. Download ELA into
FPGA along with
Design
3. ELA Samples Internal
Signals
4. Quartus II
Communicates with
ELA through JTAG
Copyright © 2005 Altera Corporation
5
ELA Resource Utilization
 ELA Uses Device Resources for Implementation
 ALMs/LEs for ELA Megafunction & Routing
 Memory for Sample Storage
 LE Count Is a Function of the Number of
Channels & Trigger Levels
 Memory Block Count Is a Function of Number of
Channels & Sample Depth
 Selectable Trade-off Between Depth & Number of
Channels
 128K Sample Depth with 1024 Channels Is Not
Practical – 32,768 M4K Blocks
Copyright © 2005 Altera Corporation
6
Stratix/Cyclone Sample Resource Usage
Number of
Channels
Logic Elements
Trigger Level 1
Trigger Level 2
Trigger Level 3
8
316
371
426
32
566
773
981
256
2900
4528
6156
Number of
Channels
M4Ks Based on Sample Depth
256
512
2K
8K
32K
8
<1
1
4
16
64
32
2
4
16
64
256
256
16
32
128
512
Copyright © 2005 Altera Corporation
7
Modes of Operation
Three Different Configurations
 Internal RAM ELA Configuration
 Debug Port ELA Configuration
 Hybrid Approach
Provides Flexibility Based on Available
Device Resources
 Memory Resources Are Limited
Use Debug Port Configuration
 Pin Resources Are Limited
Use Internal RAM Configuration
Copyright © 2005 Altera Corporation
8
Internal RAM Configuration

Acquired Data Saved in Device Internal RAM
 Streamed Off-device through JTAG Port
 LEs Required to Implement ELA Core Logic
Signals From
Internal Nodes
ELA
Core Logic
ELA
Memory
Copyright © 2005 Altera Corporation
9
JTAG Port
To JTAG
Connector
Debug Port Configuration
 Acquired Data Routed to Unused Device I/O Pins
 Captured by External Logic Analyzer or Oscilloscope
 LEs Required to Implement ELA Core Logic
 I/O Pins Required for External Analysis
Signals From
Internal Nodes
Copyright © 2005 Altera Corporation
10
ELA
Core Logic
Signals to
Debug Ports
To Unused
I/O Pins
Supported Download Cables
USB Blaster
 USB Port Cable
ByteBlaster™ II
 Parallel Port Cable
ByteBlasterMV™
 Parallel Port
MasterBlaster™
 USB / Serial Port Cable
Copyright © 2005 Altera Corporation
11
SignalTap II Key Features
Setup
Data Triggering
Data Capture
Data Analysis
Copyright © 2005 Altera Corporation
12
Setup Features
 Up to 1024 Data Channels
 Multiple Analyzers in One Device
 Supports Analysis of Multiple Clock
Domains
 Each Analyzer Can Run Simultaneously
Setup
Data Triggering
Data Capture
 Resource Usage Estimation
 Incrementally Routes New Signals
Copyright © 2005 Altera Corporation
13
Data Analysis
Data Triggering Features
 Up to 10 Trigger Levels Per Channel
Setup
 Allows Application of Simple (Basic) &
Complex (Advanced) Triggering Schemes
 Defines a Sequential Pattern of Logic Conditions
Data Triggering
 Each Trigger Level is Logically ANDED
 If (L1 & L2 ... & L10) == TRUE  Data Capture
Data Capture
Data Analysis
Copyright © 2005 Altera Corporation
14
Data Triggering Features (Cont.)
 Three Main Trigger Positions
Setup
trigger
Samples Captured
Samples Captured
Old Samples
New Samples
TIME
Data Triggering
 Trigger Input
 Setup External Trigger to Trigger the Analyzer
 Trigger Output
Data Capture
 Signifies Trigger Event Occurred with SignalTap II
 Use One ELA’s Trigger Output as Trigger
Input for Another
Copyright © 2005 Altera Corporation
15
Data Analysis
Data Capture Features
 Up to 128K Samples Per Channel
Setup
 Increases Chance of Catching Target
Event
 Two Methods of Data Acquisition
1. Circular
2. Segmented
Data Triggering
Data Capture
 Mnemonic Tables

Create User-Defined Labels for Bit Sequences
(Ex. State Machine)
Copyright © 2005 Altera Corporation
16
Data Analysis
Data Analysis Features
 Data Export
 Save Real Time Data & Apply Data
as Stimulus to Simulation
Setup
Data Triggering
Data Capture
 Data Log
 Keep a a Log of Captured Data
 Compare Old Data Vs. New Data
Copyright © 2005 Altera Corporation
17
Data Analysis
SignalTap II Agenda
 SignalTap II Overview & Features
 Using SignalTap II Interface
 Advanced Triggering
Copyright © 2005 Altera Corporation
18
SignalTap II Design Flow
1) Use SignalTap II File (.STP)
 Use Quartus II GUI
 STP Separate from Design Files
2) Use Quartus II MegaWizard
 Instantiate Directly into HDL
Copyright © 2005 Altera Corporation
19
Using STP File
1. Create .STP File
•
•
•
•
•
Assign Sample Clock
Specify Sample Depth
Assign Signals to STP File
Specify Triggering
Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
Copyright © 2005 Altera Corporation
20
1) Creating a New .STP File
 To Create a .STP File
 Method 1
 Select the
in Quartus II
 Method 2
 Select New (File Menu)
 Other Files
 SignalTap II File
 Default File Name Will Be STP1.stp
Copyright © 2005 Altera Corporation
21
Main .STP File Components
Instance Manager
.STP File
JTAG Chain
Configuration
Waveform Viewer
Signal Configuration
Copyright © 2005 Altera Corporation
22
Instance Manager
Instance Manager
 Selects Current ELA to Setup/View
 Displays the Current Status of each Instance
 Displays Size (Resource Usage) of ELA
Copyright © 2005 Altera Corporation
23
Signal Configuration
Manages Data Capture & Signal
Configuration
 Sample Clock
 Sample Depth
 Trigger Position
 Trigger-In & Trigger-Out
Copyright © 2005 Altera Corporation
24
Assign Sample Clock
 Use Global Clock for Best
Results
 Data Written to Memory on
Every Sample Clock Rising
Edge
 Clock Signal Cannot Be
Monitored as Data
 External Clock Pin Created
Automatically if Clock
Unassigned
 auto_stp_external_clock
 ELA Expects External Signal to
be Connected to Clock Pin
Copyright © 2005 Altera Corporation
25
Specify Sample Depth
 Sample Depth
 Set Number of Samples
Stored for each Data Signal
 0 to 128K Sample Depth
 0 Selected When External
Analyzer Is Used
 Select RAM Type for Stratix
& Stratix II Devices
 Useful when Preserving a
Specific Memory Type is
Necessary
Copyright © 2005 Altera Corporation
26
Data Capture
 Circular
 Specify Trigger Position
 Pre
 Center
 Post
 Continuous
 Segmented
 Specify Segment Depth
Copyright © 2005 Altera Corporation
27
Circular Buffer
1. Data is Circled through the Acquisition Buffer until the
Trigger Event Occurs
2. After the Trigger Event Occurs, Post-Trigger Data is
Collected until the Buffer Fills up
Copyright © 2005 Altera Corporation
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Example: Circular Buffer
Copyright © 2005 Altera Corporation
29
Segmented Buffer
Segment 1
Segment 2
Segment 3
Trigger Event
 Acquisition Buffer is Segmented into a Smaller, User
Defined Blocks
 Example: 4K is segmented into 4-1K segments
1. Data is Circled through the Acquisition Buffer until the
Trigger Event Occurs
2. When the Trigger Event Occurs, Post-Trigger Data is
Collected until the Segment Fills up
3. Process Repeats until all Segments are Filled
Copyright © 2005 Altera Corporation
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Example: Segmented Buffer
Copyright © 2005 Altera Corporation
31
Triggering
 Trigger Levels
 Indicate up to 10 Trigger Conditions
 Trigger-In
 Any I/O Pin Can Trigger the SignalTap
II Analyzer
 Generates auto_stp_trigger_in_n Pin
 Trigger-Out
 Indicates When a Trigger Pattern
Occurs
 Generates auto_stp_trigger_out_n Pin
 Delayed 4 Clock Cycles after Actual
Trigger Event
Copyright © 2005 Altera Corporation
32
Waveform Viewer
Setup Tab Describes the Signal Settings
 Data Signals vs. Trigger Signals
 Sets up Each Triggering Level (L1 – L10)
Data Tab Displays Captured Data
Copyright © 2005 Altera Corporation
33
STP File Waveform Viewer
Setup Tab
Data Tab
Copyright © 2005 Altera Corporation
34
Set up Waveform Viewer
 Add Signals to Viewer Window
 Use Node Finder
 Main Menu, Toolbar, or Right-Click Click
 Only Signals that Are Found Using the SignalTap II Filter in the Node
Finder Can Be Captured
 Important: Not All Signals Are Available
 Data Enable Column Check Box Controls Whether Signal
Is Captured As Data
 Ex. Removing Reduces Sample Memory Size
 Trigger Enable Column Check Box Controls Whether
Signal Is Disregarded as a Trigger Pattern
 Ex. Signal Used Only for Data Collection
Copyright © 2005 Altera Corporation
35
Basic Triggering
All Signals Must Be
True for Level to
Cause Data Capture
Right-Click
to Set Value
Copyright © 2005 Altera Corporation
36
Debug Port
 Routes Data Signals to Spare I/O Pins for
Capture by External Logic Analyzer
 Quartus II Automatically Generates
auto_stp_debug_out_m_n Pin
 m Represents the Instance Number of the Analyzer
 n Represents the Order the Debug Port Pin Occurs
in the Signal List
Copyright © 2005 Altera Corporation
37
Mnemonic Table
 Allows a Set of Bit Patterns
to Be Assigned UserDefined Names
 Right-Click in the Setup View
of an STP File & Select
Mnemonic Setup
 Select Add Table
 Select Add Entry
 Ex. State Machines or
Decoders/Encoders
Copyright © 2005 Altera Corporation
38
JTAG Chain Configuration
Select Programming Hardware
Scan Chan Button Automatically
Determines Devices Physically Connected
to the Chain
Detects Non-Altera Devices & Displays Them as
Unknown
Copyright © 2005 Altera Corporation
39
2) Save .STP File & Compile

SignalTap II Logic Analyzer Control in Compiler
Settings
 Assignments  Settings
 Specify the STP File to Compile with Project
Copyright © 2005 Altera Corporation
40
3) Program Device(s)
 Use Quartus II Programmer or STP File
 Program Button in the SignalTap II Interface Only
Configures the Selected Device in Chain
 Use Quartus II Programmer to Program Multiple
Devices
 Can Create a STP File for each Device in the JTAG Chain
Copyright © 2005 Altera Corporation
41
4) Acquire Data
SignalTap II Toolbar & STP File Controls
 Run
 Autorun
 Stop
 Read Data (Reads in Data from Last Analysis)
Copyright © 2005 Altera Corporation
42
Displaying Acquired Data
Format in Time or
Sample Number
 Display Signal as Bar or Line Chart
 Export to Other Tools for Viewing or Analysis (File
Menu)
 Creates .VWF, .TBL, .CSV, .VCD, .JPG or .BMP File
Copyright © 2005 Altera Corporation
43
Using STP File Review
1. Create .STP File
•
•
•
•
•
Assign Sample Clock
Specify Sample Depth
Assign Signals to STP File
Specify Triggering
Setup JTAG
2. Save .STP File & Compile with Design
3. Program Device
4. Acquire Data
Copyright © 2005 Altera Corporation
44
Using MegaWizard
1. Create Instantiation Using MegaWizard
•
•
•
•
2.
3.
4.
5.
Number of Data Channels
Sample Depth
Number of Triggers Inputs
Number of Trigger Levels (Advanced/Basic)
Instantiate into Design
Synthesize Design
Create STP File Based on Instances & Edit
Acquire Data
Copyright © 2005 Altera Corporation
45
1) Create Instantiation
Size SignalTap II Instance
Basic or Advanced
Triggering?
Copyright © 2005 Altera Corporation
46
2 & 3) Instantiate & Synthesize
Copyright © 2005 Altera Corporation
47
4) Create STP File (File Menu) & Edit
 Generates New STP
File Based on Number
Design Instances
Copyright © 2005 Altera Corporation
48
Recompilation
Recompilation Required
 Addition/Removal of Instance, Data or Trigger
 Modifying the Sample Clock or Buffer Depth
 Enabling/Modifying Trigger-In/Trigger-Out
 Enabling the Debug Port
Lock Mode Prevents Changes Requiring
Recompilation
Copyright © 2005 Altera Corporation
49
Incremental Routing
Switches between Nodes without Full
Recompilation
Maximizes Effectiveness
Copyright © 2005 Altera Corporation
50
SignalTap II Incremental Routing
 Switches between Nodes without Full Recompilation
1) Enable Smart Recompilation
2) Manually Set the Number of Allocated Nodes
 Nodes Acts as Place Holders for Real Signals that Can Be Added Later
 Auto Creates Enough Nodes for Current Number of Data/Triggers
Copyright © 2005 Altera Corporation
51
SignalTap II Incremental Routing
Step 3: Add Post-Fitting nodes to STP file
 SignalTap II: Post-Fitting Nodes Always Incrementally Routed
 SignalTap II: Pre-Synthesis Nodes Always Cause a Full
Recompilation if Added Later
 Benefit of Enabling Incremental Routing on Pre-Synthesis Nodes is
that They Can Be Removed & Replaced with Post-fitting Nodes
without a Total Recompilation
Pre-Synthesis
Nodes
Post-fitting
Nodes
Copyright © 2005 Altera Corporation
52
Quartus II Netlist Optimization
 New Synthesis Optimization Features Do Not
Work Well with SignalTap II
 SignalTap II Nodes may Disappear
 Register Re-timing & WYSIWYG Re-Synthesis Should
be Disabled if SignalTap II is Used
 Set the Netlist Optimizations Logic Option to
Never Allow on Entities Which Have SignalTap II
Nodes
Copyright © 2005 Altera Corporation
53
SignalTap II & LogicLock
SignalTap II can Potentially Effect the
Performance of a Design
 Routing and/or Placement Can Change
Possible Solution: LogicLock
 Use LogicLock to Place Design Blocks within
Specific Regions
 Place the SignalTap II Block in its Own
LogicLock Region
See Appendix for Example of Using LogicLock with SignalTap II
Copyright © 2005 Altera Corporation
54
Exercise
Copyright © 2005 Altera Corporation
55
SignalTap II Agenda
 SignalTap II Overview & Features
 Using SignalTap II Interface
 Advanced Triggering
Copyright © 2005 Altera Corporation
56
Advanced Triggering
 Create Advanced Boolean Functions
Using Pre-Synthesis Nodes
Boolean Function Composed of
Multiple Objects
SignalTap II
Nodes
Copyright © 2005 Altera Corporation
57
Trigger Result
Enabling Advanced Triggering
1. Change the Trigger Level Type from Basic
to Advanced Triggering
2. A New Advanced Trigger Tab & Window
Will Appear
Copyright © 2005 Altera Corporation
58
Advanced Trigger Window
Copyright © 2005 Altera Corporation
59
Advanced Trigger Window
Node List
 Lists Available Nodes for Advanced Triggering
Pre-Synthesis Nodes Only
Object Library
 Lists Functions Necessary to Build Equations
Advanced Trigger Condition Editor
 Graphic Tool to Build Equation
Copyright © 2005 Altera Corporation
60
Object Library
Object Type
Settings
Edge & Level Detector
Pos/Neg Edge, Levels
Input Objects
Bit & Bus Values
Comparison Operators
<, <=, =, !=, >, >=
Bitwise Operators
Bitwise AND, OR, XOR,
Complement
Logical Operators
Logical NOT, AND , OR, XOR
Reduction Operators
Reduction AND, OR, XOR
Shift Operators
Left/Right Shift
Copyright © 2005 Altera Corporation
61
Advance Trigger Condition Editor
1. Click & Drag from Node List/Object Library into
Editor
Copyright © 2005 Altera Corporation
62
Advance Trigger Condition Editor
2. Connect Nodes & Objects
 Use Automatic Connection by Positioning
 Click & Drag Output Ports to Draw Wires
Copyright © 2005 Altera Corporation
63
Advance Trigger Condition Editor
3. Connect to Result Block
Copyright © 2005 Altera Corporation
64
Object Properties
 General Tab
 Change the Object Type
 Add Your Own Object
Name
Double-Click on an Object
to Open Object Properties
 Parameter Tab
 Set Bus or Bit Value
 Switch Between
Operators of the Same
Object Type
 Insert Pipelining
Copyright © 2005 Altera Corporation
65
Post-Fitting Nodes
 Results of Basic Triggering Conditions Can Be
Used For Advanced Triggering
Copyright © 2005 Altera Corporation
66
Example (1)
 Trigger on the Following Condition
If (Control =1) OR (d = F0h) AND (result = 10Fh)
 Pre-synthesis Nodes:
 Control
 d[7:0]
 Post-synthesis Node:
 result[11:0]
Copyright © 2005 Altera Corporation
67
Example (2)
Edit Basic Trigger Conditions - result
Copyright © 2005 Altera Corporation
68
Example (3)
Change to Advance Trigger Condition
Copyright © 2005 Altera Corporation
69
Example (4)
Add Rest of Pre-Synthesis Nodes
Copyright © 2005 Altera Corporation
70
Example (5)
Copyright © 2005 Altera Corporation
71
Compiling with SignalTap II
 Any Object Parameter with a White Background
is Runtime Configurable
 Change Does Not Require a Full Compilation
 Any Other Changes Require a Full Compilation
The User Entered Bus
Value Constant is
Runtime Configurable
The Comparator Setting
is also Run Time
Configurable
Copyright © 2005 Altera Corporation
72
Data Delay
 Delays a SignalTap II
Node by a User
Specified Number of
Sampling Clock
Cycles
Copyright © 2005 Altera Corporation
73
Object Properties
Dialog Box
Data Delay Example
Trigger Condition 1
If (Opcode = 0x01) followed by
(Opcode = 0x02) followed by
(Opcode = 0x03)
Clock
Instruction Register
0x01
0x02
0x03
Trigger Out Latency: 6 Clock Cycles
Copyright © 2005 Altera Corporation
74
SignalTap II ELA Summary
 Allows User to Debug Logic Design Problems
during Circuit Operation at System Speed
 Provides Easy Setup & Visibility of Internal
Nodes without External Analyzer
Copyright © 2005 Altera Corporation
75
Accelerating Design Cycles
Using Quartus II
SignalProbe Incremental Routing
Copyright © 2005 Altera Corporation
SignalProbe Incremental Routing
 Fast Incremental Routing of Debugging Signals
(Test Points) to Spare/Reserved I/O Pins
 Uses Any Available Routing without Full Recompilation
Debugging Cell
Logic
Unused I/O
Used Routing
Available
Routing
JTAG
Copyright © 2005 Altera Corporation
77
SignalProbe Advantages
 Simple to Use
 Quartus II Handles Signal Routing
 User Only Specifies Source Node & Destination Pin
 Quartus II Reports Delay Times from Node to Pin
 User Can Test Output of Any Hard Node
 Placement of Compiled Design Remains
Unaffected
 fMAX of Signal Being Debugged Unchanged
 SignalProbe Uses Incremental Routing
 Compilation Time Typically <10% of Full Compilation
Time
Copyright © 2005 Altera Corporation
78
SignalProbe Supported Devices
Stratix II
Stratix
Stratix GX
Cyclone
MAX II
Excalibur
APEX II
APEX 20K/E/C
Copyright © 2005 Altera Corporation
79
Using SignalProbe
1. Enable Smart Compilation
 Assignments  Settings  Compiler Process
2. Reserve SignalProbe Output Pins
3. Compile Design (Optional)
4. Assign SignalProbe Source (Debugging
Nodes)
5. Add Pipeline Registers & Clock, if Needed
Copyright © 2005 Altera Corporation
80
Using SignalProbe (cont.)
6. Perform SignalProbe Compilation

Processing  Start  Start SignalProbe
Compilation
7. Program Device
8. Repeat Steps 4-7 to Change SignalProbe
Sources
Copyright © 2005 Altera Corporation
81
Assign SignalProbe Dialog Box
Copyright © 2005 Altera Corporation
82
Reserve SignalProbe Pins
Select Pin Number
Type Reserved
Pin Name
Click Add
Enable
SignalProbe
Assign I/O
Standard
Copyright © 2005 Altera Corporation
83
Assign SignalProbe Sources
Use SignalProbe
Filter in Node Finder
to Locate Sources
Assign Clock & Number
of Registers for Pipelining
Copyright © 2005 Altera Corporation
84
SignalProbe Sources
 All Sources Must Be Nodes that Exist after Fitting
 Use SignalProbe Filter in Node Finder
 Valid Examples
 LE Outputs
 Memory Block Outputs
 DSP Block Outputs
 Invalid Examples
 Groups or Busses
 Carry or Cascade Chains
Copyright © 2005 Altera Corporation
85
Editing SignalProbe Assignments
 Change Source of Pins
 Add/Delete Source of Pins
 Enable/Disable SignalProbe Pins
 All Require SignalProbe Compilation Only
 Do Not Need to Perform Full Compilation
Copyright © 2005 Altera Corporation
86
SignalProbe Options
Route SignalProbe Signals during Full
Compilation
 Warning : Test Nodes May Be Synthesized
Away
Allow Place & Route to Be Modified (If
Necessary)
Copyright © 2005 Altera Corporation
87
SignalProbe Summary
 Allows Internal Signals to Be Routed to Unused
I/O Quickly & Easily
 Ensures Design Placement & Routing Are
Unchanged When Adding Test Points
Copyright © 2005 Altera Corporation
88