Global Timing Constraints
Objectives
After completing this module you will be able to…
Apply global timing constraints to a simple synchronous
design
Use the Xilinx Constraints Editor to specify global timing
constraints
The Effects of Timing Constraints
 Without global timing constraints
 Logic tends to be grouped to
improve internal timing at the
expense of I/O timing
 With global timing constraints
 All timing paths are evaluated
 I/O paths are improved (CLBs
are place closer to I/O pins)
Timing Constraints Define Your Performance
Objectives
Timing constraints define your timing objectives
– Over-constraining gets you nothing, but costs extra PAR time
– Always use timing constraints, even when your timing objective is modest
Unrealistic timing constraints will cause the tools to stop
– Your synthesis tool’s timing report and the Post-Map Static Timing Report
contain performance estimates
– Both will tell you if your constraints are realistic
After implementing, review the Post-Place & Route Static Timing
Report to determine if your objectives were met
– If your constraints failed, use the Timing Report to determine the cause
Path Endpoints
Path Endpoints are…
– I/O pads
– Synchronous elements
• FFs, Latches, Rams, DSP slices, SRLs, etc.
Flip-Flops
Latches
RAMs
 Path Endpoints do NOT include…
– LUTs
– Nets, or any other asynchronous element
DSP48
Creating Timing Constraints
 Creating timing constraints is a two step process
Step 1:
Create groups of path endpoints
Step 2:
Specify a timing requirement between the groups
 Global timing constraints use a default grouping of path endpoints which
makes it easy to constrain your design
PERIOD Constraint
 The PERIOD constraint covers paths between synchronous elements on a
single clock domain
– In this example, there is one clock signal (CLK)
– There are five synchronous elements (all FFs) attach to the clock which means
there are five path endpoints, in this case
– There are three delay paths constrained between those five FFs
FLOP1
DQ
ADATA
FLOP2
DQ
FLOP3
DQ
OUT1
CLK
BUFG
BUS [7..0]
CDATA
FLOP4
DQ
FLOP5
DQ
OUT2
PERIOD Constraint
The PERIOD constraint
uses the most accurate
timing information, so it
considers…
Clock skew between the
source and destination
flip-flops
Synchronous elements
clocked on the negative
edge
Unequal clock duty cycles
Clock input jitter
The Implementation tools use this information to place and route your
design
Example of the PERIOD Constraint
Assume…
FF1
FF2
– 50-percent duty cycle on CLK
– PERIOD constraint of 10 ns
– Because FF2 will be clocked on the
BUFG
falling edge of CLK, the path between
the two flip-flops will be constrained
to 50 percent of 10 ns = 5 ns
CLK
INV
– The implementation tools will automatically take into account that you are
triggering one FF on the rising edge and another on the negative edge
Clock Input Jitter
 The Xilinx Constraints Editor allows you to enter the input clock jitter
 The Implementation tools will then use this information to manage the place
and route solution found so the distributed clocks jitter can be tolerated
OFFSET IN/OUT Constraints
OFFSET IN
OFFSET OUT
FLOP
D Q
ADATA
FLOP
DQ
FLOP
DQ
FLOP
DQ
FLOP
DQ
OUT1
CLK
BUFG
BUS [7..0]
CDATA
OUT2
= Combinatorial Logic
 The Offset In constraint covers paths from input pads to synchronous elements
 The Offset Out constraint covers paths from synchronous elements to output pads
OFFSET IN/OUT Constraints
The Offset In/Out constraints takes the clock delay into account
to report an effective input and output delay
OFFSET IN = T_data_In - T_clk_In
OFFSET OUT = T_data_Out + T_clk_Out
T_data_Out
T_data_In
In
Out
T_clk_In
Clk
OFFSET-IN
T_clk_Out
OFFSET-OUT
OFFSET Constraints Reporting
 Timing constraint reporting is handled by the Timing Analyzer
 The Offset In/Out constraints take into account the clock delay and jitter
Apply Your Knowledge
Which paths are constrained by a Period constraint on CLK1?
– 1 path is constrained, FF to Latch
Which paths are constrained by a Period constraint on CLK2?
– No paths are constrained, only 1 synchronous element
Launching the Constraints Editor
Expand User Constraints in the
Processes window
Double-click Create Timing
Constraints
Entering a PERIOD Constraint
PERIOD constraints can be
entered by clicking Clock Domains
Constraints can be deleted by
right-clicking the constraint
Right-click here and select Create
Constraint to make a PERIOD
constraint
Multiple UCF Files
Select which UCF to read
constraints from and store
constraints to
Many designers keep their
timing constraints in a separate
UCF file
– User Constraints File (user
editable in many text editors)
– Some designers like to keep their
pin assignments, area constraints,
and placement constraints in a
separate UCF
PERIOD Constraint Options
TIMESPEC name
Specific constraint value
– Active clock edge
– Duty cycle
Relative to other PERIOD
TIMESPEC
– Useful for designs with multiple
clock signals
– Can define both frequency and
phase relationships
Input jitter
Entering OFFSET Constraints
Global OFFSET IN
and OFFSET OUT
constraints can be
made from Inputs or
Outputs
Right-click here and
select Create
Constraint to make
an OFFSET
constraint
Apply Your Knowledge
Given the system diagram below, what values would you put in
the Constraints Editor so that the system will run at 100 MHz?
– Assume no clock skew between devices
Upstream Device
4 ns
Downstream Device
5 ns
Answer
Given the system diagram below, what values would you put in the
Constraints Editor so that the system will run at 100 MHz?
Upstream Device
4 ns
Downstream Device
6 ns
10 ns
5 ns
5 ns
Answer: PERIOD = 10 ns , OFFSET IN = 6 ns, and OFFSET OUT = 5 ns
Summary
Performance expectations are communicated with timing
constraints
The PERIOD constraint covers delay paths between synchronous
elements
The OFFSET IN constraint covers delay paths from input pins to
synchronous elements
The OFFSET OUT constraint covers delay paths from
synchronous elements to output pins
Use the Constraints Editor to create timing constraints
Where Can I Learn More?
Constraints Guide
– Help  Software Manuals
• Entry strategies (UCF syntax and HDL syntax)
• Advanced timing constraints
Timing Constraints User Guide
– Help  Software Manuals  Timing Constraints User Guide
• Timing constraints (Global and Path Specific)
• Placement and Area constraints
• UCF syntax
Xilinx Education Services courses
– www.xilinx.com/training
• Path Specific Constraints are included with the Designing for Performance
course
• Xilinx tools and architecture courses
• Basic FPGA architecture, Basic HDL Coding Techniques, and other topics
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