Global Timing
Constraints
FPGA Design Flow Workshop
© 2003 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
•
•
Apply global timing constraints to a simple synchronous design
Specify global timing constraints with the Constraints Editor
Global Timing Constraints 7- 3
© 2003 Xilinx, Inc. All Rights Reserved
Outline
•
•
•
•
Global Timing Constraints 7- 4
Introduction
Global Constraints
The Constraints Editor
Summary
© 2003 Xilinx, Inc. All Rights Reserved
Timing Constraints
and Your Project
What effects do timing constraints have on your project?
•
The implementation tools do not attempt to find the place & route that will
obtain the best speed
–
•
Instead, the implementation tools try to meet your performance
expectations
Performance expectations are communicated with timing constraints
–
–
Timing constraints improve the design performance by placing logic closer
together so shorter routing resources can be used
Note that when we discuss using the Constraints Editor, we are referring to
the Xilinx Constraints Editor
Global Timing Constraints 7- 5
© 2003 Xilinx, Inc. All Rights Reserved
Without Timing Constraints
•
This design had no timing
constraints or pin assignments
–
–
Note the logical structure of the
placement and pins
This design has a maximum
system clock frequency of 50 MHz
Global Timing Constraints 7- 6
© 2003 Xilinx, Inc. All Rights Reserved
With Timing Constraints
•
•
•
This is the same design with three
global timing constraints entered
with the Constraints Editor
It has a maximum system clock
frequency of 60 MHz
Note that most of the logic is
placed closer to the edge of
the device, where the pins have
been placed
Global Timing Constraints 7- 7
© 2003 Xilinx, Inc. All Rights Reserved
More About Timing
Constraints
•
Timing constraints should be used to define your performance objectives
–
–
–
•
Tight timing constraints will increase your compile time
Unrealistic constraints will cause the implementation tools to stop
Use the synthesis report or the Post-Map Static Timing Report to determine
whether your constraints are realistic
After implementing, review the Post-Place & Route Static Timing Report
to determine whether your performance objectives were met
–
If constraints were not met, use the Timing Report to determine the cause
Global Timing Constraints 7- 8
© 2003 Xilinx, Inc. All Rights Reserved
Path End Points
•
Two types of path end points:
–
–
•
Creating a timing constraint is a two-step process:
–
–
•
I/O pads
Synchronous elements (flip-flops, latches, and RAMs)
Step 1: Create groups of path end points
Step 2: Specify a timing requirement between the groups
Global constraints use default groups of path end points
–
All flip-flops, all I/O pads, etc.
Global Timing Constraints 7- 9
© 2003 Xilinx, Inc. All Rights Reserved
Review Questions
•
•
•
A single global constraint can cover multiple delay paths
If the arrows are constrained paths, what are the path end points in this
circuit?
Do all of the registers have anything in common?
ADATA
FLOP1
FLOP2
FLOP3
D
D
D
Q
Q
Q
OUT1
CLK
BUFG
FLOP4
FLOP5
D
D
Q
Q
OUT2
BUS [7..0]
= Combinatorial Logic
CDATA
Global Timing Constraints 7- 11
© 2003 Xilinx, Inc. All Rights Reserved
Answers
•
What are the path end points in this circuit?
–
•
FLOP1, FLOP2, FLOP3, FLOP4, and FLOP5
Do all of the registers have anything in common?
–
They share a clock signal. A constraint that references this net could constrain
all delay paths between all of the registers in the design
ADATA
FLOP1
FLOP2
FLOP3
D
D
D
Q
Q
Q
OUT1
CLK
BUFG
FLOP4
FLOP5
D
D
Q
Q
BUS [7..0]
CDATA
Global Timing Constraints 7- 12
© 2003 Xilinx, Inc. All Rights Reserved
OUT2
Outline
•
•
•
•
Global Timing Constraints 7- 13
Introduction
Global Constraints
The Constraints Editor
Summary
© 2003 Xilinx, Inc. All Rights Reserved
The PERIOD Constraint
•
•
The PERIOD constraint covers paths between synchronous elements
clocked by the reference net
The PERIOD constraint does NOT cover paths from input pads to output
pads (purely combinatorial), from input pads to synchronous elements, or
from synchronous elements to output pads
ADATA
FLOP1
FLOP2
FLOP3
D
D
D
Q
Q
Q
OUT1
CLK
BUFG
FLOP4
FLOP5
D
D
Q
Q
BUS [7..0]
CDATA
Global Timing Constraints 7- 14
© 2003 Xilinx, Inc. All Rights Reserved
OUT2
Features of the PERIOD
Constraint
•
The PERIOD constraint uses the most accurate timing information so it
can automatically account for:
–
–
–
–
•
Clock skew between the source and destination flip-flops
Synchronous elements clocked on the negative edge
Unequal clock duty cycles
Clock input jitter
FF1
FF2
Assume:
–
–
–
CLK
50-percent duty signal on CLK
BUFG
INV
PERIOD constraint of 10 ns
Because FF2 will be clocked on the falling edge of CLK, the path between
the two flip-flops will actually be constrained to 50% of 10 ns = 5 ns
Global Timing Constraints 7- 15
© 2003 Xilinx, Inc. All Rights Reserved
Clock Input Jitter
•
•
Clock input jitter is one source of clock uncertainty
Clock uncertainty is subtracted from:
–
–
•
PERIOD constraint setup paths
OFFSET IN constraint setup paths
Clock uncertainty is added to:
–
–
–
PERIOD constraint hold paths
OFFSET IN constraint hold paths
OFFSET OUT constraint paths
Global Timing Constraints 7- 16
© 2003 Xilinx, Inc. All Rights Reserved
The Pad-to-Pad Constraint
•
•
Purely combinatorial delay paths do not contain any synchronous
elements
Purely combinatorial delay paths start and end at I/O pads and are often
left unconstrained
Global Timing Constraints 7- 17
© 2003 Xilinx, Inc. All Rights Reserved
Review Questions
•
Which paths are constrained by a PERIOD constraint on CLK1?
•
Which paths are constrained by a pad-to-pad constraint?
FLOP
PADA
D
Q
LATCH
D
Q
OUT1
G
CLK1
PADB
BUFG
RAM
D
CLK2
BUFG
PADC
Global Timing Constraints 7- 19
© 2003 Xilinx, Inc. All Rights Reserved
OUT2
Answers
•
Which paths are constrained by a PERIOD constraint on CLK1?
–
•
FLOP to LATCH
Which paths are constrained by a pad-to-pad constraint?
–
PADC to OUT2
FLOP
PADA
D
Q
LATCH
D
Q
OUT1
G
CLK1
PADB
BUFG
RAM
D
CLK2
PADC
Global Timing Constraints 7- 20
BUFG
© 2003 Xilinx, Inc. All Rights Reserved
OUT2
The OFFSET Constraint
•
The OFFSET constraints cover paths:
–
–
From input pads to synchronous elements (OFFSET IN)
From synchronous elements to output pads (OFFSET OUT)
OFFSET IN
ADATA
OFFSET OUT
FLOP
FLOP
FLOP
D
D
D
Q
Q
Q
OUT1
CLK
BUFG
FLOP
FLOP
D
D
Q
Q
OUT2
BUS [7..0]
= Combinatorial Logic
CDATA
Global Timing Constraints 7- 21
© 2003 Xilinx, Inc. All Rights Reserved
Features of the OFFSET
Constraint
•
The OFFSET constraint automatically accounts for the clock distribution
delay
–
–
–
•
Provides the most accurate timing information
Increases the amount of time for input signals to arrive at synchronous
elements (clock and datapaths are in parallel)
Reduces the amount of time for output signals to arrive at output pins (clock
and datapaths are in series)
The OFFSET constraint also accounts for clock input jitter
–
Uses the jitter defined on the associated PERIOD constraint
Global Timing Constraints 7- 22
© 2003 Xilinx, Inc. All Rights Reserved
Clock Delay
•
Both the datapath delay and the clock distribution delay are used to
calculate OFFSET constraints
–
–
OFFSET IN = T_data_In - T_clk_In
OFFSET OUT = T_data_Out + T_clk_Out
T_data_Out
T_data_In
In
Out
T_clk_In
T_clk_Out
Clk
OFFSET-IN
Global Timing Constraints 7- 23
OFFSET-OUT
© 2003 Xilinx, Inc. All Rights Reserved
Page 3
Review Question
•
Which paths are constrained by an OFFSET IN and an OFFSET OUT
constraint in this circuit?
PADA
FLOP
D
Q
LATCH
D
Q
G
CLK
BUFG
OUT1
RAM
PADB
OUT2
PADC
Global Timing Constraints 7- 25
© 2003 Xilinx, Inc. All Rights Reserved
Answer
•
Which paths are constrained by an OFFSET IN and an OFFSET OUT
constraint in this circuit?
–
–
OFFSET IN: PADA to FLOP and PADB to RAM
OFFSET OUT: LATCH to OUT1, LATCH to OUT2, and RAM to OUT1
PADA
FLOP
D
Q
LATCH
D
Q
G
CLK
BUFG
OUT1
RAM
PADB
OUT2
PADC
Global Timing Constraints 7- 26
© 2003 Xilinx, Inc. All Rights Reserved
Outline
•
•
•
•
Global Timing Constraints 7- 27
Introduction
Global Constraints
The Constraints Editor
Summary
© 2003 Xilinx, Inc. All Rights Reserved
Launching the Constraints
Editor
•
•
In the Processes for Source
window, expand User Constraints
Double-click Create Timing
Constraints
Global Timing Constraints 7- 28
© 2003 Xilinx, Inc. All Rights Reserved
Entering PERIOD and
Pad-To-Pad Constraints
•
•
•
•
The PERIOD and pad-topad constraints can be
made on the Global tab
Double-click here to make
a PERIOD constraint
Global pad-to-pad
constraint
Constraints can be deleted
by selecting the constraint
in the text window and
pressing <Delete>
Global Timing Constraints 7- 29
© 2003 Xilinx, Inc. All Rights Reserved
PERIOD Constraint Options
•
•
TIMESPEC name
Specific constraint value
–
–
•
Relative to another PERIOD constraint
–
–
•
Active clock edge
Duty-cycle
Useful for designs with multiple clock
signals
Can define both frequency and phase
relationships
Input jitter
Global Timing Constraints 7- 30
© 2003 Xilinx, Inc. All Rights Reserved
Entering OFFSET Constraints
•
Global OFFSET IN/OUT constraints can also be made on the Global tab
Pad to setup = OFFSET IN
Clock to pad =
OFFSET OUT
Global Timing Constraints 7- 31
© 2003 Xilinx, Inc. All Rights Reserved
Outline
•
•
•
•
Global Timing Constraints 7- 32
Introduction
Global Constraints
The Constraints Editor
Summary
© 2003 Xilinx, Inc. All Rights Reserved
Review Question
•
Given the system diagram below, what values would you put in the
Constraints Editor so that the system will run at 100 MHz?
–
Assume no clock skew between devices
Upstream Device
Downstream Device
2 ns
3 ns
Global Timing Constraints 7- 33
© 2003 Xilinx, Inc. All Rights Reserved
Answer
•
Given the system diagram below, what values would you put in the
Constraints Editor so that the system will run at 100 MHz?
Upstream Device
3 ns
•
Downstream Device
7 ns
10 ns
8 ns
2 ns
Answer: PERIOD = 10 ns , OFFSET IN = 7 ns and OFFSET OUT = 8 ns
Global Timing Constraints 7- 34
© 2003 Xilinx, Inc. All Rights Reserved
Summary
•
•
•
•
Performance expectations are communicated with timing constraints
The PERIOD constraint covers delay paths between synchronous
elements
The OFFSET constraint covers delay paths from input pins to
synchronous elements and from synchronous elements to output pins
The Constraints Editor allows you to create timing constraints
Global Timing Constraints 7- 35
© 2003 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
•
Timing Presentation on the Web at http://support.xilinx.com
–
•
Documentation  Technical Tips  Timing & Constraints  Getting
Started  The Timing Presentation
Timing Improvement Wizard on the Web at http://support.xilinx.com
–
Click the Problem Solvers menu
Global Timing Constraints 7- 36
© 2003 Xilinx, Inc. All Rights Reserved