Chapter 3
The concept of the signal
 Process concurrency
 Delta time
 Concurrent and sequential statements
 Process activation by a signal event
 Signal-valued & signal-related attributes
 Exercises

14-Mar-16
EE514
1
The concept of the signal
Signal functions as connection line which transfers information between
circuit parts
Signal properties
•
present and future values
•
timing delay
•
event and transaction
•
signal driver and signal resolution
Multiple drivers
14-Mar-16
EE514
2
Process concurrency

NANXOR code
14-Mar-16
entity NANDXOR is
port (
A, B : in bit;
C : in bit;
D : out bit);
end NANDXOR;
architecture RTL of NANDXOR is
signal T : bit;
begin
p0 : T <= A nand B after 2 ns;
p1 : process (T, C)
begin
D <= T xor C after 3 ns;
end process p1;
end RTL;
EE514
3
Process concurrency
Signal T:bit;
Defines T as the connection signal between NAND and OR gates.
T  AB
and
D T C
Initialization: signals set to their default (left most for their type)
values
Each process is evaluated and then suspended
Active
Signal event
Suspended
Update signal
value
Select a process
by a scheduler
14-Mar-16
Running
EE514
Execution complete
4
Process concurrency
architecture RTL of NANDXOR is
signal T : bit;
begin
p0 : T <= A nand B after 2 ns;
p1 : process (T, C)
begin
D <= T xor C after 3 ns;
end process p1;
end RTL;
14-Mar-16
EE514
5
Delta time
architecture DELTA of NANDXOR is
signal T : bit;
begin
p0 : T <= A nand B;
p1 : process (T, C)
begin
D <= T xor C;
end process p1;
end DELTA;
14-Mar-16
EE514
6
Delta time

Compare Figures 3.5 & 3.6
14-Mar-16
EE514
7
Delta time

Waveforms at time 30
14-Mar-16
EE514
8
Delta time
Delta time
Processes p0, p1 have no time delay,
but if the simulator continues to
increase the delta delay, the delta goes
up infinitely and the simulator may go
into an infinite loop.
14-Mar-16
EE514
9
Concurrent & sequential statements

Concurrent statements

block statement
process statement
generate statement
procedure call statement
assert statement
signal assignment
component instantiation
if statement
case and loop statements
procedure call statement
assert statement
signal assignment statement
variable assignment statement
null, exit, and wait statements
return and next statements
14-Mar-16
Sequential statements
EE514
10
Concurrent & sequential statements
VHDL coding rules




Only concurrent statements can be inside the architecture
statement part.
Sequential statements can only appear inside the procedure
and function body and inside the process statement.
Signals are used to communicate among concurrent
processes.
Local variables can only be declared inside the procedure
and function body and the process statement. They are not
visible outside of the procedure, function, and process
statement.
14-Mar-16
EE514
11
Concurrent & sequential statements

Architecture VHDL code
entity OVERALL is
end OVERALL
architecture RTL of OVERALL is
--architecture declarative part
begin
--architecture statement part
end RTL;
14-Mar-16
EE514
12
Concurrent & sequential statements
14-Mar-16
EE514
13
Process activation by a signal event
architecture SLIST of
NANDXOR is
signal T : bit;
begin
p0 : T <= A nand B;
p1 : process (T)
begin
D <= T xor C;
end process p1;
end SLIST;
14-Mar-16
EE514
14
Process activation by a signal event
T is the sensitivity list of the p1 process (line 5 of SLIST
architecture).
Process is activated by a signal T event.
A process statement requires an explicit wait statement
or a process sensitivity list but not both.
14-Mar-16
EE514
15
Process activation by a signal event
Wrong simulation waveforms of the SLIST
14-Mar-16
EE514
16
Signal-valued & signal-related
attributes


SIG’delayed(T) defines a signal which is the signal SIG
delayed by time T. T=0 ns is the default if parameter T
is not specified.
SIG’stable(T) defines a BOOLEAN signal whose value
is TRUE if signal SIG has not had an event for the
length of time T. T=0 ns is the default if parameter T is
not specified. SIG’stable would be FALSE during the
simulation cycle when SIG is changed and then returns
to TRUE.
14-Mar-16
EE514
17
Signal-valued & signal-related
attributes


SIG’quiet(T) defines a BOOLEAN signal whose value
is TRUE if signal SIG has not had an transaction (not
active) for the length of time T. T=0 ns is the default.
SIG’quiet would be FALSE during the simulation cycle
when SIG is assigned to and then returns to TRUE.
SIG’transaction defines a BIT signal whose value
toggles each time a transaction occurs on signal SIG.
14-Mar-16
EE514
18
Signal-valued & signal-related
attributes



SIG’event is a BOOLEAN typed attribute. It is true if
an event occurs on signal SIG during the current
simulation cycle.
SIG’active is a BOOLEAN typed attribute. It is true if
a tranction occurs on signal SIG during the current
simulation cycle.
SIG’last_event is a TIME typed attribute. It returns
the amount of time elapsed since the last event on
signal SIG.
14-Mar-16
EE514
19
Signal-valued & signal-related
attributes


SIG’last_active is a TIME typed attribute.It returns
the amount of time elapsed since the last transaction on
signal SIG.
SIG’last_value returns the value of signal SIG before
the last event on signal SIG.
14-Mar-16
EE514
20
Exercises
Is it possible for a VHDL
simulator to run forever without
advancing simulation time?
For example, Figure 3.13 shows a
NAND gate with its output
connecting to one of its inputs
entity RUNAWAY is
port (
X : in bit;
Z : out bit);
end RUNAWAY;
architecture RTL of RUNAWAY is
signal T : bit;
begin
T <= X nand T;
Z <= T;
end RTL;
14-Mar-16
EE514
21