Digital Testing:
Design Representation
and Fault Detection
Based on text by S. Mourad
"Priciples of Electronic Systems"
2016/3/14
http://www.talikom.com.my/tester4.jpg
Outline
Design Representation Models
Switching functions
Sensitized Path
Boolean Difference
Fault Detection and Redundancy
Finite State Machines
Tabular Representation
Binary Decision Diagrams
Copyright(c)2001, Samiha Mourad
2
Design Paradigm
The design representation
space consists of domains
and levels
Syst em Level
RT L Level
Behavioral
Domain
Logic Level
Structural
Domain
Behavioral domain most
abstract
A
Circuit Level
P
Structural domain specifies
the architecture
Physical domain include the
transistors and layout
Physical
Domain
Copyright(c)2001, Samiha Mourad
3
Domains and Levels
Table 3.1 Domains and Level of Design
Domain
L
Behavioral
Structural
Physical
System
System Specifications
Blocks
Chip
RTL
RTL Specifications
Registers
Macro Cells
Logic
Boolean Functions
Logic Gates
Standard Cells
Circuit
Differential Equations
Transistors
Masks
E
V
E
L
S
Copyright(c)2001, Samiha Mourad
4
Domains
Behavioral
Domain
a = b+c
z = !(a·d)
b
Structural
Domain
c
a
d
z
Physical
Domain
b
Copyright(c)2001, Samiha Mourad
c
d
5
Levels
Gate Level
c
System Level
b
a
z
d
Circuit Level
Register Level
Clk
Q1
Q8
Q1
Z
ENB
H
Reg. B
Q8
Register
Register
A
A
H
ENB
Reg. A
Adder
Copyright(c)2001, Samiha Mourad
A
C
B
D
6
SPICE Modeling
D
C
IC
CGDO
ID
VGD
VBC
CBD
RD
rc
QBC
VBD
B
VDS
G
rb
IE
VBE
VGS
CGSO
VBS
CGBO
CBS
B
QBE
re
RS
E
S
(a)
(b)
Copyright(c)2001, Samiha Mourad
7
Fault detection and redundancy
Definition:
A test vector t detects a fault t iff Zf (t)  Z(t)
Z(x) - logic function of circuit N
x - input vector
t - a specific input (test) vector
Nf - a faulty circuit (N changes as a result of
fault f)
Fault detection and redundancy
Example :
OR bridging fault between x1 and x2
Consider test t = 011
x1
0
x2
OR
1
x3
1
0
Z1
1
Z2
Fault detection and redundancy
Example :
x1 0
0
Z1
Z1 = x1 x2,
OR
x2 1
Z1f = x1 + x2
Z2 = x2 x3
1 Z2
1
x3
Z2f = (x1 +x2) x3
Z (011) = 01, Zf (011) = 11 => t = 011 detects f
The set of all tests that detect f is given by
Z(x)  Zf(x) =1
Fault activation
Primary inputs
(PI)
X
1
0
0
1
0
1
X
X
Combinational circuit
1/0
Stuck-at-0 fault
Fault effect
1/0
Primary outputs
(PO)
Path sensitization
SPECIFIC-FAULT ORIENTED TEST SET GENERATION
Example: Test for c/0 is w, x, y = 0,1,1
· Activate Fault c/0
· Set x = y = 1 to make c = 1
in Fault-free Circuit
1= x
1= y
w
c/0
· Propagate Value on c to f
· Set w = 0 to sensitize c to f
x
y
0=w
c/0
f
f
Fault detection and redundancy
a set of inputs which detect all possible
(detectable) faults is called a complete
detection test set
an input b = (b1… bn) distinguishes a fault a
from another fault b if Za  Zb or
Za  Zb= 1
a set of tests which distinguish all pairs of
fault is called a complete location test set
Fault detection and redundancy
Example :
Consider fault a= x2 sa1 and b = x3 sa0
• find Z1 , Za & Zb
• check if (101) detects Za
• check if (101) distinguishes Za & Zb
x1
x2
x3
Z
Fault detection and redundancy
Example :
Z = [(x1 x2)’(x2 x3)’]’
= x1 x2 +x2 x3
= x2 (x1 + x3)
a= x2 sa1 and b = x3 sa0
Z  Za | (1,0,1) = Z (x1+x3)=0  1 =1
Za  Zb | (1,0,1) = Z (x1x2)= 1  0 =1
We see that the same vector x=(1,0,1)
distinguishes these two faults
Fault detection and redundancy
If only f out of x faults have been detected by
a test then “test coverage ” is tc = f/x  1
One-dimensional path sensitization
A line whose value changes in the presence of
the fault is sensitized to the fault by the test t.
A path composed of sensitized lines is called a
sensitized path.
Fault detection and redundancy
Example:
consider G2 sa1
x2
0
x3
0
x1
G1
0
1
0
G2 0/1
x4
1
G3
G4
0/1
G5
0/1
Z
Fault detection and redundancy
Path sensitization algorithm
I. specify inputs to generate at the site of the fault
II. propagate error to the output
III. specify inputs to obtain signal values needed in II
IC circuit modification from:
http://www.wintech-nano.com/services_ic
Element evaluation
Truth tables
• requires 2n entries
Input Scanning is simpler
• gates described by
- c -- controlling value
- i -- inversion
c
x
x
c’
x
c
x
c’
x
x
c
c’
ci
ci
ci
c’ i
c
AND 0
OR
1
NAND 0
NOR 1
i
0
0
1
1
Fault detection and redundancy
Lemma:
Gate with c, i - controlling and inversion values
all inputs of G sensitized to f have the same value
(say a)
all not sensitized inputs have value c’
the output of Gate is equal a  i
c
x
x
c’
x
c
x
c’
x
x
c
c’
ci
ci
ci
c’ i
c
AND 0
OR
1
NAND 0
NOR 1
i
0
0
1
1
Fault detection and redundancy
The rules for error propagation
with sensitized inputs equal to a
c i
0 0
0 1
1 0
1 1
Gate
AND
NAND
OR
NOR
Other inputs Output
all must be 1 a
all must be 1 a’
all must be 0 a
all must be 0 a’
Fault detection and redundancy
x2=0
Example :
Diagnose
sa0 fault x1=0
at G2
x3=0
G4=0
G1=1
G5=D’
x1=0
x2=0
x3=0
x2=0
x4=0
G8=D
G2=1
sa0
D
G3=1
x4=1
G6=0
G7=0
Conflicting requirements
x3=0
Fault detection and redundancy
x2=0
Example :
Diagnose
sa0 fault x1=0
x3=0
at G2
G4=0
G1=1
G5=D’
x1=0
x2=0
x3=0
x2=0
x4=0
G8=D
G2=1
sa0
D
G3=1
x4=0
G6=D’
G7=0
x3=0
Detectability
if no test can detect fault f => f is
undetectable
such a circuit is redundant
undetectable fault can prevent detection of
another fault
Detectability
Example : b sa0 is detected by t =1101
A=1
0
a=0
D=1
0
C=0
B=1
1
0/1
1
0/1
b=1/0
1/0
Detectability
Example : b sa0 is no longer detected by t =1101 if
a sa1 is present
A=1
0/1
a=0/1
D=1
0
C=0
B=1
1/0
0
1
0/1
b=1/0
1/0
Detectability
Redundant circuit can always be simplified
by removing a gate or gate input
Rules
Undetectable fault
AND (NAND) input sa1
AND (NAND) input sa0
OR (NOR) input sa0
OR (NOR) input sa1
simplification rule
remove input
remove gate, replace by 0(1)
remove input
remove gate, replace by 1(0)
Detectability
Triple modular redundancy (TMR) is used in fault
tolerant design. TMR is untestable, off line testing
possible for individual modules only
A
A
A
M
Detectability
Redundancy may be used to avoid hazards
Example :
Consider : b=c=1, a changes from 1 to 0
a=1u0
b=111
X=1u0
redundant
Y
F= ab + a’c
= 1u1
c=111
Z=0u1
Boolean Algebra
Boolean function F(x) maps domain B n to B, where B =
{1,0} and F: B n B.
For any element c  B, the constant function is
f(xi)= c, where xi B n
For any xi B n, the projection function is f(xi)= xi
The set of variables {x1, x2, xn} is called the
cube or support of the function
A Boolean function can be expressed in different forms,
for instance
f ( x1 , x2 , x3 )  x1x2 ' x2  x1  x2 ,
Copyright(c)2001, Samiha Mourad
30
Boolean difference
Definition : The Boolean difference of f(x) is equal
D(f) = df(x)/dx = f(x)  f(x’)
An equivalent definition results from the following
Shannon’s law
f(x) = x f(1) + x’ f(0)
Lemma: f(x)  f(x’) = f(0)  f(1)
Then the Boolean difference is
f (x1 , , x i  0 , , x n )  f (x1 , , x i  1, , x n )  1
Boolean difference
Boolean difference of a product is
simple
df(x1x2…xn)/dx1=0 x2…xn= x2…xn
And a Boolean difference of a sum is
df(x1+x2+…+xn)/dx1= (x2+…+xn)1=
= (x2+…+xn)’=x’2…x’n
Boolean difference
Theorem:
Boolean difference can be used to obtain all
tests for stuck-at faults
x sa0 will be tested by input vectors that
satisfy :
T0 = x (df/dx) =1
x sa1 will be tested by
T1 = x’(df/dx) =1
Fault Detection
Consider an example function
f (x) = g (x) +x3,
where g(x) = x1x2 ,
Thus df (x)/dx2 = x3  (x1 + x3) = x3’x1 = 1.
then
x1 = 1 and x3 = 0.
For the SA1 and SA0 faults on x2, the test
patterns are then x1x2x3 = (100) and (110),
respectively.
x1
x2
g
x3
Copyright(c)2001, Samiha Mourad
f
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Fault Detection:
Repeat calculations for stuck-at faults on x3.
df (x)/dx3 = g (x)  1 = x1 x2 1 = (x1 x2)'.
Test patterns to detect all the faults x3/0 and x3/1
are T0=x3 (x1 x2)' = 1 and T1=x3’ (x1 x2)' = 1.
for x3/0, we must have x3x'1 +x3x'2 = 1, this results
in three test patterns: x1x2x3 = (001, 011, or 101)
and for x3/1, we have x1x2x3 = (000, 010, or 100)
x1
x2
g
x3
Copyright(c)2001, Samiha Mourad
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Boolean difference
Example :
Find set of tests for x1 sa1 in the circuit
x2
x3
x1
G1
G2
x4
G3
G4
G5 f
Boolean difference
x2
x3
x1
Example :
T1 = x1’(df/dx1)
= x1’{f(0)  f(1)}
x4
= x1’ [x4  (x2 + x3)]
= x1’(x4x2’x3’ + x4’x2 + x4’x3)
G1
G2
x=0001 is a solution which sensitize
the path x1G2G4G5
G3
G4
G5 f
Boolean difference
1  f ( x )  xf ( 0)  xf (1)
2  f ( x )  xf ( 0)  xf (1)
3
A  ( A  B )  AB
4  A  AB  AB
5  AC  AB  A( C  B )
Transistor level circuit modification on
90nm process from
http://www.wintech-nano.com/services_ic
6  ( A  B)  ( A  C )  A( B  C )
Boolean difference
Example : find the Boolean difference of
f w.r.t. x2
x1
x2
f
Boolean difference
Example :
f ( x )  x1 x2  x1 x2
df
 f (0)  f (1)  x1  x1  0
dx2
df
T0  x2
0
dx2
df
T1  x2
0
dx2
Not testable
Boolean difference
Theorem :
The set of all tests which detect h sa0 is defined by :
df ( x, h)
T0  h( x )
dh
And h sa1 is defined by :
df ( x, h)
T1  h ( x )
dh
TEST PATTERN GENERATION – BOOLEAN DIFFERENCE
df d (cx  yz )

 yz  ( x  yz )  xx(yz)’
( y '  z )  x( y '  z ' )
dc
dc
To Propagate Fault, Set x = 1, y or z =0
v
w
x
a
b
c  v '  w'
For c/1, must set c = 0,
So v = w = 1
c
1
d
h
f
y
z
e
g
j
Test for c/1
v w x y z
1 1 1 0 1
1 1 1 1 0
1 1 1 0 0
Boolean difference
Example :
Find all h sa0 tests
x1
x2
h
x3
x4
f
Boolean difference
Example :
Find all h sa0 tests
x1
x2
f  h  x3 x 4  x 2 x 4
where h  x1 x2
df
T0  h
dh
 h[ f (h  0)  f (h  1)]
h
x3
x4
f
 h[( x3 x 4  x2 x 4 )  1]
 hx3 x 4  x2 x 4
 x1 x2 ( x3  x 4 )( x2 x 4 )
 x1 x2 x3 x 4
Boolean difference
Example :
Find G1 sa1 tests
x2
x3
x1
G1
G2
x4
G3
G4
G5 f
Boolean difference
Example :
Find G1 sa1 tests
x2
x3
x1
G1
G2
G3
G5 f
G4
x4
f  G1 x1  x1 x 4 ,
G1  x2  x3
df
T1  G1
 G1[ f (0)  f (1)]  G1[( x1 x 4  ( x1  x1 x 4 )]
dG1
 x2  x 3  x1 x 4  x1  x2 x3 ( x1  x 4 ) x1  x1 x2 x3
Boolean difference
Boolean difference can be formed by concatenating
Boolean differences (Simple chain rule)
dZ dZ dy

dx dy dx
In the previous example we have :
f  G3  G4 , G3  G1 x1 , G4  x1 x 4
df
df dG3 d (G3  G4 )


x1
dG1 dG3 dG1
dG3
 G4  x1  x1 x 4  x1  ( x1  x 4 ) x1  x1
Boolean difference
Lemma : (Hong Dai)
f ( x1 x 2 )  f ( x1 x 2 )
 x1 x 2 [ f ( 00 )  f (11)]
 x1 x 2 [ f (10 )  f ( 01)]
 x1 x 2 [ f ( 01)  f (10 )]
 x1 x 2 [ f ( 00 )  f (11)]
Boolean difference
Test for multiple faults
for x1 sa0 & x2 sa0
T0  0  x1 x2 ( f ( x1 x2 )  f ( x1 x2 ))
 x1 x2 ( f (11)  f (00))
these results can be extended to more than 2 faults
x1 x2 xn sa0
T00  x1 x2  xn ( f ( x1 x2  xn )  f ( x1 x2  xn ))
 x1 x2  xn ( f (11 1)  f (00  0))
Boolean difference
Test for multiple faults
for x1 sa0 & x2 sa1
T01  x1 x2 ( f ( x1 x2 )  f ( x1 x2 ))
 x1 x2 ( f (10)  f (01))
for x1 sa0  x2 sa0
T0 0  f  f (00)
d2 f
df
df
 x1 x2
 x1 x2
 x1 x2
dx1 x2
dx1
dx2
Finite State Machine
A finite state machine is formally expressed as a 6-tuplet
(I, S, d, S0, O, l), where







I is the finite non-empty set of inputs
S is the finite and non-empty set of states
d:S x I  S is the next state function
S0  S is the set of initial states
O is the set of outputs
l: S x I  O is the output function for a Mealy machine,
l: S  O is the output function for a Moore machine.
Copyright(c)2001, Samiha Mourad
52
Graphical & Tabular Representation
z
I
SET
Combinational
Circuit
Q
D
Z
CLR
Table 3.3 State Table for FSM M
Q
I
PS
NS
Out
0
1
0
1
0
1
0
1
A
A
B
B
C
C
D
D
C
B
C
B
D
C
A
C
1
0
0
1
1
1
1
0
Clk
Graphical Representation (FSM)
Present
State
A
B
C
D
Next
I=0
C,1
C,0
D,1
A,1
State
I=1
B,0
B,1
C,1
C,0
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53
Binary Decision Diagram
x1
1
x1
0
x2
1
1
0
1
0
x2
0
1
0
f =x1x2
(a)
1
0
f = x1 + x2
(b)
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54
Binary Decision Diagram
f
x1
1
x1
1
1
0
1
0
g
0
x2
x1
0
1
0
x2
x3
x2x4 + x2'x3
(a)
x3
x3
x4
x3
1
x4
0
0
1
(b)
f =x1 x2 x4 + x1`x3+ x2`x3
0
1
(c)
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55
Binary Decision Diagram
Binary decision tree and truth table for the function
f(x1, x2, x3) = x1’ x2 ‘x3’ + x1 x2 + x2 x3
BDD for the function f
Wikipedia
56
Test Generation with BDD
f
x1
1
0
To get the Boolean difference for x1 we
need to find paths to x1 =1 and x1 =0 from1
and 0 function values using the same
internal signals (no fork at any node)
so df/d x1 =x2x3’
0
x2
1
f=g+x3=x1 x2 + x3
x3
1
0
1
(a)
0
f
1
g
1
x2
x1
0
The same procedure for internal signal g
0
df/dg=x3’
x3
1
0
1
(b)
0
Copyright(c)2001, Samiha Mourad
57
Test Generation with BDD
f
For Boolean function
f =x1 x2 x4 + x1‘x3+ x2‘x3
Boolean difference to test for x1
s_a faults is
df/d x1 = x2x4x3’ + x2x4’x3
1
1
x1
0
0
x2
x3
1
x4
0
0
1
1
Copyright(c)2001, Samiha Mourad
0
58
Conclusion
Design Representation Models used in Fault
Simulation
Path Sensitization to Detect a Fault
Boolean Difference
Complete Detection and Location Sets
Finite State Machines
Binary Decision Diagrams
Copyright(c)2001, Samiha Mourad
59