Digital Signal Processing
Vref
Analog signal (time
varying, continuous)
Incoming
samples
Analog-toDigital
Converter
(ADC)
0
0x030,
0x4A,
0x12,
0xAF, etc.
Time
Vref
new
waveform
0
Time
Digitalto-Analog
Converter
(DAC)
0x0B3,
0x23,
0xCF,
0x78, etc.
Processor
performs
computation
Outgoing samples
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Applications
• Audio
– Speech recognition
– special effects (reverb, noise cancellation, etc)
• Video
– Filtering
– Special effects
– Compression
• Data logging
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Vocabulary
• ADC (Analog-to-Digital Converter) – converts an analog
signal (voltage/current) to a digital value
• DAC (Digital-to-Analog Converter) – converts a digital
value to an analog value (voltage/current)
• Sample period – for ADC, time between each conversion
– Typically, samples are taken at a fixed rate
• Vref (Reference Voltage) – analog signal varies between 0
and Vref, or between +/- Vref
• Resolution – number of bits used for conversion (8 bits, 10
bits, 12 bits, 16 bits, etc).
• Conversion Time – the time it takes for a analog-to-digital
conversion
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Digital-to-Analog Conversion
For a particular binary code, output a voltage between
0 and Vref
Vref
D[7:0]
Vout
DAC
Assume a DAC that uses an unsigned binary input code,
with 0 < Vout < Vref. Then
D= 0000 0000 Vout = 0V
D= 0000 0001 Vout = Vref(1/256 ) (one LSB)
D = 0000 0010 Vout = Vref(2/256)
...
D = 1111 1111 Vout = Vref(255/256) (full scale)
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DAC Output Plot
Vout
Output signal
increases in 1 LSB
increments.
4/256 Vref
3/256 Vref
2/256 Vref
1/256 Vref
0
1
2
3
Input code
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Typical DAC Output
From http://www.allaboutcircuits.com
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DAC Architecture
Operational
Amplifier can be
used to sum
voltages.
From http://www.allaboutcircuits.com
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DAC Architecture (cont)
Note ratios of
resistors
This is a binary code
From http://www.allaboutcircuits.com
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DAC Architecture (cont)
A 3-bit DAC, called an R/2NR DAC. Resistors are
scaled by powers of 2 (this is hard to do in practice).
From http://www.allaboutcircuits.com
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Another View
Resistance values are still R, 2R, 4R
From http://www.allaboutcircuits.com
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R/2R DAC
Via circuit analysis, can prove this is an
equivalent circuit.
Now only need resistances of R, 2R –
this is easy to do. This is the most
common DAC architecture.
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From http://www.allaboutcircuits.com
11
Commercial DACs
• Either voltage or current DACs
– Current DACs require an external operational amplifier
to convert to voltage
• Precision up to 16-bits
• Key timing parameter is settling time - amount of
time it takes to produce a stable output voltage
once the input code has changed
• We will use an 8-bit voltage DAC with an I2C
interface from Maxim semiconductor
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DAC Application
Phosper
Vertical Deflection
Cathode
R
Red
DAC
Electron Beams
(Red, Green Blue)
G 8 DAC Green
Blue
B 8
DAC
8
Grid
High speed video
DACs produce RGB
signals for color CRT
Horizontal Deflection
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A 1-bit ADC
Vref
analog signal
Vin
R
Vref/2
Vdd
+
Vout=Vdd is Vin > Vref/2
-
Vout=0 if Vin < Vref/2
R
digital signal
comparator
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A 2-bit ADC
R
Vin
+
A
R
3/4Vref
Vin
+
B
-
1/2Vref
R
Vin +
-
1/4Vref
C
A B C
D1 D0
------------0 0 0
0 0
0 0 1
0 1
0 1 1
1 0
1 1 1
1 1
D[1:0]
(other codes
don’t cares)
R
Encoding logic
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ADC Architectures
• The previous architectures are called Flash ADCs
–
–
–
–
–
Fastest possible conversion time
Requires the most transistors of any architecture
N-bit converter requires 2N-1 comparators.
Commercially available flash converters up to 12 bits.
Conversion done in one clock cycle
• Successive approximation ADCs
– Use only one comparator
– Take one clock cycle per bit
– High precision (16-bit converters are available)
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Successive Approximation ADC
First, set DAC to produce
Vref/2.
Output of Comparator is
Q[N-1] (MSB)
If MSB =1 , then Vin
between Vref and Vref/2, so
set DAC to produce ¾ Vref.
If MSB=0, then Vin between
Vref/2 and 0, so set DAC to
½ Vref.
Output of comparator is now
Q[N-2].
Do this for each bit.
Output is Q[N].
From http://www.allaboutcircuits.com
Takes N cycles.
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Commercial ADCs
• Key timing parameter is conversion time – how
long does it take to produce a digital output once a
conversion is started
• Up to 16-bit ADCs available
• Separated into fast/medium/low speed families
– Serial interfaces common on medium/low speed ADCs
• For high-precision ADCs, challenge is keeping
system noise from affecting conversion
– Assume a 16-bit DAC, and a 4.1V reference, then 1 LSB
= 4.1/216 = 62 V.
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ADC, DAC Equations
ADC: Vin = input voltage, Vref = reference voltage
Vref
N = number of bits of precision
Vin/ Vref * 2N = output_code
output_code/ 2N * Vref = Vin
output
code
ADC
Vin
N
1 LSB = Vref/2N
DAC: Vout = output voltage, Vref = reference voltage,
N = number of bits of precision
Vref
Vout/ Vref * 2N = input_code
input_code/ 2N * Vref = Vout
Vout
input
code
DAC
N
1 LSB = Vref/2N
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Sample ADC Computations
If Vref = 5V, and the 10-bit A/D output code is 0x12A, what
is the ADC input voltage?
output_code/2N * Vref = (0x12A)/210 * 5 V
= 298/1024 * 5 V = 1.46 V (Vin)
If Vref = 5V, and the upper 8 bits of the A/D output code is
0xA9, what is the ADC input voltage?
output_code/2N * Vref = (0xA9)/28 * 5 V
= 169/256 * 5 V = 3.3 V (Vin)
If Vref = 4V, and the A/D input voltage is 2.35 V, what is
the ADC output code, upper 8-bits?
Vin/ Vref * 2N = 2.35 V/ 4 V * 28
= .5875 * 256 = 150.4 = 150 = 0x96
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Sample DAC Computations
If Vref = 5V, and the 8-bit input code is is 0x8A, what is
the DAC output voltage?
input_code/2N * Vref = (0x8A)/28 * 5 V
= 138/256 * 5 V = 2.70 V (Vout)
If Vref = 4V, and the DAC output voltage is 1.25 V, what is
the 8-bit input code?
Vout/ Vref * 2N = 1.25 V/4 V * 28
= 0.3125 * 256 = 80 = 0x50 (input_code)
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PIC18 A/D
• PIC18F242 has onboard A/D
–
–
–
–
–
Successive approximation
10 bit resolution
Reference voltage can be Vdd or separate voltage
Multiple input (more than one input channel)
Time per bit(Tad) for conversion is either 2Tosc, 8Tosc, or 32
Tosc, where Tad cannot be less than 1.6 us (Tosc = 1/Fosc)
• Total conversion time is 10* Tad +Taq (acquisition)
– Taq is approximately 20 us; acquisition time is the amount of
time input capacitor requires to charge up to input voltage.
– So a 20 Mhz Fosc, Tosc = .05 us, so 32Tosc = 1.6 us;
conversion time = 10*1.6 us + 20 us = 36 us.
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Input Pins
Analog input channels (AN0,AN1, AN4)
Can be analog
input channels
or Vref+/Vref-
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Channel
select
analog
mux.
A/D Block
Diagram
Vref+/Vref- select
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Acquisition Time
Acquisition time is the time required for the analog input voltage
to be sampled by the input capacitor.
The sampling switch is CLOSED during this time.
When the conversion begins, the sampling switch is OPENED and
the input capacitor holds the input voltage while the conversion is
done.
This process is also called sample and hold.
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Voltage References
Stability of voltage reference is critical for high precision
conversions.
We will use Vdd as our voltage reference for convenience, but will
be throwing away at least two bits of precision due to Vdd
fluctations.
Example Commercial voltage reference: 2.048v, 2.5v , 3v, 3.3v,
4.096v, 5v (Maxim 6029)
5V
Vdd
4.096v
Vref
Key parameter for a voltage is
stability over temperature operating
range. Need this to be less than ½
of a LSB value.
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PIC A/D Registers
• ADCON0, ADCON1 – configuration registers
– ADCON1 used to configure port A for analog/digital
inputs, voltage reference
– ADCON0 used for clock selection, analog input selection,
start/finish conversion status.
• ADRESH, ADRESL -10-bit results returns in two
registers
– 10-bit result can be configured to be left or right justified.
ADRESH : ADRESL
ADRESH : ADRESL
DD DDDDDDDD
00000098 76543210
DDDDDDDD DD
98765432 10000000
Right justified
Left justified
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MAXIM 517 DAC
R/2R DAC
I2C
interface
Not present on
Max517, Vref
instead.
Personalizes device
address
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Max517 I2C Transaction
First byte: Device address
Second Byte: DAC
command byte
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Third Byte:
output byte to
DAC
29
Device Address Format
For Max517, bits [7:3] = 01011
If AD1:AD0 tied to gnd then address is: 01011000 = 0x58
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Command Format
Only command byte we will use for Max517 will be
00000000 = 0x00 as this does a write to DAC0.
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Timing
Max517 DAC has a 6 us settling time.
Requires 3 bytes over I2C bus to write a new value.
At 400Khz, one bit time = 2.5 us.
Each byte is 8 bits + 1 ACK.
So 27 bits * 2.5 us = 67.5 us not counting software overhead. So
we are limited by I2C bus speed, not by the DAC settling time.
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Testing the ADC and DAC
Analog
input
Analog out, To
multimeter or scope
PIC
Vdd
RA0/AN0
Maxim 517
OUT1
OUT0
AD1
SCL
RC3/SCK/SCL
AD0
10K Pot.
RC4/SDI/SDA
SDA
Vdd
If you have trouble
distinguishing which
8-pin DIP in your
parts kit is the
MAX517, look for the
Maxim symbol on the
package.
This diagram assumes that 10K pullups are already on the
SCL/SDA lines from the previous lab.
Read the voltage from the potentiometer via the PIC A/D, write
this digital value to the DAC. The DAC output voltage should
match the potentiometer voltage.
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Potentiometer
Vdd
A variable resistor. Tie outer two legs
to Vdd/GND. Voltage on middle leg
will vary between Vdd/GND as
potentiometer is adjusted, changing the
position of the wiper on the resistor.
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dactest.c
/* A/D Setup */
/* all bits input */
TRISA = 0xFF;
A/D Configuration
/* A0 analog input, others digital,right
justification of result */
ADCON1 = 0x8E;
/* sampling freq = Fsoc/32, channel 0 */
ADCON0 = 0x80;
/* turn on ADC*/
bitset(ADCON0,0);
printf("ADC is configured!!!");
pcrlf();
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dactest.c (cont.)
int adc_value;
for(;;) {
bitset(ADCON0, 2); /* start conversion */
/* wait for end of conversion */
while (bittst(ADCON0,2));
/* read result */
Read from A/D, print
adc_value = 0;
adc_value = adc_value | (ADRESH << 8);
adc_value = adc_value | (ADRESL);
printf("%x",adc_value);
This is a 10-bit value!!!
pcrlf();
dac_value = ((adc_value >> 2)) & 0x00ff;
/* now write to DAC */
update_dac(dac_value);
Only write upper 8
bits to DAC
}
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dactest.c (cont.)
#define DAC 0x58
/* I2C DAC 01011000 */
void update_dac(unsigned char val) {
i2c_WriteTo(DAC);
device address byte
DAC command byte
i2c_PutByte(0x00);
i2c_PutByte(val);
DAC output byte
i2c_Stop();
}
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Modifications to dactst.c
Modify dactest.c to provide four functions:
Multiply by 2
Divide by 2
Invert
Clipped
Vnew = Vold << 1
Vnew = Vold >> 1
Vnew = Vref-Vold
Vmax
‘if’ tests to
check if Vold
in range
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Vmin
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What do you have to know?
• Vocabulary
• DAC R/2N architecture
• ADC Flash, Successive approximation
architectures
• PIC A/D
– How to configure
– Acquisition, Conversion time
– How to start do conversion, read result
• Max517 DAC usage
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