Lecture 6 - Writing Tests
• A difference if treating the design as a black
box or if you have access to internal signals
• EE762 assignment testbenches treat student
design as a black box
• Must know what you are testing
• Must test corner cases
EE694v-Verification-Lect6
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Floating Point Multiplier
• Used as a EE762 assignment
Project Assignment #10
Floating Pt Unit
DUE: Mon Mar 10
In this assignment you will use VHDL to describe the function of a floating point multiplier. The
multiplier will accept IEEE Standard 754 single precision inputs and produce single precision
output. It will support NaN, ±∞, ±0, normalized numbers, and denormalized numbers.
A
B
The interface to the design will be:
latch
Floating Point
M ultiplier
drive
C
EE694v-Verification-Lect6
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The Assignment
Inputs will arrive as per the attached specification and test bench. Your design will latch inputs using the latch input signal.
Your design will drive the outputs using the drive signal. After driving the output, when the drive signal again goes high,
you must drive the bus back to high impedance. Use the component interface given in the testbench
STEP 1) Write the initial architecture. In the initial architecture, simply latch the input, route the A input to the output, and
correctly drive the C bus. If you get this step working correctly the rest will go much easier. SIMULATE
STEP 2) Write a VHDL process to do the floating point multiply.
Recommendation : As you start to write your routine handle special cases first. Write the code to handle the NaNs - then
simulate and check that you handle the NaNs correctly. Note that ±∞ * ±0 results in a NaN.. Then correctly handle ±∞,
and verify through simulation. Then correctly handle ±0 and simulate. Finally do the cases where you actually have to
multiply.
You can use process(es), concurrent signal assignment, etc., as you would like.
You will find the following files in ~degroat/ee762_assign
fpmtb.vhdl - the test bench - the component declaration, configuration,and instantiation
have been done but you can change them if you want to.
fpmvectors - a list of the input stimul
EE694v-Verification-Lect6
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The Assignment (2)
fpm.do - do file for listing and waveform
Other NOTES for floating point multiplier.
The test bench also uses a concurrent procedure call that reads the testvector file in
~degroat/ee762_assign/fpmvectors. Use of these vectors is hard coded in the concurrent procedure as are the checks and
grading routine. This procedure has been compiled and is in the library assign in this directory. To provide the mapping to
it you must execute the unix command
qhmap
assign
/user2/faculty/degroat/ee762_assign/assign
This provides the logical mapping such that the library clause in the test bench know where library assign is located. This
must be done prior to compiling the test bench. The procedure will also do the grading of this assignment.
EE694v-Verification-Lect6
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Floating Point Standard
s
e (8 bits)
31 30 • • •
f (23 bits)
23 22 • • •
0
Single Precision Floating Point Format
Value is
If e = 255 and f ≠ 0, then v is NaN regardless of s
If e = 255 and f = 0, then v = (-1)s ∞
If 0 < e < 255, then v = (-1)s 2e-127 (1.f)
If e = 0 and f ≠ 0, then v = (-1)s 2-126 (x.f)
(denormalized numbers)(x is msb of value stored)
If e = 0 and f = 0, then v = (-1)s 0 (zero)
EE694v-Verification-Lect6
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Other Specifications
•
•
•
•
Inputs are in IEEE 754 Single Precision
Results are in IEEE 754 Single Precision Format
Unit can latch A and B inputs from parallel busses
Must be able to handle both numerical values and
special cases
– NaNs, ±inif,
– ±zero,
– ±normalized numbers, ±denormalized numbers
EE694v-Verification-Lect6
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What to Check
• How to test the floating point multiplier for
both timing of inputs and outputs and
functional operation?
• Assume you have no knowledge of how
design is going to be implemented
EE694v-Verification-Lect6
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The Test Vectors
Must test for normal operation and boundary conditions
A input
NaN
±∞
±0
±Denorm
±Norm
by
B input
NaN
±∞
±0
±Denorm
±Norm
Denorm * OtherVal = Max Denorm
Denorm * OtherVal = Min Norm
•••
Rounding using first guard bit
Rounding using 1st and 2nd guart bits
EE694v-Verification-Lect6
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The Inputs – Example 1
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
...NaN
...Nan
.+INIF
...NaN
01111111100000000000000000000001...NaN
01111111100000000000000000000001
01111111100000000000000000000001.+INIF
01111111100000000000000000000001
01111111100000000000000000000001.-INIF
01111111100000000000000000000001
01111111100000000000000000000001....+0
01111111100000000000000000000001
01111111100000000000000000000001....-0
01111111100000000000000000000001
01111111100000000000000000000001....+1
01111111100000000000000000000001
01111111100000000000000000000001....-1
01111111100000000000000000000001
01111111100000000000000000000001...+25
01111111100000000000000000000001
01111111100000000000000000000001...-25
01111111100000000000000000000001
01111111100000000000000000000001..+100
01111111100000000000000000000001
01111111100000000000000000000001.1/100
01111111100000000000000000000001
01111111100000000000000000000001+DNORM
01111111100000000000000000000001
01111111100000000000000000000001-DNORM
01111111100000000000000000000001
01111111100000000000000000000000...NaN
01111111100000000000000000000001
01111111100000000000000000000001
01111111100000000000000000000000
11111111100000000000000000000000
00000000000000000000000000000000
10000000000000000000000000000000
00111111100000000000000000000000
10111111100000000000000000000000
01000001110010000000000000000000
11000001110010000000000000000000
01000010110010000000000000000000
00111100001000111101011100001010
00000000001010000000000000000000
10000000001010000000000000000000
01111111100000000000000000000001
EE694v-Verification-Lect6
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The Inputs – Example 2
...+25
....+0
...+25
....-0
...+25
...+25
...+25
...-25
...+25
..+625
...+25
..-625
...+25
.+2500
...+25
.+0.25
...+25
small1
...+25
small2
...-25
...NaN
...-25
.-INIF
...-25
.+INIF
...-25
....-0
01000001110010000000000000000000....+0
00000000000000000000000000000000
01000001110010000000000000000000....-0
10000000000000000000000000000000
01000001110010000000000000000000....+1
01000001110010000000000000000000
01000001110010000000000000000000....-1
11000001110010000000000000000000
01000001110010000000000000000000...+25
01000100000111000100000000000000
01000001110010000000000000000000...-25
11000100000111000100000000000000
01000001110010000000000000000000..+100
01000101000111000100000000000000
01000001110010000000000000000000.1/100
00111110011111111111111111111111
01000001110010000000000000000000+DNORM
00000001111110100000000000000000
01000001110010000000000000000000-DNORM
10000001111110100000000000000000
11000001110010000000000000000000...NaN
01111111100000000000000000000001
11000001110010000000000000000000.+INIF
11111111100000000000000000000000
11000001110010000000000000000000.-INIF
01111111100000000000000000000000
11000001110010000000000000000000....+0
10000000000000000000000000000000
00000000000000000000000000000000
10000000000000000000000000000000
00111111100000000000000000000000
10111111100000000000000000000000
01000001110010000000000000000000
11000001110010000000000000000000
01000010110010000000000000000000
00111100001000111101011100001010
00000000001010000000000000000000
10000000001010000000000000000000
01111111100000000000000000000001
01111111100000000000000000000000
11111111100000000000000000000000
00000000000000000000000000000000
EE694v-Verification-Lect6
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Applying Inputs to Design
WHILE (NOT ENDFILE(test_data)) LOOP
--get next input test vector and expected result
readline(test_data,cur_line);
read(cur_line,aid); read(cur_line,a_test_val);
read(cur_line,bid); read(cur_line,b_test_val);
readline(test_data,cur_line);
read(cur_line,resid);read(cur_line,result_val);
std_result_val := To_StdLogicVector(result_val);
num_tests := num_tests + 1;
-- run through bus cycle to send data to unit
aid_sig <= "======", aid after 20 ns;
bid_sig <= "======", bid after 20 ns;
resid_sig <= "======", resid after 20 ns;
-- drive signals on bus
aval <= To_StdLogicVector(a_test_val) after 20 ns, HIGHZ after 80 ns;
bval <= To_StdLogicVector(b_test_val) after 20 ns, HIGHZ after 80 ns;
latch <= '0' after 20 ns, '1' after 70 ns;
wait for 100 ns;
drive <= '0' after 20 ns, '1' after 80 ns;
exp_res <= std_result_val after 20 ns, HIGHZ after 80 ns;
wait for 50 ns;
ASSERT (C = std_result_val)
REPORT "result does not agree with expected result"
SEVERITY WARNING;
IF (C /= std_result_val) THEN
num_errors := num_errors + 1;
err_sig <= '1', '0' after 10 ns;
END IF;
wait for 50 ns;
EE694v-Verification-Lect6
END LOOP;
Inputs are read
from a file and
applied to the
design
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The File I/O Declarations
• First must set up
the basic
declarations
library ieee, assign;
use ieee.std_logic_1164.all;
use ASSIGN.fpm_test_vect.all;
use STD.TEXTIO.all;
entity fpm_test_bench is
end fpm_test_bench;
architecture my_test of fpm_test_bench is
signal A,B,C : std_logic_vector (31 downto 0);
signal exp_res : std_logic_vector (31 downto 0);
signal latch,drive : std_ulogic := '0';
signal aid_sig, bid_sig, resid_sig : string(1 to 6) := "======";
signal err_sig : bit;
signal score : integer := 0;
-- Place your component declaration and configuration here
component fpm
PORT (A,B : IN std_logic_vector (31 downto 0);
latch, drive: IN std_ulogic;
C : OUT std_logic_vector (31 downto 0));
end component;
for all : fpm use ENTITY work.fpm(behavioral);
BEGIN -- test architecture
-- Instantiate your component here
fpm0: fpm PORT MAP(A,B,latch,drive,C);
gen_vec(aid_sig,bid_sig,resid_sig,A,B,exp_res,C,latch,drive,err_sig,sco
re);
end my_test;
EE694v-Verification-Lect6
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File I/O
• And then must
also do the
declarations for
File I/O
• Note that the file
I/O here uses the
1987 version of
the language
library ieee;
use ieee.std_logic_1164.all;
use STD.TEXTIO.all;
package fpm_test_vect is
constant HIGHZ : std_logic_vector (31 downto 0)
:= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
procedure gen_vec (SIGNAL aid_sig,bid_sig,resid_sig : OUT string (1 to
6);
SIGNAL aval,bval,exp_res : OUT std_logic_vector (31
downto 0);
SIGNAL C : IN std_logic_vector (31 downto 0);
SIGNAL latch,drive : OUT std_ulogic;
SIGNAL err_sig : OUT bit;
SIGNAL score : OUT integer);
end fpm_test_vect;
package body fpm_test_vect is
procedure gen_vec (SIGNAL aid_sig,bid_sig,resid_sig : OUT string (1 to
6);
SIGNAL aval,bval,exp_res : OUT std_logic_vector (31
downto 0);
SIGNAL C : IN std_logic_vector (31 downto 0);
SIGNAL latch,drive : OUT std_ulogic;
SIGNAL err_sig : OUT bit;
SIGNAL score : OUT integer) is
variable cur_line : LINE;
file test_data: TEXT is IN
"/rcc4/faculty/degroat/ee762_assign/fpmvectors";
variable a_test_val, b_test_val : bit_vector (31 downto 0);
variable result_val : bit_vector (31 downto 0);
variable std_result_val : std_logic_vector (31 downto 0);
variable aid,bid,resid : string (1 to 6);
variable num_tests,num_errors : integer := 0;
EE694v-Verification-Lect6
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Checking Results
• Timing is checked when result is expected
on bus and again just prior to bus going
back to high impedance.
• Busses are also checked that they go back to
a value of high impedance
• When results do not match what is expected
a signal called error goes to ‘1’ for 10 ns
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