House Alarm FSM (VHDL)
Creating the FSM Model
You have a house alarm which behaves as follows:
1. The alarm has two states, AlarmOn and AlarmOff.
2. When the Reset button is pressed, the alarm is immediately turned off.
3. When the Door is closed (D = 1) and the Pressure pad is inactive (P = 0) then the alarm remains off
4. If the door is opened, then the alarm is turned on and stays on (until the Reset button is pressed)
5. If the pressure pad is activated, then the alarm is turned on and stays on (until the Reset button is pressed)
Task1. Create s state transition diagram for the two states. Make sure you add transitions between the states to
reflect the above behaviour.
Task2. Complete the state transition diagram
Current State
Inputs
D
Next State
Current Output
P
Task3. Look at the lines in this table which have a Next State of 1. Try to find a combination of 2-input logic gates
which take as input {current state, D, P} and give the next state as output.
Task4. Add a D-flop and so complete the “next-state” logic. You may wish to simulate this using a digital logic
simulator (not Vivado) if you wish, to check that your circuit works.
Writing the VHDL Code
Task5. Here you have to write two blocks of code (i) the next state logic and (ii) the output logic. The template file
and the testbench file are zipped on the module website.
The syntax for the next state logic is as follows. Words in italics are names which you have chosen, the symbol ‘X’ is
either logical high ‘1’ or low ‘0’. You must decide what these are. To write the code, start by looking at the state
transition table, starting with all the rows for the first state then continuing with all the rows for the second state.
Note that names s0 and s1 have been chosen for you. These appear in the line of code
type state_type is (s0,s1);
If you choose your own names such as ‘start’ and ‘end’ then you should change this line to look like this
type state_type is (start,end);
case state is
when statename? =>
if(input? = ‘X’) then state <= statename?
elsif (input? = ‘X’) then state <= statename?
end if;
when statename? =>
if(input? = ‘X’) then state <= statename?
elsif (input? = ‘X’) then state <= statename?
end if;
end case;
Note that the second case is needed by the compiler even if you do not need it (there may be no way out of the
state defined by inputs). You should put a dummy case here for example to get the state to return to itself:
when statename1 =>
state <= statename1;
The syntax for the output logic is as follows
output_logic: process(state)
begin
case state is
when statename? => alarm <= ‘X’;
when statename? => alarm <= ‘X’;
end case;
end process;
Task6. Now let’s look at the circuit created by Vivado. To do this start the “Open Elaborated Design” found on
Vivado’s left. This should give you a circuit diagram containing MUXes and a D-Flop. We need to check that this
circuit correctly reproduces the state transition table you saw above.
(a) Start with the first MUX and make a truth table for its output (call it ‘A’) for all value of inputs D and P.
(b) Now look at the second MUX and create its truth table for its output (call it ‘B’) for all values of inputs Current
State (call this ‘C’) and ‘A’.
(c) Combine these two truth tables together to get the output ‘B’ for all possible values of D,P, and C. This should
agree with the state transition table.
Simulating the Circuit using the provided TestBench
Download the associated testbench VHDL code.This is not really adequate since it does not properly test the action
of the floor-pad. The code is shown below.
Task7. Use this code to run a simulation of the circuit and interpret the waveforms produced. The waveforms are
correct, but do not fully test the circuit. Work out why.
Task8. Now change the testbench code (in the tb_input : process block) so that the alarm circuit is fully exercised.
tb_input : process
begin
reset <= '1';
wait for 112 ns;
reset <= '0';
wait for 135 ns;
door <= '1';
pad <= '0';
wait for 160 ns;
door <= '0';
wait for 160 ns;
door <= '1';
wait for 160 ns;
pad <= '1';
wait for 160 ns;
pad <= '0';
wait for 160 ns;
reset <= '1';
wait;
end process;
-- apply a reset signal
-- drop the reset signal to zero
-- door initially closed
-- pad initially not activated
-- door opened
-- door closed again
-- now activate the pad
-- now deactivate the pad
-- alarm reset