C166 Family-High Performance
16-Bit Microcontrollers
C161
SAB-C167CR
XRAM XRAM
1KByte 1KByte
RAM
1KByte
CAN
BUSCONTROL
RAM
1KByte
C163






C164
SAB 8xC166
C167x
C165
C163
C164x
C161x
C165
C166
C167
CORE
ROM
PWM
ADC
INTERRUPT IR+PECCONTROL
UNIT
WDT
GPT
USART
1+2
CAPCOM SSC
1+2
The Reference Class
Microcontrollers
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1-1
C166 Family
The Three Subsystems
C161
C163
ROM /
Flash
C164
Processor -System
C165
CPU
C166
RAM
C167
Interrupt-System
OSC.
Ext..
Bus
Control
X-Bus
Peripheral.
USART
ADC
GPTs
PEC
WDT
CAPCOM
Sync Communication
PWM
Peripheral-System
PORTS
The Reference Class
Microcontrollers
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1-2
C166 Family
The Best of Both Worlds
C161
Microcontrollers:
Microprocessors:
Control oriented instruction set
optimized event handling
“System on Silicon”
High computational power
high data throughput
good addressing capabilities
HLL-supporting architecture
C163
C164
C165
C166
C167
ROM /
Flash
Processor -System
CPU
Interrupt-System
OSC.
Ext..
X-Bus
Bus
Control
Periphrl.
USART
ADC
GPTs
RAM
PEC
WDT
CAPCOM
Sync Communication
PWM
Peripheral-System
PORTS
The Reference Class
Microcontrollers
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1-3
The Modular Concept
C161
Downgraded
Core
Processor
Core
C163
C164
C165
n x 4 KB
ROM
Internal
ROM
OSC.
n x 8 KB
Flash-EPROM
Internal
RAM
CPU
Interrupt Controller
C166
n x 512 B
RAM
C167
WDT
PEC
Ext..
10-bit
Bus
ADC USARTs GPTs CAPCOM
Control
PORTS
Different Mix
+ CAN
More AD-Ch.
More I/O
The Reference Class
+ PWM
Microcontrollers
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Four Bus Modular System
X Bus Modules
SSP
XRAM
ROM
8K
Flash
128K
ROM
32K
New
Modules
New
Modules
Core
C165
RAM
1k
2x16 bit
Flash
32K
C164
C166
16 - b i t
32 bit
OTP
64K
C163
New
Modules
I²C
Flash
64K
C161
CAN
16 - b i t
C167
RAM
1k
New
Modules
ADC
Timers
USART
SSC
CAPCOM
WDT
Ports
New
Modules
Basic Library Modules
The Reference Class
Microcontrollers
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1-5
Highly Integrated
* 16 M Address Range
* 2/4 KByte RAM
* 32 CAPCOM
* 4 PWM
* 2 Serial Interface
* 5 Timer
* Chip Selects
Benefits in System
Integration
* Extensive I/O
C167CR
C167SR
C167S
C167
* 2KB RAM
* 32K ROM
* 2KB RAM
* PLL
* CAN
* 4K RAM
* PLL
* 2KB RAM
* PLL
C161
C163
C164
General Purpose
C165
Balanced Peripheral
set for a broad
Application Ranges:
Price differentiation:
* 1K / 2 KB RAM
* ROM / Flash / OTP
* CAPCOM
* PWM
* Serial Interfaces
* Timer
* 10-bit / 8bit ADC
* full Bus Support/
MUX Bus only
C164
8xC166
* 1KB RAM
* 32KB ROM
* 32KB Flash
* P-MQFP-100
C166
* 2KB RAM
* 64KB OTP/ROM/Flash
* Full-CAN 2.0B active
* Power Management / RTC
* CAPCOM6
* P-MQFP-80
C167
Low Cost
Processor Oriented
* different RAM Size
* up to 16 M Addr. Range
* up to 5 Timers
* Serial Interfaces
SSP, SSC
Roadmap
C165
* less Chip Selects
* full Bus Support/ * 2KB RAM
MUX Bus only
* 3V
* 3 V Options
* P-TQFP-100
* 25 MHz Option
C163
* 1KB RAM
* SSP
* 3V
* reduced Peripherals
* P-TQFP-100
C161x
* 16MHz CPU
* 4 M address
* 1-2KB RAM
* Pwr. Man. / RTC
* P-MQFP-80/100
Microcontrollers
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Numbering Scheme
8xC166 Products
C161
Prefix
Memory
Type Code
ROMLess
80
Type
Designation
Memory
Size Code
83
C166
5
M
C166W
5
M
5
M
5
M
(-)
C166
C166W
(-)
M
(-)
M
32KBytes
88
Flash EEPROM
Overview
Temp. Range
Code
(-)
T3
(-)
T3
T4
(-)
T3
(-)
T3
T4
(-)
Metal Mask ROM
SAB
Package
Code
C166
C166W
W = without prescaler
M = Metric
Quad Flatpack
C163
0° / 70°
-40° / 85°
0° / 70°
-40° / 85°
-40° / 110°
0° / 70°
-40° / 85°
0° / 70°
-40° / 85°
-40° / 110°
0° / 70°
0° / 70°
C164
C165
C166
C167
(-) no suffix
Microcontrollers
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Numbering Scheme
C161/C163/165 Products
Prefix
Temp. Range
Code
B
Type
Designation
C161V / K / O*
Memory Code
Size
Type
(-)
CPU
Freq.
Package
Code
16
M
L
C161
C163
C164
C165
SA
B
B,F
B,F
C163
(-)
(-)
16
L
L
F
(-)
25
25
F
F
F
(-)
25
M,F
M,F
C166
C167
128kB FLASH
B,F
C165
later on
* difference
in this Foilset
B = 0/ 70 °C
F = -40/ 85 °C
Overview
(-)
L
R
4KB Metal Mask ROM
(-) = 0kB
16 = 128kB
L = ROMless
R = MASK ROM
F = FLASH
M = Metric Quad Flatpack
F = Thin Quad Flatpack
Microcontrollers
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3-8
Numbering Scheme
C164 Products
C161
C163
C164
Prefix
Temp. Range
Code
Type
Designation
Memory Code
Size
Type
CPU
Freq.
Package
Code
C165
C166
SA
B,F,H,K
C164CI
(-)
8
8
L
E
R
(-)
(-)
(-)
M,F
M,F
M,F
C167
64KB OTP
B = 0/ 70 °C
F = -40/ 85 °C
H = -40/ 110°C
K = -40/ 125°C
Overview
(-) = 0kB
8 = 64kB
L = ROMless
R = MASK ROM
E = EPROM
M = Metric Quad Flatpack
F = Thin Quad Flatpack
Microcontrollers
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3-9
Numbering Scheme
C167 Products
C161
Prefix
Temp. Range
Code
B,F
SA
Type
Designation
C167
Memory Code
Size
(-)
L
C167S
B,F,K
C167SR
(-)
32KBytes
C167CR
4*
(-)
R*
L
C167CR
F
B
Mask ROM
16*
C163
C164
M
C165
B
B, F, K
4
ROMLess
Type
Package
Code
R
M
C166
L
M
C167
M
M
Flash
M
128KBytes
B, F,K
B= 0/ 70 °C
F= -40/ 85 °C
K= -40/110 °C
Overview
C167CR
C= CAN Interface
R= 2KBytes XRAM
16*
R*
M
M= Metric Quad Flatpack
Microcontrollers
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C166-Core
Dual Port
16
Data
no
CPU
Instr./Data
ROM
Data
32
16
RAM
1 KByte
C161
C163
OSC
XTAL
input: 16MHz;
prescaler
or direct drive
C164
PEC
4
XBUS (16-bit NON MUX Data / Addresses)
no
X-Bus
Peripheral
External Instr./Data
C165
Watchdog
Interrupt Controller
Peripheral Data
16
GPT1
External Bus,
USART
Sync. Channel
(SPI)
T3
ASC
SSC
T4
BRG
BRG
T2
MUX only
XBUS Control,
no CS Logic,
16
Port 5
Port 3
Port 2
6
16
C167
16
Interrupt Bus
Port 1
C166
5 ext. IR
2
Overview - C161V Block Diagram
12
161V
7
Microcontrollers
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16
Dual Port
C166-Core
Data
no
CPU
Instr./Data
ROM
Data
32
RAM
1 KByte
16
C161
C163
OSC
XTAL
C164
(input: 16MHz;
prescaler
or direct drive)
PEC
4
XBUS (16-bit NON MUX Data / Addresses)
no
X-Bus
Peripheral
External Instr./Data
C165
Watchdog
Interrupt Controller
C166
5 ext. IR
C167
16
Interrupt Bus
Peripheral Data
16
GPT1
External Bus,
USART
Sync. Channel
(SPI)
T3
ASC
SSC
T4
BRG
BRG
T2
XBUS Control,
2 x CS Logic
16
Port 1
Port 5
Port 3
Port 2
161K
6
16
2
Overview - C161K Block Diagram
12
7
Microcontrollers
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16
Dual Port
C166-Core
Data
no
CPU
Instr./Data
ROM
Data
32
RAM
2 KByte
16
C161
C163
OSC
XTAL
C164
(input: 16MHz;
prescaler
or direct drive)
PEC
4
XBUS (16-bit NON MUX Data / Addresses)
no
X-Bus
Peripheral
External Instr./Data
Interrupt Controller
C165
Watchdog
C166
11 ext. IR
C167
16
Interrupt Bus
Peripheral Data
16
GPT1
External Bus,
GPT2
USART
Sync. Channel
(SPI)
T3
T5
ASC
SSC
T4
T6
BRG
BRG
T2
XBUS Control,
4 x CS Logic
16
Port 1
Port 5
Port 3
Port 2
161O
6
16
2
Overview - C161O Block Diagram
12
7
Microcontrollers
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16
Dual Port
C166-Core
Data
no
Instr./Data
ROM
Data
CPU
32
RAM
1 KByte
16
C161
C163
OSC
XTAL
(input: 16MHz;
prescaler
or direct drive)
C164
Watchdog
PEC
C165
I2C-Bus
XRAM
2 KByte
8
XBUS (16-bit NON MUX Data / Addresses)
External Instr./Data
RTC
Interrupt Controller
Interrupt Bus
16
External Bus,
XBUS Control,
5 x CS Logic
C166
11 ext. IR
C167
16
Peripheral Data
8-bit
ADC
4 Channels
USART Sync.
Channel
(SPI)
ASC
SSC
BRG
BRG
GPT1
GPT2
T2
T5
T
3
T4
T6
16
Port 1
Port 5
Port 3
Port 2
161 RI
7
16
6
Overview - C161RI Block Diagram
15
8
Microcontrollers
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16
Dual Port
C166-Core
up to
128 KByte
Flash
EPROM
Data
CPU
Instr./Data
Data
32
RAM
RAM
KByte
11 KByte
16
C161
C163
PLL
XTAL
C164
progr. multiplier
(W/0.5/1.5/2/../5)
PEC
C165
SSP
Module
12.5 Mbit/s
8
XBUS (16-bit NON MUX Data / Addresses)
External Instr./Data
Watchdog
Interrupt Controller
C166
11 ext. IR
C167
16
Interrupt Bus
16
Peripheral Data
GPT1
External Bus,
GPT2
USART
T3
T5
T4
T6
ASC
BRG
T2
XBUS Control,
5 * CS Logic
16
Port 5
Port 1
Port 2
Port 3
163
8
16
6
Overview - C163 Block Diagram
16
8
Microcontrollers
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C166-Core
16
Dual Port
64 K
ROM
Data
(C164 Cl-8-RM)
or OTP
Instr./Data
CPU
32
C164-8EM)
Data
RAM
2 KByte
16
C161
C163
Watchdog
0.5; 1; 1.5; 2;
2.5; 3; 4; 5
16
6
Port 4
RTC
C166
13 ext. IR
C167
16
Interrupt Bus
16
Peripheral Data
External Bus,
(8/16 bit;
MUX only
&
XBUS
Control
10-Bit USART Sync.
Channel
ADC
(SPI)
8-Channels
Port 5
8
ASC
BRG
SSC
BRG
GPT1 CAPCOM 2
T2
T
3
T4
Port 3
9
Overview - C164CI Block Diagram
8-Channel
Port 8
4
CAPCOM6 Unit for
PWM Generation
Timer 13
Interface
V2.0B
active
Interrupt Controller
C165
Timer 8
P 4.6/ CAN TxD
Full-CAN
XBUS (16-bit NON MUX Data / Addresses)
P4.5/ CAN RxD
C164
PEC
External Instr./Data
Timer 7
XTAL
PLL-Oscillator
prog. Multiplier:
1 Comp.
Channel
3/6 CAPCOM
Channels
Port 1
164 CL
16
Microcontrollers
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C166-Core
no
ROM
Dat
a
CPU
Instr./Dat
a
Dual Port
16
Dat
a
32
16
RAM
2 KByte
C161
C163
XTAL
OS
C
C164
CPU clock:
20 / 25 MHz
PEC
8
XBUS (16-bit NON MUX Data / Addresses)
X-Bus
Peripheral
External
Instr./Data
Interrupt Controller
C165
Watchdog
Peripheral
Data
GPT
1
External Bus,
T
2
T
3
T
4
XBUS Control,
5 * CS Logic
16
Port 1
C167
16
Interrupt Bus
16
C166
12 ext. IR
GPT2
USART
AS
C
BRG
T
5
T
6
Sync.Channel
(SPI)
SS
C
BRG
Port 5
Port 3
Port 2
6
16
8
165
8
16
Overview - C165 Block Diagram
Microcontrollers
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Dual Port
16
up to
32 KByte
ROM/
FlashEPROM
Data
SAB 8xC166
CPU CORE
Instr./Data
32
Data
RAM
1 KByte
C161
16
C163
XTAL
C164
OSC
PEC
External Instr./Data
C165
Watchdog
Interrupt Controller
C166
19 ext. IR
C167
16
Interrupt Bus
Peripheral Data
10-Bit
ADC
Bus
16 Channels
USART
USART
GPT1 GPT2
T2
Controller
ASC
BRG
ASC
BRG
T3
T5
T4
T6
Timer 1
External
CAPCO
M
Timer 0
16
16
Port 1
Port 5
Port 3
Port 2
2
16
10
16
16
Overview - SAB 80C166 Block Diagram Microcontrollers
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C166-Core
16
128 KByte
ROM/
Flash
EPROM
Dat
a
CPU
Instr./Dat
a
Dual Port
up to
Dat
a
32
16
RAM
2 KByte
C161
C163
PLL
OS
(output: 20MHz)
C
PEC
External
Instr./Data
Interrupt Controller
C165
Watchdog
C167
16
Interrupt Bus
Peripheral
Data
External Bus,
ADC
16 Channels
USART Sync.
Channel
(SPI)
AS SS
C BRG
C
BRG
GPT GPT2
1
T2
T3
T5
T4
T6
CAPCOM1, 2
Timer
0
10-Bit
32
Channels
Timer
8
Multi Funktional
Timer
1
16
XBUS Control,
5 * CS Logic
C166
36 ext. IR
Timer
7
2KB
XRAM
8
C164
(input: 5
MHz)
XBUS (16-bit NON MUX Data / Addresses)
XTAL
PWM Module
PT
1
PT
2
PT
3
PT
4
16
8
Port 1
16
Port 5
16
Port 3
16
Overview - C167 Block Diagram
Port 2
16
Port 8
8
Port 7
167
8
Microcontrollers
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3 - 19
C166-Core
128
KByte
ROM/
EPRON
FLASH
Dat
a
CPU
Instr./Dat
a
Dual Port
16
Dat
a
32
RAM
2 KByte
16
C161
C163
PLL
C164
(input: 5
MHz)
OS
(output: 20MHz)
C
Interrupt Controller
2.0 B active
16 Channels
Channel
(SPI)
AS SS
C BRG
C
BRG
GPT GPT2 CAPCOM1, 2
1T
2
T
3
T
4
Timer
0
8
USART Sync.
T5
T6
32
Channels
Timer
8
10-Bit
ADC
Timer
1
MultiFunktional
XBUS Control,
5 * CS Logic
C167
16
Peripheral
Data
16
External Bus,
C166
36 ext. IR
Interrupt Bus
Addresses)
2KB XRAM
C165
Watchdog
Timer
7
CAN
PEC
External
Instr./Data
XBUS (16-bit NON MUX Data /
XTAL
PWM Module
PT
1
PT
2
PT
3
PT
4
16
Port 1
Port 5
Port 3
Port 2
Port 8
Port 7
167CR
8
16
16
15
Overview - C167CR Block Diagram
16
8
8
Microcontrollers
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Overview (16MHz)
C161
 Complete 16-bit architecture with 32-bit bus to the internal
ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV)
operands
 16 MHz CPU clock results in an instruction cycle time of
125ns which guarantees highest CPU performance
 To avoid an accumulator bottleneck
16 General Purpose Register (GPR) are implemented
Up to 16 GPRs from a register bank
Any register bank is freely locatable in internal RAM
 Easy and efficient programming is supported by powerful
instructions combined with complex addressing modes
 Transparent programming of the on-chip peripherals via
an universal Special Function Register (SFR) interface
C163
C164
C165
C166
C167
-
CPU
Microcontrollers
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Overview (20MHz)
C161
 Complete 16-bit architecture with 32-bit bus to the internal
ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV)
operands
 20 MHz CPU clock results in an instruction cycle time of
100ns which guarantees highest CPU performance
 To avoid an accumulator bottleneck
16 General Purpose Register (GPR) are implemented
Up to 16 GPRs from a register bank
Any register bank is freely locatable in internal RAM
 Easy and efficient programming is supported by powerful
instructions combined with complex addressing modes
 Transparent programming of the on-chip peripherals via
an universal Special Function Register (SFR) interface
C163
C164
C165
C166
C167
-
CPU
Microcontrollers
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Overview (25MHz)
C161
 Complete 16-bit architecture with 32-bit bus to the internal
ROM to process 8-bit, 16-bit and even 32-bit (MUL/DIV)
operands
 25 MHz CPU clock results in an instruction cycle time of
80ns which guarantees highest CPU performance
 To avoid an accumulator bottleneck
16 General Purpose Register (GPR) are implemented
Up to 16 GPRs from a register bank
Any register bank is freely locatable in internal RAM
 Easy and efficient programming is supported by powerful
instructions combined with complex addressing modes
 Transparent programming of the on-chip peripherals via
an universal Special Function Register (SFR) interface
C163
C164
C165
C166
C167
-
CPU
Microcontrollers
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Block Diagram
ROM / RAM interaction
C161
C163
STK UV
CPU
Exec. Unit
Instr. Ptr.
MDH
SP
MDL
STK OV
Mul./Div.-HW
STK UV
Instr. Reg.
32
On-Chip
(EP)ROM
4-Stage
Pipeline
Bit-Mask Gen.
ALU
PS
W
SYSCON
C164
16-bit
Barrel-Shifter
BUSCON 1
R15
CPU
Context Ptr.
C165
On-Chip
Static
RAM
C166
C167
R15
General
Purpose
Registers
ADDRSEL 1
Data Page
Pointer
16
STK OV
16
R0
R0
Code Seg.Ptr
Microcontrollers
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Block Diagram
ROM / RAM interaction
C161
C163
STK UV
CPU
32
On-Chip
(EP)ROM
Exec. Unit
MDH
SP
Instr. Ptr.
MDL
STK OV
Mul./Div.-HW
STK UV
Instr. Reg.
4-Stage
Pipeline
16
Bit-Mask Gen.
R15
STK OV
C165
On-Chip
Static
RAM
C166
C167
R15
ALU
PS
W
SYSCON
BUSCON 0
16-bit
Barrel-Shifter
BUSCON 1
ADDRSEL 1
BUSCON 2
ADDRSEL 2
BUSCON 3
ADDRSEL 3
BUSCON 4
ADDRSEL 4
Data Page
Pointer
CPU
C164
Context Ptr.
General
Purpose
Registers
16
R0
R0
Code Seg.Ptr
Microcontrollers
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General Purpose Register
(GPR)
C161
 Up to 16 GPRs = 1 Register bank
Consisting of max.
8 Word-Registers
8 Word-Registers with lower and higher Byte access
 The GPRs are bit-addressable
 Any Register bank can be freely allocated in internal RAM
 The location of the active Register bank is determined by
Context Pointer (CP)
 CP can be easily switched, to select another Register bank
 SWTC (one instruction cycle)
C163
-
CPU
Microcontrollers
C164
C165
C166
C167
HL MC AT, lehmann
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Block Diagram
ROM / RAM interaction with 1K RAM
C161
C163
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
R15
R14
R13
R12
R11
R10
R9
R
8
C164
1KBytes
internal RAM
C165
0FDFE
C166
R15
C167
RL7
RL6
RL5
RL4
RL3
RL2
RL1
RL0
R7
R6
R5
R4
R3
R2
R1
R
0
R
0
Context pointer
0FC00 STKUV
Stackpointer Underflow STKUV
Stackpointer
Stackpointer Overflow STKOV
0FA00 STKOV
CPU
Microcontrollers
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Block Diagram
ROM / RAM interaction with 2K RAM
C161
C163
RH7
RH6
RH5
RH4
RH3
RH2
RH1
RH0
R15
R14
R13
R12
R11
R10
R9
R
8
C164
2KBytes
internal RAM
C165
0FDFE
C166
R15
C167
RL7
RL6
RL5
RL4
RL3
RL2
RL1
RL0
R7
R6
R5
R4
R3
R2
R1
R
0
R
0
Context pointer
0FC00 STKUV
Stackpointer Underflow STKUV
Stackpointer
Stackpointer Overflow STKOV
0F600 STKOV
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 16 MHz
C161
 Effective execution time of most instruction in 125 ns
 Three word prefetch queue (buscontroller) to support
pipeline
 Optimized branch processing
For branch instruction (Jump, Cond. Jump, Call, Return,...)
only one additional machine cycle is normally required to
fetch target instruction
 Jump Cache
For loop processing no additional machine cycle is required
C163
C164
C165
-
C166
C167
-
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 16 MHz
C161
C163
C164
Processing of each instruction is partitioned in 4 stages
C165
C166
Fetch
Decode
1. Instr.
2. Instr. 3. Instr.
4. Instr.
C167
Execute
Write Back
Time
1 Machine Cycle = 125 ns at 16 MHz CPU clock
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 20 MHz
C161
 Effective execution time of most instruction in 100 ns
 Three word prefetch queue (buscontroller) to support
pipeline
 Optimized branch processing
For branch instruction (Jump, Cond. Jump, Call, Return,...)
only one additional machine cycle is normally required to
fetch target instruction
 Jump Cache
For loop processing no additional machine cycle is required
C163
C164
C165
-
C166
C167
-
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 20 MHz
C161
C163
C164
Processing of each instruction is partitioned in 4 stages
C165
C166
Fetch
Decode
1. Instr.
2. Instr. 3. Instr.
4. Instr.
C167
Execute
Write Back
Time
1 Machine Cycle = 100 ns at 20 MHz CPU clock
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 25 MHz
C161
 Effective execution time of most instruction in 80 ns
 Three word prefetch queue (buscontroller) to support
pipeline
 Optimized branch processing
For branch instruction (Jump, Cond. Jump, Call, Return,...)
only one additional machine cycle is normally required to
fetch target instruction
 Jump Cache
For loop processing no additional machine cycle is required
C163
C164
C165
-
C166
C167
-
CPU
Microcontrollers
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Four Stage Instruction Pipeline
at 25 MHz
C161
C163
C164
Processing of each instruction is partitioned in 4 stages
C165
C166
Fetch
Decode
1. Instr.
2. Instr. 3. Instr.
4. Instr.
C167
Execute
Write Back
Time
1 Machine Cycle = 80 ns at 25 MHz CPU clock
CPU
Microcontrollers
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Instruction Set at 16 MHz
C161
 Data manipulation
Arithmetic and boolean instruction incl. fast multiply/divide
in 0.6/1.2µs
Multiple (up to 15) bit shift and rotate in 125 ns
Bit to bit manipulation in internal RAM and SFR’s
 Data movement
MOV instructions with all important addressing modes
Byte to word conversion
System stack (PUSH, POP) with over- and underflow
control
User stack (MOV with auto increment and decrement)
 ...
-
CPU
Microcontrollers
C163
C164
C165
C166
C167
HL MC AT, lehmann
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...Instruction Set at 16 MHz
 Program manipulation
Jumps and calls / conditional jumps under 16 different
conditions
Software- and hardware-Traps
Fast context switching in 125 ns
C161
 Special instructions for
Power consumption reduction and system Control
Non-interruptable instruction sequences
Extended addressing access
C167
-
C163
C164
C165
C166
-
CPU
Microcontrollers
HL MC AT, lehmann
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Instruction Set at 20 MHz
C161
 Data manipulation
Arithmetic and boolean instruction incl. fast multiply/divide
in 0.5/1.0us
Multiple (up to 15) bit shift and rotate in 100 ns
Bit to bit manipulation in internal RAM and SFR’s
 Data movement
MOV instructions with all important addressing modes
Byte to word conversion
System stack (PUSH, POP) with over- and underflow
control
User stack (MOV with auto increment and decrement)
 ...
-
CPU
Microcontrollers
C163
C164
C165
C166
C167
HL MC AT, lehmann
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...Instruction Set at 20 MHz
 Program manipulation
Jumps and calls / conditional jumps under 16 different
conditions
Software- and hardware-Traps
Fast context switching in 100 ns
C161
 Special instructions for
Power consumption reduction and system Control
Non-interruptable instruction sequences
Extended addressing access
C167
-
C163
C164
C165
C166
-
CPU
Microcontrollers
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...Instruction Set
at 20 MHz on the 8xC166
 Program manipulation
Jumps and calls / conditional jumps under 16 different
conditions
Software- and hardware-Traps
Fast context switching in 100 ns
C161
 Special instructions for
Power consumption reduction and system Control
C167
-
C163
C164
C165
C166
-
CPU
Microcontrollers
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Instruction Set at 25 MHz
C161
 Data manipulation
Arithmetic and boolean instruction incl. fast multiply/divide
in 0.4/0.80µs
Multiple (up to 15) bit shift and rotate in 80 ns
Bit to bit manipulation in internal RAM and SFR’s
 Data movement
MOV instructions with all important addressing modes
Byte to word conversion
System stack (PUSH, POP) with over- and underflow
control
User stack (MOV with auto increment and decrement)
 ...
-
CPU
Microcontrollers
C163
C164
C165
C166
C167
HL MC AT, lehmann
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...Instruction Set at 25 MHz
 Program manipulation
Jumps and calls / conditional jumps under 16 different
conditions
Software- and hardware-Traps
Fast context switching in 80 ns
C161
 Special instructions for
Power consumption reduction and system Control
Non-interruptable instruction sequences
Extended addressing access
C167
-
C163
C164
C165
C166
-
CPU
Microcontrollers
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Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
up to 8 MBytes address space
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
no ROM
1 KByte SFR's
-
RAM
Memory
C161V
C161K
C161O
C161RI
1 KByte
1 KByte
2 KByte
3 KByte
Microcontrollers
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...Address Space
C161
 Flexible ext. bus configurations to simplify system
integration
up to 22-bit Address / 8-bit Data MUX
up to 22-bit Address / 16-bit Data MUX
Five completely independent configuration registers
0-5 programmable chip selects and programmable bus
control signal to save external glue-logic
C163
-
Memory
Microcontrollers
C164
C165
C166
C167
HL MC AT, lehmann
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Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
up to 16 MBytes address space
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
up to 128 KBytes ROM / Flash-EPROM
1 KByte SFR's
-
Memory
Microcontrollers
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C164RI
Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
up to 16 MBytes address space
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
1 KByte SFR's
2 KByte RAM
64 KByte of OTP ROM
-
Memory
Microcontrollers
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C164RI
...Address Space
C161
 Flexible ext. bus configurations to simplify system
integration
up to 22-bit Address / 8-bit Data (MUX)
up to 22-bit Address / 16-bit Data (MUX)
Five completely independent configuration registers
Programmable bus control signal to save external gluelogic
C163
-
Memory
Microcontrollers
C164
C165
C166
C167
HL MC AT, lehmann
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Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
up to 16 MBytes address space
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
no ROM
1 KByte SFR's
2 KByte RAM
-
Memory
Microcontrollers
HL MC AT, lehmann
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Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
64KByte non-segmented address space
up to 16 MBytes
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
up to 32 KBytes ROM / Flash-EPROM
1 KByte SFR's
-
Memory
83 C166
88 C166
RAM
1 KByte
1 KByte
ROM
32 KByte
32 KByte Flash
Microcontrollers
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...Address Space
C161
 Flexible ext. bus configurations to simplify system
integration
up to 18-bit Address / 8-bit Data (MUX and NMUX)
up to 18-bit Address / 16-bit Data (MUX and NMUX)
Two on 80C166 completely independent configuration
registers
Programmable HOLD/HOLDA/BREQ bus arbitration
function for multi-master operations
C163
-
Memory
Microcontrollers
C164
C165
C166
C167
HL MC AT, lehmann
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Address Space...
C161
 Complete address space
“von Neumann” architecture with multiple internal bus
structure to avoid bus bottlenecks
64KByte non-segmented address space
up to 16 MBytes
segmented address space: 64KB code segments and 16K
data pages
-
C163
C164
C165
C166
C167
 Internal address space
up to 128 KBytes ROM / Flash-EPROM
max 4 KByte SFR's
-
RAM
ROM
Memory
C167
C167CR
4 KByte
4 KByte
128 KByte Flash 128 KByte Flash
Microcontrollers
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...Address Space
C161
 Flexible ext. bus configurations to simplify system
integration
up to 24-bit Address / 8-bit Data (MUX and NMUX)
up to 24-bit Address / 16-bit Data (MUX and NMUX)
Five completely independent configuration registers
Five programmable chip selects and programmable bus
control signal to save external glue-logic
Programmable HOLD/HOLDA/BREQ bus arbitration
function for multi-master operations
C163
-
Memory
Microcontrollers
C164
C165
C166
C167
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Internal and external
Memory Map
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
C161V, C161K,
C161O, C161RI:
C161O:
Internal
RAM
Internal
RAM
Reserved
512 Bytes
Ext. SFR’s
C161RI:
0.5K
0FE00
1K
0FA00
1K
0F600
4 MBytes external
16 MByte internal
Code Segments
Data Pages
3FFFF
15
30000
0.5K
0F000
On-Chip XRAM
13
2
C164
C166
12
C167
11
0F200
C163
C165
14
3
10
9
20000
I²C
Reserved
C161RI:
10000
C161
8
7
0E800
2K
0E000
1
6
5
10000
4
3
Bit Addressable Space
X-Bus Peripheral
Memory
External
Memory
0
2
1
00000
0
Microcontrollers
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Internal and external
Memory Map
C161
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
Internal
RAM
10000
0.5K
0FE00
3FFFF
Data Pages
15
C164
C165
14
3
30000
Reserved
13
C166
12
C167
11
0F200
512 Bytes
Ext. SFR’s
SSP Module
Reserved
Code Segments
1K
0FA00
C163
up to 16 MBytes
2
0.5K
0F000
10
9
20000
8
7
0E800
1
6
5
External
Memory
10000
Internal
ROM/
FLASH
4
3
Bit Addressable Space
X-Bus Peripheral
Memory
Internal
ROM /
Flash E²PROM
(mappable to Seg. 1)
08000
128K
0
2
1
00000
0
Microcontrollers
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Internal and external
Memory Map
C161
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
Internal
RAM
Internal
RAM
Reserved
512 Bytes
Ext. SFR’s
Full -CAN
Reserved
10000
0.5K
0FE00
Code Segments
3FFFF
1K
0FA00
1K
3
0F600
C164
C165
13
C166
12
C167
11
2
0.5K
0F000
Data Pages
15
14
30000
0F200
C163
up to 4 MBytes
10
9
20000
8
7
0E800
1
6
5
External
Memory
10000
Internal
ROM/
FLASH
4
3
Bit Addressable Space
X-Bus Peripheral
Memory
Internal
ROM /
Flash E²PROM
(mappable to Seg. 1)
08000
64K
0
2
1
00000
0
Microcontrollers
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Internal and external
Memory Map
C161
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
Internal
RAM
Internal
RAM
Reserved
512 Bytes
Ext. SFR’s
10000
0.5K
0FE00
Code Segments
3FFFF
1K
0FA00
1K
3
0F600
C164
C165
13
C166
12
C167
11
2
0.5K
0F000
Data Pages
15
14
30000
0F200
C163
up to 16 MBytes
10
9
20000
8
7
1
6
5
External
Memory
10000
4
3
0
Bit Addressable Space
1
00000
Memory
2
0
Microcontrollers
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Internal and external
Memory Map
C161
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
Internal
RAM
10000
0.5K
0FE00
Code Segments
3FFFF
1K
0FA00
C163
256 KBytes
Data Pages
15
C164
C165
14
3
30000
13
C166
12
C167
11
2
10
9
External
Memory
20000
8
7
1
6
5
10000
Internal
ROM/
FLASH
4
3
Bit Addressable Space
Memory
Internal
ROM /
Flash E²PROM
(mappable to Seg. 1)
08000
32K
0
2
1
00000
0
Microcontrollers
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Internal and external
Memory Map - C167CR
C161
Segment 0 includes Internal Memory
7
0
512 Bytes
SFR’s
Internal
RAM
Internal
RAM
10000
0.5K
0FE00
Code Segments
3FFFF
1K
0FA00
1K
3
30000
512 Bytes
Ext. SFR’s
Full - CAN
Reserved
0F200
C164
C165
13
C166
12
C167
11
2
10
9
0.5K
0F000
Data Pages
15
14
0F600
Reserved
C163
up to 16 MBytes
20000
8
7
0E800
1
6
5
External
Memory
10000
Internal
ROM/
FLASH
4
3
Bit Addressable Space
X-Bus Peripheral
Memory
Internal ROM /
Flash E²PROM
(mappable to Seg. 1)
08000
128K
00000
0
2
1
0
Microcontrollers
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Code and Data Addressing via Segmentation
and Paging on 8 Mbyte address range
C161
Data addressing with Data Page Pointer (DPP)
Code addressing with Code Segment Pointer
C163
C164
15 14 13
16-bit Adress
0
15
5
Code Seg. Pointer
0
15
16-bit Instr. Pointer
0
C165
C166
Selection of one
Data Page Pointer
DPP3
DPP2
DPP1
DPP0
8-bit
C167
6-bit Segment
Number
16-bit
14-bit
Page
Number
Physical 22-bit Code address
Physical 22-bit Data address
Memory
Microcontrollers
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Code and Data Addressing via Segmentation
and Paging on 16 Mbyte address range
C161
Data addressing with Data Page Pointer (DPP)
Code addressing with Code Segment Pointer
C163
C164
15 14 13
16-bit Adress
0
15
7
Code Seg. Pointer
0
15
16-bit Instr. Pointer
0
C165
C166
Selection of one
Data Page Pointer
DPP3
DPP2
DPP1
DPP0
10-bit
C167
8-bit Segment
Number
16-bit
14-bit
Page
Number
Physical 24-bit Code address
Physical 24-bit Data address
Memory
Microcontrollers
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Code and Data Addressing via Segmentation
and Paging on 256 KByte address range
C161
Data addressing with Data Page Pointer (DPP)
15 14 13
16-bit Adress
0
15
Code addressing with Code Segment Pointer
Code Seg. Pointer 1
0
15
16-bit Instr. Pointer
0
C163
C164
C165
C166
Selection of one
Data Page Pointer
DPP3
DPP2
DPP1
DPP0
4-bit
2-bit Segment
Number
C167
16-bit
14-bit
Page
Number
Physical 18-bit Code address
Physical 18-bit Data address
Memory
Microcontrollers
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Data Addressing via
Data Page Pointer (DPPx)
C161
MByte
C163
KByte
C164
C165
8
4
2
23
22
21
1M 512
20
19
256 128
18
17
64
32
16
8
4
2
1K
512
16
15
14
13
12
11
10
9
256 128
8
7
64
32
16
8
4
2
0
6
5
4
3
2
1
0
C166
C167
16K
DPP0
DPP1
DPP2
DPP3
=
=
=
=
0
0
1
1
0
1
0
1
DPP
Memory
Microcontrollers
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Data Addressing via Extended Mode
C161
 Overrides standard DPP addressing scheme to ease large
(up to 32-bit) address calculation
Segment or Page override by an immediate value
Segment and Page override by a Register contents
C163
-
C164
C165
C166
C167
Examples: Override Segment Number
Override Page Number
EXTS RN,#data2 ;data2:No. of instructions
MOV [RM],Ri
;to be used for Ext.Addr.Mode
15
0 15
RN
15
0 15
RM
7
A23
0
EXTP RN, #data2
MOV [RM], Ri
0
15
A16 A15
RN
RM
0
9
0
A0
A23
A14
Physical address, where the contents of Ri is moved to
Memory
0
13
0
A13
A0
Physical address, where the contents of Ri is moved to
Microcontrollers
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Comparison of Bus Speed at Different Bus
Configurations at 16 MHz CPU Clock
C161
C163
single Chip
Mode
16 Bit Data
16 Bit Data
8 Bit Data
8 Bit Data
16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address
NON MUX
MUX
NON MUX
MUX
C164
C165
used Ports
none
Port 0, 1, 4
Port 1, 4
Port 0, 1, 4
Port 1, 4
Address Latch
none
none
16 Bit
none
8 Bit
Bus Cycle Time
0 / 1 / 2 Wait States
125ns /../..
125/188/250 ns
188/250/313 ns
125/188/250 ns
188/250/313 ns
Instr. Fetch Time
1 Word
125ns /../..
125/188/250 ns
188/250/313 ns 250/375/500 ns
375/500/625 ns
Instr. Fetch Time
2 Word
125ns /../..
250/375/500 ns
375/500/625 ns
500/750ns/1µs
750/1µs/1.25µ
n.a.
88/150/213 ns
88/150/213 ns
88/150/213 ns
88/150/213 ns
1
1.5
2.5
3.0
4.5
EPROM Access
Time t17
rel. speed for
typ. code
C166
C167
(50% 2 word instructions)
 External bus speed optimization by prefetching into the instruction queue !
Memory
Microcontrollers
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Comparison of Bus Speed at Different Bus
Configurations at 20 MHz CPU Clock
C161
C163
single Chip
Mode
16 Bit Data
16 Bit Data
8 Bit Data
8 Bit Data
16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address
NON MUX
MUX
NON MUX
MUX
C164
C165
used Ports
none
Port 0, 1, 4
Port 1, 4
Port 0, 1, 4
Port 1, 4
Address Latch
none
none
16 Bit
none
8 Bit
Bus Cycle Time
0 / 1 / 2 Wait States
100ns /../..
100/150/200 ns
150/200/250 ns 100/150/200 ns
150/200/250 ns
100/50/200 ns
150/200/250 ns 200/300/400 ns
300/400/500 ns
100ns /../..
200/300/400 ns
300/400/500 ns 400/600/800 ns
600/800ns/1µs
n.a.
70/120/170 ns
70/120/170 ns
70/120/170 ns
70/120/170 ns
1
1.5
2.5
3.0
4.5
Instr. Fetch Time
1 Word
Instr. Fetch Time
2 Word
EPROM Access
Time t17
rel. speed for
typ. code
100ns /../..
C166
C167
(50% 2 word instructions)
 External bus speed optimization by prefetching into the instruction queue !
Memory
Microcontrollers
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Comparison of Bus Speed at Different Bus
Configurations at 25 MHz CPU Clock
C161
C163
single Chip
Mode
16 Bit Data
16 Bit Data
8 Bit Data
8 Bit Data
16/24 bit Address 16/24 bit Address 16/24 bit Address 16/24 bit Address
NON MUX
MUX
NON MUX
MUX
C164
C165
used Ports
none
Port 0, 1, 4
Port 1, 4
Port 0, 1, 4
Port 1, 4
Address Latch
none
none
16 Bit
none
8 Bit
Bus Cycle Time
0 / 1 / 2 Wait States
80ns /../..
80/120/160 ns
120/160/200 ns
80/120/160 ns
120/160/200 ns
Instr. Fetch Time
1 Word
80ns /../..
80/120/160 ns
120/160/200 ns 160/240/320 ns
240/320/400 ns
Instr. Fetch Time
2 Word
80ns /../..
160/240/320 ns
240/320/400 ns 320/480/640 ns
480/640/800ns
EPROM Access
Time t17
rel. speed for
typ. code
n.a.
55/105/155 ns
55/105/155 ns
55/105/155 ns
55/105/155 ns
1
1.5
2.5
3.0
4.5
C166
C167
(50% 2 word instructions)
 External bus speed optimization by prefetching into the instruction queue !
Memory
Microcontrollers
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Relative Performance vs. CPU
Frequency
Performance of SABC163 vs Frequency at 0/1/2 Waitstates
Based on 50% mix of 1-word and 2-word fetches
C161
14.00
C163
0/1/2 Waitstates based on 0% mix of 1-word
and 2-word Fetches with Data in the internal DP-RAM
12.00
C164
C165
10.00
Relative Performance
C166
C167
8.00
6.00
4.00
Single Chip Pe rform ance
0 WS Pe rform ance
1 WS Pe rform ance
2 WS Pe rform ance
2.00
0.00
10
11
12
13
14
15
16
17
CPU Frequency
Memory
18
(MHz)
19
20
21
22
23
24
25
graph by Patrick Pettibon
Microcontrollers
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Flash technology from Siemens!
C161
C163
SAB C163-16F25F
C164
C165
C166
C167
128KByte FLASH
CPU
1k RAM
C163 Flash Module!
Microcontrollers
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C163 Flash
Comparsion with C167CR Flash
C163 Flash Module
New Technology
128 KByte capacity
Any use for instruction code or data
C161
C167 Flash Module
C163
128 KByte capacity
Any use for instruction code or data
C164
C165
C166
Programming and erase
+ Progr. voltage 5V on standard VCC pins
+ Integrated state machine
+ Directly controlled by commands
Programming control
+ Fast: 125 msec per 8 KB block
Erase control
+ Simple erase command per sector
+ Fast: 10 msec per sector
C163 Flash Module
Programming and erase
- 12 V on separate VPP pin
- SW controlled
- Complex SW to avoid over/underprogramming or erase
Programming control
+ Fast: 200 msec per 8 KB block
Erase control
- Preprogramming (all zeros) necessary
- Slow: 1 sec per sector
Microcontrollers
C167
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Embedded Flash Module
Basic Overview
C161
C163
C163 Flash
C164
C165
C166
C167
CPU
C163 Core
Bus
128 KByte
Flash Module
External
Host
Bus
2 Interfaces for Flash Programming
C163 Flash Module
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Basic Structure
Programming Interface
C161
C163 Flash Module
C164
C165
C166
32K Sector
32K Sector
32K Sector
C167
32K Sector
32 Bit Data Bus
16 Bit Address Bus
Voltage Pumps
64 x 8 Assembly Buffer
C163
Core
External Host
Interface
Programming
Interfaces
External
Host
Command
& Array
State
Machine
CPU Interface
C163
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Programming and Erase Control
on CPU Interface...
C161
 Commands for Flash Control written to Flash by CPU:
Reset to Read
Resets the internal state machine;
returns to read mode
Enter Burst Mode Enter programming mode and write first
word of burst into assembly burst
register
Load Burst Data Write subsequent word into assembly
burst register
Store Burst
Write last word into burst register and
store whole burst into Flash array
Erase Sector
Erase addressed 32KByte sector
Read Flash Status Read status register
Clear Status
Clear error flags in status register
 ...
-
C163
C164
C165
C166
-
C163 Flash Module
Microcontrollers
C167
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...Programming and Erase Control
on CPU Interface
C161
 Commands are transferred to Flash with command
sequences for protection
 Cycles of command sequences are based on JEDEC
standard (USA)
 Command sequences can only be written by instructions
not fetched from Flash itself
C163 Flash Module
Microcontrollers
C163
C164
C165
C166
C167
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Operation Control by Command
Sequences
Flash Command Sequences
Command
Reset to Read
C161
Sequence of bus cycles to Flash
1. Cycle
2.Cycle
3.Cycle
4.Cycle
5.Cycle
Addr Data
Addr Data
Addr Data
Addr Data
Addr Data
AAAA xxF0
Enter Burst Load AAAA xx50
Load Burst Data A0F2
RA
C163
6.Cycle
C164
Addr Data
C165
RD
C166
WA 1.WD
C167
WD
Store Burst
AAAA xxAA
5554 xx55
AAAA xxA0 WA 32WD
Erase Sector
AAAA xxAA
5554 xx55
AAAA xx80
Read Status
AAAA xxFA
SA, R status
Clear Status
AAAA xxF5
5554 xxAA
AAAA xx55
SA xx30
R = Register Address RA = Read Data Address RD = Read Data WA = Write Address
WD = Write Data SA = Sector Address (hex)
All commands cycles are write cycles (exception status read cycle) !
C163 Flash Module
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Programming a Burst of 32 Words
C161
Programming is performed by a load / store procedure with the assembly buffer:
C163
C164
Programming Commands
- Enter Burst Load / Load 1. Word
Assembly Buffer
Flash Array
C165
1. Word
C166
- Load 2. Word
C167
Flash Memory
- Load 3. Word
and so on
64 Byte Block
- Load 31. Word
- Load 32. Word and Store Burst
C163 Flash Module
Last Word
Store Burst
into Flash
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Erasing a Sector of Flash Memory
C161
C163
Erasing a sector is performed in a single step:
C164
Programming Command
Flash Array
C165
C166
Only one command (sequence):
Erase Sector
C167
Flash Memory
Sector addressing:
Sector
Number
Sector Size
Sector Address
A16 A15 A14...A01
SA 1
32 KB
0
0
-0-
SA 2
32 KB
0
1
-0-
SA 3
32 KB
1
0
-0-
SA 4
32 KB
1
1
-0-
32 KByte Sector
Sector addresses are physical addresses !
C163 Flash Module
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Flash Status Information
C161
The Flash Status Register FSR provides information of the
actual operating state and of error conditions to the user.
 Status bits in FSR:
- BUSY
C163
C164
Flash Busy
Busy with programming or erase;
not in read mode
Programming State Flash busy with store burst
Erase State
Flash busy with erase state
Sector Erased
Addressed sector correctly erased
Burst Mode
Assembly buffer being filled
- PROG
- ERASE
- SE
- BRST
 Error bits in FSR:
- OPER Operation Error
- VPER Voltage Error
- SQER Sequence Error
- BUER Burst Error
C163 Flash Module
C165
C166
C167
Error during programming or erase
operation
Voltage problem during Flash
operation
Improper command or address in
command sequence
Overflow or underload condition in
burst mode
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SW control of a flash operation
C161
 A Flash operation shall be controlled by following SW
procedure:
C163
1 Write command sequence to Flash
2 Check SQER error bit for fault condition in command
sequence
3 Check BUSY status bit if command is (still) in operation
4 When finished: check OPER and VPER error bits; in case
of a store burst operation also the BUER error bit
5 In case of fault condition: clear error flag with a clear status
command; start corrective action
 All addresses to Flash have to be mapped to Flash space
Command, sector and data addresseshave to be located
within active Flash memory space
The active Flash space is that address range which is
covered by the Flash
C164
C165
C166
C167
-
C163 Flash Module
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Features
Programming Modes
C161
 64 K byte embedded OTP memory
 Two different programming possibilities
Parallel programming mode
Controlled by external standard programming system
Serial programming mode
Controlled by int. CPU with boot routine out of boot ROM
Using e.g. a laptop as programming device
 External 11,5 V programming voltage
 Fast programming cycles: 1 word (16 bit) in 100 µs
 Optional read protection
 Interface optimized for CPU performance
with 32-bit instruction fetch in one cycle
 Any use for instruction code or constant data
C163
-
OTP module
Microcontrollers
C164
C165
C166
C167
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Comparsion of Programming Modes
Serial Programming
CPU Host Mode
C161
Parallel Programming
External Host Mode
C163
C164
Host programming device
• Internal CPU
Host programming device
• External programmer or tester
Programming Interface
• Standard serial interface (USART)
• Automatical adjustment on baud rate
• Optimized for com-link of PC or laptop
Programming Interface
• External 16-bit system bus (XBUS)
• Fully asynchron
• OTP is slave; CPU disabled
Programming control
• User SW fetched by boot ROM routine
Programming control
• External control with bus cycles
VPP control
• By SW: control signal on port pin
VPP control
• Controlled by programming device
OTP
Microcontrollers
C165
C166
C167
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Basic Structure
Programming Interface
Programming
Control
OTP module
C166
C167
16 Bit
Address Bus
64K OTP Array
CPU Interface
C164
C165
32 Bit
Data Bus
C164
Core
C163
Array Control
External Host
or CPU Host
Programming
Interface
C161
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Overview at 16MHz...
C161
 Interrupt Controller
Extremely short interrupt response time of minimal 312ns
typical: 500ns
Interrupt execution in small time segments
Ensures highest real-time performance
Comprehensive prioritization scheme
- Easy scheduling of complex real-time systems by
using up to 64 priority levels (4 groups within 16
levels)
Non-maskable interrupt input (NMI)
Hardware-Traps on runtime errors and Software-Traps
 ...
-
C163
C164
C165
C166
C167
-
Interrupt System
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...Overview at 16MHz
C161
 CPU independent interrupt-service via
Peripheral Events Controller (PEC)
Off-loads the CPU from simple but frequent interruptservices
Interrupt-driven “DMA-like” data transfer to any location in
segment 0, without task switch of the CPU
Makes peripheral data transfers Independent of running
CPU routine
Response-time is minimal 187ns, typical 375ns
with a CPU load of 125ns
C163
-
Interrupt System
Microcontrollers
C164
C165
C166
C167
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Overview at 20MHz...
C161
 Interrupt Controller
Extremely short interrupt response time of minimal 250ns
typical: 400ns
Interrupt execution in small time segments
Ensures highest real-time performance
Comprehensive prioritization scheme
- Easy scheduling of complex real-time systems by
using up to 64 priority levels (4 groups within 16
levels)
Non-maskable interrupt input (NMI)
Hardware-Traps on runtime errors and Software-Traps
 ...
-
C163
C164
C165
C166
C167
-
Interrupt System
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...Overview at 20MHz
C161
 CPU independent interrupt-service via
Peripheral Events Controller (PEC)
Off-loads the CPU from simple but frequent interruptservices
Interrupt-driven “DMA-like” data transfer to any location in
segment 0, without task switch of the CPU
Makes peripheral data transfers Independent of running
CPU routine
Response-time is minimal 150ns, typical 300ns
with a CPU load of 100ns
C163
-
Interrupt System
Microcontrollers
C164
C165
C166
C167
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Overview at 25MHz...
C161
 Interrupt Controller
Extremely short interrupt response time of minimal 200ns
typical: 320ns
Interrupt execution in small time segments
Ensures highest real-time performance
Comprehensive prioritization scheme
- Easy scheduling of complex real-time systems by
using up to 64 priority levels (4 groups within 16
levels)
Non-maskable interrupt input (NMI)
Hardware-Traps on runtime errors and Software-Traps
 ...
-
C163
C164
C165
C166
C167
-
Interrupt System
Microcontrollers
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Overview at 25MHz
C161
 CPU independent interrupt-service via
Peripheral Events Controller (PEC)
Off-loads the CPU from simple but frequent interruptservices
Interrupt-driven “DMA-like” data transfer to any location in
segment 0, without task switch of the CPU
Makes peripheral data transfers Independent of running
CPU routine
Response-time is minimal 120ns, typical 240ns
with a CPU load of 80ns
C163
-
Interrupt System
Microcontrollers
C164
C165
C166
C167
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Priority System, PEC
C161
group
PEC 6
group 2
Level 15
PEC 5
group 1
PEC 3
Level
group 3
group 2
Level 13
group 3
group 2
Level 1-12
group 3
Level 0
group 2
group 1
Interrupt System
3 2 1 0
PEC 4
group 0
PEC 2
PEC 1
PEC 0
group 2
group 1
14
group 0
group 3
group 1
group 1
group 0
group 0
group 0
C163
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C164
64
C165
C166
C167
Level
PEC 7
group 3
Microcontrollers
1
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Interrupt Processing
C161
Interrupt Control Register of the appropriate peripheral
INTR Service:
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
INTR Flag
16 Priority Levels
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C163
C164
C165
C166
C167
PEC
Service
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
C161V
C161K
C161O
C161RI
Peripheral Interrupts
15
21
21
21
Ext. Interrupts + NMI
5
5
11
11
sampled every 63 ns
4
4
7
8
Interrupt System
Microcontrollers
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Interrupt Processing
C161
C163
INTR Service:
Interrupt Control Register of the appropriate peripheral
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
INTR Flag
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C164
C165
C166
C167
PEC
Service
16 Priority Levels
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
12 Peripheral Interrupts
12 ext. Interrupts(+ NMI) including 8 which are sampled every 40 ns
Interrupt System
Microcontrollers
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Interrupt Processing
C161
C163
INTR Service:
Interrupt Control Register of the appropriate peripheral
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
INTR Flag
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C164
C165
C166
C167
PEC
Service
16 Priority Levels
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
32 Peripheral Interrupts
13 ext. Interrupts(+ NMI) including 4 which are sampled every 50 ns
Interrupt System
Microcontrollers
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Interrupt Processing
C161
C163
Interrupt Control Register of the appropriate peripheral
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
INTR Flag
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
INTR Service:
C164
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C165
C166
C167
PEC
Service
16 Priority Levels
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
28 Peripheral Interrupts
12 ext. Interrupts(+ NMI) including 8 which are sampled every 40 ns
Interrupt System
Microcontrollers
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Interrupt Processing
C161
C163
Interrupt Control Register of the appropriate peripheral
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
INTR Flag
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
INTR Service:
C164
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C165
C166
C167
PEC
Service
16 Priority Levels
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
32 Peripheral Interrupts on the 80C166
19 ext. Interrupts(+ NMI)
Interrupt System
Microcontrollers
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Interrupt Processing
C161
C163
Interrupt Control Register of the appropriate peripheral
INTR Flag is Set
Peripheral Interrupt
Priority Check
Peripheral Interrupt
Comparison of
Interrupt Priority
with CPU
Runtime Priority
if
higher
Priority
Group Check
Clear
INTR Flag
Peripheral Interrupt
External Interrupt*
Peripheral Interrupt
External Interrupt*
INTR Service:
C164
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
peripheral
vector or
Trap no.
C165
C166
C167
PEC
Service
16 Priority Levels
4 Groups
* External Interrupts are possible, e.g. instead of the Capture Input
55 Peripheral Interrupts
36 ext. Interrupts(+ NMI) including 8 which are sampled every 50 ns
Interrupt System
Microcontrollers
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Peripheral Event Controller (PEC)
C161
Interrupt has passed priority and group check
C163
C164
Interrupt priority 14 or 15
and Data Counter > 0
Interrupt priority < 14
C165
C166
Interrupt service
PEC service
Memory Segment 0
C167
0FFFF
PEC
Contr. Reg.
INTR Service:
Save PSW,
CSP, IP
Set new priority
in PSW.
Set CSP, IP
according to
Peripheral
vector or
Trap No.
8 PEC
Channel
priority & group
check
Interrupt System
Data Counter
SRC Pointer
DEST Pointer
Byte or
Word
Transfer
IR request if Data Counter = 0
00000
Microcontrollers
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Peripherals Set of the
C161x
C161
 2 General Purpose Timer units (GPT1 & GPT2)
5 Timers (250/500ns) with multiple Input/Output, Reload
and Capture functions and complex concatenation
capabilities
 Capture/Compare unit (CAPCOM)
2 timers (500ns) each with Reload register and 16
independent
16-bit Capture/Compare channels programmable to 6
modes of operation
 2 independent identical USARTs
max 500KBaud asynchronous
max 2.0 Mbit/sec synchronous data transfer
 I/O Ports
6 Ports provide 76 I/O lines (V/K/O only)
 Watchdog: 16-bit Reload-timer causes reset on overflow
-
C163
C164
C165
C166
-
C167
-
Peripherals
Microcontrollers
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Peripherals Set of the
C161RI
C161
 I/O Ports
7 Ports provide 77 I/O Lines
 Realtime clock
 Fast and accurate A/D Converter
8-bit resolution, 4 input channels, 7.5µs conversion time,
continuous modes
 I2C Bus
7 and 10-bit addressing, 400KHz
2 channels (multiplexed)
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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Varieties of the C161
Feature
C161V
C161K
C161O
Internal RAM Size (IRAM)
1 KByte
1 KByte
2 KByte
C161
C161RI
C163
Chip Select Signals
2
4
5
(DE)MUX
(DE)MUX
(DE)MUX
yes
yes
yes
4
4
7
8
yes
yes
yes
yes
yes
yes
yes
yes
yes
MUX
General Purpose Timer 1 (GPT1)
Input / Output Functionality GPT1
General Purpose Timer 2 (GPT2)
with Capture Input (CAPIN) Funct.
Real Time Clock (RTC)
yes
I²C - BUS
yes
8-Bit ADC
yes
Peripherals
C165
C166
C167
Power Saving Modes
Fast external Interrupts
C164
2 KByte
Extension RAM Size (XRAM)
Bus Modes
1 KByte
Microcontrollers
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Peripherals Set of the
C163
C161
 2 General Purpose Timer units (GPT1 & GPT2)
5 Timers 160/320ns with enhanced Input/Output,
Reload and Capture functions and
complex concatenation capabilities
 Independent USART
max. 780 KBaud asynchronous
and max 3.1 Mbit/sec synchronous data transfer
 Fast Synchronous Serial Port (SSP)
max. 12.5 Mbit/sec to connect to slave devices like
EEPROMs with sending up to 3 Bytes (24bits)
 I/O Ports
7 Ports provide 77 I/O Lines
 Watchdog: 16-Bit Reload -timer causes reset on overflow
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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Peripherals Set of the
C164...
C161
 General Purpose Timer unit (GPT1)
3 Timers (200/400ns) with enhanced Input/Output, Reload
and Capture functions and complex concatenation
capabilities
 Capture/Compare unit (CAPCOM2)
2 Timers (400ns) with Reload register and 8 independent
16-bit Capture/Compare channels programmable to 6
modes of operation
 Capture/Compare unit (CAPCOM6)
for flexible PWM Signal Generation
2 Timers (100ns) with Period register, 1 Offset register, 3/6
16-bit Capture/Compare channels and one 10-bit compare
channel
Optimized for Drive Control Applications
 ...
-
C163
C164
C165
-
C166
C167
-
-
Peripherals
Microcontrollers
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...Peripherals Set of the
C164
C161
 Independent USART
max 625 KBaud asynchronous and max 2.5 Mbit/sec
synchronous data transfer
 Fast Serial Synchronous Communication interface (SSC)
max 5 Mbit/sec full duplex transfer rate, SPI compatible
 Fast and accurate A/D Converter
10-Bit resolution, 8 input channels, 9.7µs conversion time,
enhanced continuous and scan modes with channelinjection capability, automatic calibration.
 I/O Ports
6 Ports provide 59 I/O lines
 Watchdog: 16-Bit Reload-timer causes reset on overflow
 Reset Detection
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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16x_all.ppt
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Peripherals Set of the
C165
C161
 2 General Purpose Timer units (GPT1 & GPT2)
5 Timers (160/320)ns with enhanced
Input/Output, Reload and Capture functions and
complex concatenation capabilities
 Independent USART
max. 780 KBaud asynchronous
and max 3.1 Mbit/sec synchronous data transfer
 Fast Serial Synchronous Communication interface (SSC)
max. 6.25 Mbit/sec full duplex transfer rate, SPI compatible
 I/O Ports
7 Ports provide 77 I/O Lines
 Watchdog: 16-Bit Reload-timer causes reset on overflow
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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Peripherals Set of the
SAB 80C166...
C161
 2 General Purpose Timer units (GPT1 & GPT2)
5 Timers (200/400ns) with multiple Input/Output, Reload
and Capture functions and complex concatenation
capabilities
 Capture/Compare unit (CAPCOM)
2 timers (400ns) each with Reload register and 16
independent
16-bit Capture/Compare channels programmable to 6
modes of operation
 2 independent identical USARTs
max 625KBaud asynchronous
max 2.5 Mbit/sec synchronous data transfer
 ...
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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16x_all.ppt
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...Peripherals Set of the
SAB 80C166
C161
 Fast and accurate A/D Converter
10-bit resolution, 10 input channels, 9.7µs conversion time,
continuous and scan modes
 I/O Ports
6 Ports provide 76 I/O lines
 Watchdog: 16-bit Reload-timer causes reset on overflow
-
C163
C164
C165
-
Peripherals
Microcontrollers
C166
C167
HL MC AT, lehmann
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Peripherals Set of the
C167...
C161
 2 General Purpose Timer units (GPT1 & GPT2)
5 Timers (200/400ns) with enhanced Input/Output, Reload
and Capture functions and complex concatenation
capabilities
 2 Capture/Compare units (CAPCOM1 & 2)
4 Timers (400ns) with Reload register and 32 independent
16-bit Capture/Compare channels programmable to 6
modes of operation
 4 high resolution PWM channels
each with independent time-base of up to 50ns resolution
and programmable operation modes (edge-aligned, centeraligned, burst and single-shot mode)
 ...
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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16x_all.ppt
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...Peripherals Set of the
C167
C161
 Independent USART
max 625 KBaud asynchronous and max 2.5 Mbit/sec
synchronous data transfer
 Fast Serial Synchronous Communication interface (SSC)
max 5 Mbit/sec full duplex transfer rate, SPI compatible
 Fast and accurate A/D Converter
10-Bit resolution, 16 input channels, 9.7µs conversion time,
enhanced continuous and scan modes with
channel-injection capability.
 I/O Ports
8 Ports provide 111 I/O lines
 Watchdog: 16-Bit Reload-timer causes reset on overflow
-
C163
C164
C165
-
C166
C167
-
Peripherals
Microcontrollers
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General Purpose Timer 1 (GPT1)
at 16 MHz
C161
 Three 16-bit up/down timers:
2 auxiliary timers(T2,T4) and 1 core timer(T3)
 Input mode
Timer mode: Internal clock input with prescaler up to
2.0 MHz / 500ns;
Clock can be gated with external signal
Counter Mode: external clock up to 1.00 MHz
Cascading of core timer and any aux. timer (33-Bit timer)
 Count direction (C166 T3 only) can be changed externally
 ...
C163
C164
-
C165
C166
-
GPT 1
Microcontrollers
C167
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General Purpose Timer 1
at 16 MHz
C161
 Output mode
Interrupt possibility and toggle function at the core timer T3
Interrupt possibility at auxiliary timers T2 and T4
 Reload: Core timer can be reloaded with the contents of any
aux. timer
 Capture: Contents of the core timer can be latched into any
aux. timer
-
GPT 1
Microcontrollers
C163
C164
C165
C166
C167
HL MC AT, lehmann
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GPT 1 Function Diagram
at 16 MHz
C161
33-bit cascaded path
C163
Gate
Clk max
2.0 MHz
Run
Enable
Input
Mode
Control
max.
1.0 MHz
C164
Reload
C165
INTR
Flag
Aux Timer T2 / T4
C166
up / down
Gate
Clk max
2.0 MHz
Run
Enable
Input
Mode
Control
max.
1.0 MHz
C167
Outp.
enables
Toggle
Latch
Core Timer T3
INTR
Flag
up / down
Gate
Clk max
2.0 MHz
max.
1.0 MHz
Run
Enable
Input
Mode
Control
Capture
Aux Timer T2 / T4
INTR
Flag
up / down
GPT 1
Microcontrollers
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General Purpose Timer 1(GPT 1)
at 20 MHz
C161
 Three 16-bit up/down timers:
2 auxiliary timers(T2,T4) and 1 core timer(T3)
 Input mode
Timer mode: Internal clock input with prescaler up to
2.5 MHz / 400 ns; Clock can be gated with external signal
Counter Mode: external clock up to 1.25 MHz
Cascading of core timer and any aux. timer (33-Bit timer)
 Count direction (only T3 ) can be changed externally
 Output mode
Interrupt possibility and toggle function at the core timer T3
Interrupt possibility at auxiliary timers T2 and T4
 Reload: Core timer can be reloaded with the contents of
any aux. timer
 Capture: Contents of the core timer can be latched into
any aux. timer
C163
C164
-
C165
C166
C167
-
GPT 1
Microcontrollers
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GPT 1 Function Diagram
at 20 MHz
C161
33-bit cascaded path
C163
Run
Enable
Clk max
2.5 MHz
Input
Mode
Control
C164
Reload
C165
INTR
Flag
Aux Timer T2 / T4
C166
up / down
Gate
Clk max
2.5 MHz
max.
1.25 MHz
Run
Enable
Input
Mode
Control
Toggle
Latch
Core Timer T3
up / down
Clk max
2.5 MHz
Run
Enable
Input
Mode
Control
C167
Outp.
enables
INTR
Flag
to CAPCOM2
Timer T7, T8
Capture
Aux Timer T2 / T4
INTR
Flag
up / down
GPT 1
Microcontrollers
HL MC AT, lehmann
16x_all.ppt
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GPT 1 Function Diagram
at 20 MHz
C161
33-bit cascaded path
C163
Gate
Clk max
2.5 MHz
Run
Enable
Input
Mode
Control
max.
1.25 MHz
C164
Reload
C165
INTR
Flag
Aux Timer T2 / T4
C166
up / down
Gate
Clk max
2.5 MHz
Run
Enable
Input
Mode
Control
max.
1.25 MHz
C167
Outp.
enables
Toggle
Latch
Core Timer T3
INTR
Flag
up / down
Gate
Clk max
2.5 MHz
max.
1.25 MHz
Run
Enable
Input
Mode
Control
Capture
Aux Timer T2 / T4
INTR
Flag
up / down
GPT 1
Microcontrollers
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GPT 1 Function Diagram
at 20 MHz
C161
33-bit cascaded path
C163
Gate
Clk max
2.5 MHz
Run
Enable
Input
Mode
Control
max.
1.25 MHz
C164
Reload
C165
INTR
Flag
Aux Timer T2 / T4
C166
up / down
Gate
Clk max
2.5 MHz
Run
Enable
Input
Mode
Control
max.
1.25 MHz
C167
Outp.
enables
Toggle
Latch
Core Timer T3
INTR
Flag
up / down
Gate
Clk max
2.5 MHz
max.
1.25 MHz
Run
Enable
Input
Mode
Control
Capture
Aux Timer T2 / T4
INTR
Flag
up / down
GPT 1
Microcontrollers
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General Purpose Timer 1(GPT 1)
at 25 MHz
C161
 Three 16-bit up/down timers:
2 auxiliary timers(T2,T4) and 1 core timer(T3)
 Input mode
Timer mode: Internal clock input with prescaler up to
3.1 MHz / 320 ns; Clock can be gated with external signal
Counter Mode: external clock up to ~1.6 MHz
Cascading of core timer and any aux. timer (33-Bit timer)
 Count direction can be changed externally
 Output mode
Interrupt possibility and toggle function at the core timer T3
Interrupt possibility at auxiliary timers T2 and T4
 Reload: Core timer can be reloaded with the contents of
any aux. timer
 Capture: Contents of the core timer can be latched into
any aux. timer
C163
C164
-
C165
C166
C167
-
GPT 1
Microcontrollers
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16x_all.ppt
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GPT 1 Function Diagram
at 25 MHz
C161
33-bit cascaded path
C163
Gate
Clk max
3.1 MHz
Run
Enable
Input
Mode
Control
max.
1.6 MHz
C164
Reload
C165
INTR
Flag
Aux Timer T2 / T4
C166
up / down
Gate
Clk max
3.1 MHz
Run
Enable
Input
Mode
Control
max.
1.6 MHz
C167
Outp.
enables
Toggle
Latch
Core Timer T3
INTR
Flag
up / down
Gate
Clk max
3.1 MHz
max.
1.6 MHz
Run
Enable
Input
Mode
Control
Capture
Aux Timer T2 / T4
INTR
Flag
up / down
GPT 1
Microcontrollers
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16x_all.ppt
13.03.2016, 23:14
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General Purpose Timer 2 (GPT 2)
at 16 MHz
C161
 Two 16-Bit up/down timers (T5, T6)
 Input mode
Timer mode: Internal clock input with prescaler
up to 4MHz (250ns)
Counter mode: External clock up to 2.0 MHz
T5 can also be clocked with the toggle bit of T6
 Output mode
Interrupt possibility and toggle function of a
port line (via a toggle bit)
Output of T6 can be used to clock CAPCOM timers
 Count direction of all timers can be dynamically changed
(C167)
 Cascading of timer T6 with timer T5
 One 16-Bit Capture(for T5) / Reload(for T6) register
Reload register for T6, Capture register for T5
C163
-
C164
C165
C166
C167
-
GPT 2
Microcontrollers
HL MC AT, lehmann
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GPT 2 Function Diagram
at 16 MHz
C161
Clk max
4.0 MHz
max.
2 MHz
C163
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T5
C164
C165
up / down
Enable
Clear
Enable
C166
INTR
Flag
C167
Capture / Reload
Reload
Enable
Clk max
4.0 MHz
max.
2 MHz
Toggle
Latch
Run
Enable
Input
Mode
Control
Outp.
enables
Aux Timer T2 / T4
INTR
Flag
up / down
33-bit cascaded path
GPT 2
Microcontrollers
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16x_all.ppt
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GPT 2 Function Diagram
at 16 MHz - C161RI only
C161
Clk max
4.0 MHz
C163
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T5
C164
C165
up / down
Enable
Clear
Enable
C166
INTR
Flag
C167
Capture / Reload
Reload
Enable
Clk max
4.0 MHz
Toggle
Latch
Run
Enable
Input
Mode
Control
Aux Timer T2 / T4
INTR
Flag
up / down
33-bit cascaded path
GPT 2
Microcontrollers
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General Purpose Timer 2 (GPT 2)
at 20 MHz
C161
 Two 16-Bit up/down timers (T5, T6)
 Input mode
Timer mode: Internal clock input with prescaler up to 5MHz
(200ns)
Counter mode: External clock up to 2.5 MHz
T5 can also be clocked with the toggle bit of T6
 Output mode
Interrupt possibility and toggle function of a port line (via a
toggle bit)
Output of T6 can be used to clock CAPCOM timers
 Count direction of all timers can be dynamically changed
(C167)
 Cascading of timer T6 with timer T5
 One 16-Bit Capture(for T5) / Reload(for T6) register
Reload register for T6, Capture register for T5
C163
-
C164
C165
C166
C167
-
GPT 2
Microcontrollers
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16x_all.ppt
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GPT 2 Function Diagram
at 20 MHz
C161
Clk max
5.0 MHz
C163
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T5
C164
C165
up / down
Enable
Clear
Enable
C166
INTR
Flag
Capture / Reload
to CAPCOM
Timer T0, T1
Reload
Enable
Clk max
5.0 MHz
Outp.
enables
Toggle
Latch
Run
Enable
Input
Mode
Control
C167
Aux Timer T2 / T4
INTR
Flag
up / down
33-bit cascaded path
GPT 2
Microcontrollers
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GPT 2 Function Diagram
at 20 MHz
C161
Clk max
5.0 MHz
max.
2.5 MHz
C163
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T5
C164
C165
up / down
Enable
Clear
Enable
C166
INTR
Flag
Capture / Reload
to CAPCOM
Timer T0, T1
Reload
Enable
Clk max
5.0 MHz
max.
2.5 MHz
Outp.
enables
Toggle
Latch
Run
Enable
Input
Mode
Control
C167
Aux Timer T2 / T4
INTR
Flag
up / down
33-bit cascaded path
GPT 2
Microcontrollers
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General Purpose Timer 2 (GPT 2)
at 25 MHz
C161
 Two 16-Bit up/down timers (T5, T6)
 Input mode
Timer mode: Internal clock input with prescaler
up to 6.25MHz (160ns)
Counter mode: External clock up to 3.1 MHz
T5 can also be clocked with the toggle bit of T6
 Output mode
Interrupt possibility and toggle function of a port line (via a
toggle bit)
Output of T6 can be used to clock CAPCOM timers
 Count direction of all timers can be dynamically changed
 Cascading of timer T6 with timer T5
 One 16-Bit Capture(for T5) / Reload(for T6) register
Reload register for T6, Capture register for T5
C163
-
C164
C165
C166
C167
-
GPT 2
Microcontrollers
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GPT 2 Function Diagram
at 25 MHz
C161
Clk max
6.25 MHz
max.
3.1 MHz
C163
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T5
C164
C165
up / down
Enable
Clear
Enable
C166
INTR
Flag
C167
Capture / Reload
Reload
Enable
Clk max
6.25 MHz
max.
3.1 MHz
Toggle
Latch
Run
Enable
Input
Mode
Control
Outp.
enables
Aux Timer T2 / T4
INTR
Flag
up / down
33-bit cascaded path
GPT 2
Microcontrollers
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Capture / Compare Unit
(CAPCOM)
C161
 Two 16-bit timers (T0, T1) each with 16-bit reload register
Timer mode: Internal clock input with prescaler up to 2.5
MHz (400ns)
Counter mode: External clock input to T0 up to 1.25 MHz,
output from T6 (GPT2) can be used as clock input
 Two units with sixteen 16-Bit Capture/Compare registers
Individually programmable for Capture or any Compare
mode
Individually allocatable to timer T0/T1
 Various Compare modes for flex. Pulse Width
Modulation(PWM)
Output-Pin toggles if Compare is true
1 or 2 Compare registers can operate to one output-Pin
1 or more Compare events can be detected in
one timer period
Interrupt only mode
-
C163
C164
C165
C166
-
C167
-
PWM generation - CAPCOM
Microcontrollers
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13.03.2016, 23:14
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Capture / Compare Unit 2
(CAPCOM2)
C161
 Two 16-bit timers (T7,T8) each with 16-bit reload register
Timer mode: Internal clock input with prescaler up to 2.5
MHz (400ns)
Counter mode: Output from T3 can be used as clock input
 One unit with eight 16-Bit Capture/Compare registers
Individually programmable for Capture or any Compare
mode
Individually allocatable to timer T7/T8
 Various Compare modes for flex. Pulse Width
Modulation(PWM)
Output-Pin toggles if Compare is true
1 or 2 Compare registers can operate to one output-Pin
1 or more Compare events can be detected in one timer
period
Interrupt only mode
-
C163
C164
C165
C166
C167
-
PWM generation - CAPCOM 2
Microcontrollers
HL MC AT, lehmann
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Capture / Compare Unit 1/2
(CAPCOM 1/2)...
C161
 Four 16-bit timers (T0/T1 & T7/T8), 16-bit reload reg. each
Timer mode: Int. clock input with up to 2.5 MHz (400ns)
Counter mode: External clock input to T0/T7 up to 1.25
MHz, Output from T6 can be used as clock input
CAPCOM 2 can be synchronized via T0 to CAPCOM 1
 Two units with sixteen 16-Bit Capture/Compare registers
Individually program. for Capture or any Compare mode
Individually allocatable to timer T0/T1 or T7/T8
 Various Compare modes for flexible
Pulse Width Modulation(PWM)
Output-Pin toggles if Compare is true
1 or 2 Compare registers can operate to one Output-Pin
One or more Compare events can be detected in one timer
period
Interrupt only mode
-
C163
C164
C165
C166
C167
-
PWM generation - CAPCOM 1/2
Microcontrollers
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CAPCOM(1)
Function Diagram
C161
T0 Reload
Clk max
2.5 MHz
from T6
C163
C164
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T0
C166
Mode Control
Sixteen
16 Bit
Capture/
Compare
Register
CC0-CC15
Edge Select
for
Capture Input
Clk max
2.5 MHz
from T6
C165
Input
Mode
Control
Timer T1
- Capture Mode
- Compare Mode 0
- Compare Mode 1
- Compare Mode 2
- Compare Mode 3
- Double Register
Compare Mode 0
INTR
Flag
C167
INTR
Flag
INTR
Flag
Run
Enable
T1 Reload
PWM generation - CAPCOM (1)
Microcontrollers
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CAPCOM 2
Function Diagram
C161
T7 Reload
Clk max
2.5 MHz
from T6
C163
C164
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T7
C166
Mode Control
Sixteen
16 Bit
Capture/
Compare
Register
CC16-CC33
Edge Select
for
Capture Input
Channel 24 to 27
only Capture
Input possible
Clk max
2.5 MHz
from T6
C165
Input
Mode
Control
Timer T8
Run
Enable
INTR
Flag
- Capture Mode
- Compare Mode 0
- Compare Mode 1
- Compare Mode 2
- Compare Mode 3
- Double Register
Compare Mode 0
C167
INTR
Flag
Channel 31 is able to trigger
an ADC Channel Injection
INTR
Flag
T8 Reload
PWM generation - CAPCOM 2
Microcontrollers
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CAPCOM 2
Function Diagram
C161
T7 Reload
Clk max
2.5 MHz
from T6
C163
C164
Run
Enable
Input
Mode
Control
INTR
Flag
Timer T7
C166
Mode Control
eight
16 Bit
Capture/
Compare
Register
CC16-CC19
CC24-CC27
Edge Select
for
Capture Input
Channel 24 to 27
only Capture
Input possible
Clk max
2.5 MHz
from T6
C165
Input
Mode
Control
Timer T8
Run
Enable
INTR
Flag
- Capture Mode
- Compare Mode 0
- Compare Mode 1
- Compare Mode 2
- Compare Mode 3
- Double Register
Compare Mode 0
C167
INTR
Flag
Channel 27 is able to trigger
an ADC Channel Injection
INTR
Flag
T8 Reload
PWM generation - CAPCOM 2
Microcontrollers
HL MC AT, lehmann
16x_all.ppt
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CAPCOM 1/2
Compare Mode 0 and 1
C161
 Several Compare events are possible within a single Timer
period
C163
C164
C165
FFFF
C166
Compare Value 2
C167
Compare Value 1
Reload Value
is changed to
Mode 1: INTR Flag is set
and Port Pin is toggled
New
Reload Value
Value 2
Compare INTR
Mode 0: only
INTR Flag is set
Compare INTR
Compare Register X: Value 1
Timer INTR
Port Level P1.x
P8.x (C164)
PWM generation - CAPCOM 1/2
Microcontrollers
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CAPCOM 1/2
Compare Mode 2 and 3
C161
 Only one Compare events is possible within a single Timer
period
C163
C164
C165
FFFF
C166
Compare Value 2
C167
Compare Value 1
Reload Value
is changed to
Mode 3: INTR Flag is set.
Port Pin is set at the first
Compare Event and reset
at Timer overflow
Value 2
Timer INTR
Mode 2: only
INTR Flag is set
Compare INTR
Compare Register X: Value 1
New
Reload Value
Port Level P1.x
P8.x (C164)
PWM generation - CAPCOM 1/2
Microcontrollers
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CAPCOM 1/2
Double Register Compare Mode
C161
 Two Compare Register work together to control one Port
Pin
 This mode is selected by a special combination of the
mode 0 and 1
C163
C164
C165
C166
FFFF
C167
Reload Value
the associated
Bank2 Compare Register Y:
(programmed to mode 0)
Value X
Compare INTR
Reg. X
Bank1 Compare Register X:
(programmed to mode 1)
Compare INTR
Reg. Y
Compare Value 2
Compare Value 1
New
Reload Value
Value Y
Timer INTR
Port Level P1.x
P8.x (C164)
PWM generation - CAPCOM 1/2
Microcontrollers
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Pulse Width Modulation Unit
(PWM)
C161
 4 completely indep. PWM channels each with its own timebase
50ns or 12.8µs timer-resolution provides a very wide
frequency range to generate PWM signals
Programmable output polarity
Up to 78 KHz at 8-bit PWM resolution
C163
-
FPWM =
C164
C165
C166
C167
1
=78 KHz
8-bit
2
x 50ms
 Four operation modes
Standard, edge-aligned PWM
Symmetrical, center-aligned PWM for asynchronous motor
control
Burst-mode for modulated PWM signals
Single-shot mode
-
PWM generation - PWM unit
Microcontrollers
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PWM unit
Frequencies and Resolution
C161
C163
PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE-ALIGNED)
10 Bit
12 Bit
14 Bit
C164
Resolution
Input Clock (CPU @ 20 MHz)
8 Bit
16 Bit
CPU Clock (50ns Resolution)
78.1 KHz
19.5 KHz
4.88 KHz
1.22 KHz
305 Hz
C166
CPU Clock / 64 (3.2µs Res.)
1.22 KHz
305 Hz
76.3 Hz
13.1 Hz
4.77 Hz
C167
C165
PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)
Resolution
Input Clock (CPU @ 20 MHz)
8 Bit
10 Bit
12 Bit
14 Bit
16 Bit
CPU Clock (50ns Resolution)
39.1 KHz
9.77 KHz
2.44 KHz
610 Hz
152.6 Hz
610 Hz
152.6 Hz
38.15 Hz
9.54 Hz
2.4 Hz
CPU Clock / 64 (3.2µs Res.)
PWM generation - PWM unit
Microcontrollers
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PWM unit
Function Diagramm
C161
Period Register PP0-PP3
C163
C164
INTR
Flag
Shadow Register
C165
C166
Comparator
20 MHz
78 KHz
C167
Run
Enable
Input
Mode
Control
up/down,clear
Timer PT0-PT3
Output Polarity
Enable
at 20 MHz CPU Clock
PWM
Outputs
Comparator
Shadow Register
Pulse Width Reg. PW0-PW3
4 identical PWM Channels with common Interrupt Control Register
PWM generation - PWM unit
Microcontrollers
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PWM unit
Mode 0 and 1...
C161
PWM Mode 0:
Standard PWM’s or Edge-Aligned PWM’s
PWM Mode 1:
Symmetrical or Center-Aligned PWM’s
C163
C164
Contents of the Period Register (PPx)
C165
C166
Contents of the PWx
Register
Contents of the
PWx Register
Interrupt Request and
Latch of the Shadow Register
PWM Signal
C167
IR and Latch of the
Shadow Register
PWM Signal
If all channels are programmed to mode 0,
edge-aligned PWM signals will be generated.
A duty cycle from 0 to 100% is programmable
If all channels are programmed to mode 1,
center-aligned PWM signals will be generated.
A duty cycle from 0 to 100% is programmable
Possible PWM Signals from other channels programmed to the same mode:
PWMx
PWMy
PWM generation - PWM unit
Microcontrollers
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... PWM unit
Modes
Burst Mode :
Burst Sequence by combining
PWM channel 0 and 1
C161
Single Shot :
Only one PWM Pulse is generated
Mode available for channel 2 and 3
C163
C164
Period Value
Period Value
C165
C166
Period
Value
Pulse width
Value
C167
Timer is
automatically
stopped
Internal Signal
of Channel 0
Timer is
released by
Software again
Output
Signal
Period of
Timer PT1
The Timer can be dynamically changed to
lengthen (retrigger) or shorten the output pulse
Int. Signal
of Channel 1
Output Result: Channel 1 is modulated by Channel 0
PWM generation - PWM unit
Microcontrollers
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Capture / Compare Unit 6
(CAPCOM 6)
C161
 Capture Compare Unit for flexible PWM Signal Generation
 Optimized for Drive Control Applications
 C164CI suitable for
All kinds of inverters
Frequency converters
Motor applications with current control (abc-frame, block
commutation)
Motor applications with speed control.
 Same functionality as CCU of C504
C163
C164
-
PWM generation - CAPCOM 6
Microcontrollers
C165
C166
C167
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CAPCOM 6 - Block Diagram
C161
Period Reg. T12P
Mode
CC Channel 0 CC60
Offset Reg. T12OF
CC Channel 1 CC61
Input
FCPU Control
Compare Timer T12
CC Channel 2 CC62
deadtime
Control
FCPU
Input
Control
Compare Timer T13
10 bit
Port Control Logic
CTRAP
C163
C164
CC60
COUT60
CC61
COUT61
CC62
COUT62
C165
C166
C167
Burst Mode
Comp Reg. CMP13
Period Reg. T13P
PWM generation - CAPCOM 6
COUT63
Block
Commutation
Control
CC6POS0
CC6POS1
CC6POS2
Microcontrollers
M
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CAPCOM 6
Features...
C161
 3-channel 16-bit capture/compare unit (CAPCOM)
CAPCOM6 I/O lines : 2 outputs / channel in compare mode
1 input in capture mode
Channels independently programmable for capture or
compare
Compare timer T12 input clock : fCPU up to fCPU/128
Two operating modes of compare timer T12
- Mode 0 : up-count and reset
- Mode 1 : up-count and down-count
Programmable initial logic output level in compare mode
- 1 compare channel can generate 2 inverted signals
Interrupt generation at
- compare timer reset / count direction change
- compare match / capture event
-
C163
C164
C165
C166
C167
-
PWM generation - CAPCOM 6
Microcontrollers
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...CAPCOM 6
Features
- External trap input
- putting selectively compare outputs to low or high level
- Offset register for automatic constant dead-time generation
 1-channel 10-bit compare unit for PWM signal generation
- Compare timer T13 input clock : f up to f /128
- Edge aligned PWM (compare timer operating mode 0)
- PWM output at COUT3
- enable/disable and output level control
- Combination with CAPCOM unit
CPU
C161
C163
C164
C165
C166
CPU
C167
- Burst mode
- Multi-channel PWM modes
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Compare Timer T12 Operation
C161
 Two count modes
Operating mode 0 : 0000H up to period register
value and reset
Operating mode 1 : up- and down-counting between
0000H and period register value
 Compare operation - match event
CCx outputs toggle state when compare timer matches with
compare register content
COUTx outputs toggle state when compare timer matches
with compare register content plus the value in the T12OF
offset register ---> constant dead time generation
 Capture operation
Storing the compare timer T12 value in the
capture/compare register at a signal transition (rising/falling
edge) at the CCx pin
-
C163
C164
C165
C166
-
C167
-
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Compare Timer Operating Mode 0
C161
a) Standard PWM (Edge Aligned)
b) Standard PWM (Single Edge Aligned)
with constant Single Edge Delay
C163
C164
Period
Value
Period
Value
C165
C166
Compare
Value
0000H
C167
Compare
Value
Offset
tOff
CCX
CCX
COUTX
COUTX
 Both compare timers can use this operating mode
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Compare Timer Operating Mode 1
C161
c) Symetrical PWM (Center Aligned)
d) Symetrical PWM (Center Aligned)
with constant Edge Delay
C163
C164
Period
Value
Period
Value
C165
C166
Compare
Value
0000H
Compare
Value
C167
Offset
tOff
CCX
COUTX
tOff
CCX
COUTX
 Only compare timer T12 can operate is this mode
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Compare Timer Operating Mode 1
Count Value
C161
T12 + T12OF
9
8
CCP=7
Period Reg.
7
6
5
4
3
T12OF=2
Offset Reg.
2
7
6
7
6
5
4
C163
8
6
5
T12
6
5
4
3
5
4
3
2
4
3
2
1
3
2
1
0
Start of T12
C164
7
C165
5
C166
4
C167
3
2
1
Time
0
tOff
CCx (CC=5)
COINI Bit=0
tOff
Duty
Cycles:
29%
COUTx (CC=5)
COINI Bit=0
57%
COUTx (CC=5)
COINI Bit=0
57%
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Multi-Channel PWM Modes...
C161
 Special operating mode of the CAPCOM6, in which
CAPCOM and COMP unit are providing versatile PWM
compare output waveforms
 Four operating modes :
Block commutation mode (e.g.for decoding of hall sensor
signals)
4-pole multi-channel PWM
5-pole multi-channel PWM
6-pole multi-channel PWM
 ...
C163
C164
-
PWM generation - CAPCOM 6
Microcontrollers
C165
C166
C167
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CAPCOM 6
...Multi-Channel PWM Modes
C161
 Block commutation mode :
Position input (CC6POS0# - CC6POS2#) controlled PWM
timing generation
Implementation of a specific control table for hall sensor
input signals at the interrupt inputs
 Multi-pole multi-channel PWM modes :
Compare timer T12 controlled, fixed basic PWM compare
output timing pattern of active and inactive phase at 4, 5, or
6 CCx/COUTx outputs
 Special control register
-
C163
C164
C165
C166
-
PWM generation - CAPCOM 6
Microcontrollers
C167
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CAPCOM 6
Block Commutation Mode...
C161
C163
CC6POS0#
1
1
1
0
0
0
CC6POS1#
0
0
1
1
1
0
CC6POS2#
1
0
0
0
1
1
Input
Signals
C164
C165
C166
C167
CC0
CC1
CC2
Output
Signals
COUT0
COUT1
COUT2
PWM generation - CAPCOM 6
Microcontrollers
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CAPCOM 6
Block Commutation Mode
C161
 Controlled by a fixed pattern table for interrupt input
signals
Specific motor control mode
Control table covers rotate-left/-right/idle/slow-down case
for motor hall sensor input signals
CCx unmodulated / COUTx modulated with compare timer
T13 output
C163
-
PWM generation - CAPCOM 6
Microcontrollers
C164
C165
C166
C167
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CAPCOM 6
5-Pole Multi-Channel PWM Mode...
C161
Start
C163
Compare
Timer T12
C164
C165
CC0
C166
COUT1
C167
CC2
COUT0
COUT2
or
Active phase modulated
by Compare Timer T12
Active phase modulated
by Compare Timer T13
PWM generation - CAPCOM 6
active
phase
Microcontrollers
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CAPCOM 6
...5-Pole Multi-Channel PWM Mode
C161
 Active phase can be modulated by
Compare timer T12 :
modulation for two compare
timer T12 periods
Compare timer T13 :
compare timer T13 output signal
is switched to CCx
or COUTx during active phase
 Programmable polarity of active/inactive phase
-
PWM generation - CAPCOM 6
Microcontrollers
C163
C164
C165
C166
C167
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CAPCOM 6
...Block Commutation Mode
5-Pole Multi-Channel PWM Mode:
Rotate Left Mode (BCM1,0 =1,0) with COINI XX111111B
C161
Setting bit
NMCS by
software
Bit 1
NMCS 0
C163
C164
C165
CC0
C166
C167
COUT1
CC2
COUT0
COUT2
1
2
3
4
5
1
2
3
4
5
1
active
phase
Static level during active phase
(at CCx and COUTx outputs)
PWM generation - CAPCOM 6
Compare Timer T13 modulation
during active phase
Microcontrollers
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CAPCOM 6
Drive Applications Area
C161
with C164CI
 AC Drives
-
("Drehstrommotoren")
X
("Synchronmotoren")
X
-
Induction motors
("Asynchronmotoren")
X
-
Reluctance motors
("Reluktanzmotoren")
X
("Schrittmotoren")
-
-
Unipolar stepper motors ("Unipolare Schrittmotoren")
X
-
Bipolar stepper motors
("Bipolare Schrittmotoren")
X
("Gleichstrommotoren")
X
 DC Drives
C164
C165
Synchronous motors,
Brushless DC motors
 Stepper Motors
C163
PWM generation - CAPCOM 6
Microcontrollers
C166
C167
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Analog Digital Converter
(ADC) - C161RI only
C161
 8-Bit ADC based on the successive approximation
principle
flexible conversion-time control with minimal
7.5µs conversion-time
On-chip sample- & hold-circuit
(1.5 µs sample-time)
 4 multiplexed input channels
Fixed channel single channel conversion
Fixed channel single channel continuous conversion for
permanent data tracking
 8-bit result can be left- or right- adjusted to a
10-bit field
 Interrupt on
Overrun error
Conversion complete
C163
-
C164
C165
C166
C167
-
ADC
Microcontrollers
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8-Bit A/D Converter
Block Diagram - C161RI only
C161
C163
Channel and Mode Control
Conversion Control
C164
C165
Comparator
prescaler
Analog
Inputs
4
Channel
Analog
MUX
Reference
Voltage
ADC
Timing Control
and Successive
Approximation
Register
INTR
Flag
C166
INTR
Flag
C167
C-NET
Switch
Tree
Result Register
Microcontrollers
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Analog Digital Converter
(ADC)
C161
 10-Bit ADC based on the successive approximation
principle
9.7µs conversion-time
On-chip sample- & hold-circuit (1.6 us sample-time)
 10 multiplexed input channels
Flexible operation mode
Single-channel and single-channel-continuous for periodic
data acquisition
Auto-scan and auto-scan-continuous for permanent data
tracking
 Easy error handling and channel identification
10-bit result and channel number in result register
Overrun error check
C163
-
C164
C165
C166
C167
-
ADC
Microcontrollers
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10-Bit A/D Converter
Block Diagram
C161
C163
Channel and Mode Control
Conversion Control
C164
C165
Comparator
Timing Control
and Successive
Approximation
Register
Analog
Inputs
10 (16)
Channel
Analog
MUX
Reference
Voltage
ADC
INTR
Flag
C166
INTR
Flag
C167
C-NET
Switch
Tree
Channel
Information
Result Register
Microcontrollers
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Analog Digital Converter
(ADC)
C161
 10-Bit ADC based on the successive approximation
principle
9.7µs conversion-time
On-chip sample- & hold-circuit (1.6 us sample-time)
8 multiplexed input channels
Automatic self-calibration after conversion
 Flexible operation mode
Single-channel and single-channel-continuous for periodic
data acquisition
Auto-scan and auto-scan-continuous for permanent data
tracking
Channel-injection mode with own result-register can be
used to interrupt the scan modes
 Easy error handling and channel identification
10-bit result and channel number in result register
Overrun error check
C163
-
C164
C165
C166
C167
-
ADC
Microcontrollers
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Analog Digital Converter
(ADC)
C161
 10-Bit ADC based on the successive approximation
principle
9.7µs conversion-time
On-chip sample- & hold-circuit (1.6 us sample-time)
16 Multiplexed input channels
Automatic self-calibration after conversion
 Flexible operation mode
Single-channel and single-channel-continuous for periodic
data acquisition
Auto-scan and auto-scan-continuous for permanent data
tracking
Channel-injection mode with own result-register can be
used to interrupt the scan modes
 Easy error handling and channel identification
10-bit result and channel number in result register
Overrun error check
C163
-
C164
C165
C166
C167
-
ADC
Microcontrollers
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10-Bit A/D Converter
Block Diagram
C161
C163
Channel and Mode Control
Conversion Control
C164
C165
Comparator
Timing Control
and Successive
Approximation
Register
Analog
Inputs
8 (16)
Channel
Analog
MUX
Reference
Voltage
C166
INTR
Flag
C167
C-NET
Switch
Tree
Channel
Information
Channel
Selection
ADC
INTR
Flag
Result Register
Result Register for Channel Injection Mode
Microcontrollers
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Asynchronous / Synchronous
Serial Channel (USART) at 16MHz
C161
 Synchronous / asynchronous serial channel with its own
baud-rate-generator
 Asynchronous mode with max 500 KBaud transfer rate
Full duplex (receive and transmit at the same time)
programmable features:
1 or 2 stop bits, 7, 8 or 9 data bits
Generation of parity- or wake-up bit at data transmission
Odd or even parity
Error detection (parity, overrun, framing)
Wake-up check (receive int. flag is set if wake-up bit is true)
 Synchronous mode with max 2.0 Mbit/sec transfer range
Half duplex operation (only transmit or receive possible)
Easy I/O expansion with external shift register
Overrun error detection
C163
C164
-
USART
Microcontrollers
C165
C166
C167
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Asynchronous / Synchronous
Serial Channel (USART) at 20MHz
C161
 Synchronous / asynchronous serial channel with its own
baud-rate-generator
 Asynchronous mode with max 625 KBaud transfer rate
Full duplex (receive and transmit at the same time)
programmable features:
1 or 2 stop bits, 7, 8 or 9 data bits
Generation of parity- or wake-up bit at data transmission
Odd or even parity
Error detection (parity, overrun, framing)
Wake-up check (receive int. flag is set if wake-up bit is true)
 Synchronous mode with max 2.5 Mbit/sec transfer range
Half duplex operation (only transmit or receive possible)
Easy I/O expansion with external shift register
Overrun error detection
C163
C164
-
USART
Microcontrollers
C165
C166
C167
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Asynchronous / Synchronous
Serial Channel (USART) at 25MHz
C161
 Synchronous / asynchronous serial channel with its own
baud-rate-generator
 Asynchronous mode with max 780 KBaud transfer rate
Full duplex (receive and transmit at the same time)
programmable features:
1 or 2 stop bits, 7, 8 or 9 data bits
Generation of parity- or wake-up bit at data transmission
Odd or even parity
Error detection (parity, overrun, framing)
Wake-up check (receive int. flag is set if wake-up bit is true)
 Synchronous mode with max 3.1 Mbit/sec transfer range
Half duplex operation (only transmit or receive possible)
Easy I/O expansion with external shift register
Overrun error detection
C163
C164
-
USART
Microcontrollers
C165
C166
C167
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USART
Block Diagram
C161
C163
CPU CLK
Baud Rate Generator
C164
from internal Bus
Asynchronous/
Synchronous
INTR
Flag
Transmit
INTR
Flag
Receive
C166
Transmit Shift Register
C167
Shift CLK
Control
Unit
INTR
Flag
ERROR
Receive Shift Register
Port
Pin
Receive Buffer
Control Reg.
USART
C165
Port
Pin
to internal Bus
Microcontrollers
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Synchronous Serial Channel
(SSC), SPI compatible at 16MHz
C161
 Full duplex Synchronous Serial Channel (SSC) with its
own baudrate generator for high speed communication
 Up to 4 Mbit/sec transfer rate
 SPI compatible
 Master (clock is output) or slave mode (clock is input)
 Programmable features to satisfy various communication
requirements
MSB or LSB first
Data frame from one to 16-bit
Clock polarity and phase
C163
C164
C165
C166
C167
-
USART
Microcontrollers
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Synchronous Serial Channel
(SSC), SPI compatible at 20 MHz
C161
 Full duplex Synchronous Serial Channel (SSC) with its
own baudrate generator for high speed communication
 Up to 5 Mbit/sec transfer rate
 SPI compatible
 Master (clock is output) or slave mode (clock is input)
 Programmable features to satisfy various communication
requirements
MSB or LSB first
Data frame from one to 16-bit
Clock polarity and phase
C163
C164
C165
C166
C167
-
USART
Microcontrollers
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Synchronous Serial Channel
(SSC), SPI compatible at 25MHz
C161
 Full duplex Synchronous Serial Channel (SSC) with its
own baudrate generator for high speed communication
 Up to 6.25 Mbit/sec transfer rate
 SPI compatible
 Master (clock is output) or slave mode (clock is input)
 Programmable features to satisfy various communication
requirements
MSB or LSB first
Data frame from one to 16-bit
Clock polarity and phase
C163
C164
C165
C166
C167
-
USART
Microcontrollers
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Synchronous Serial Channel - Block
Diagram
CPU
Clock
Baud Rate
Generator
Clock
Control
SSCCLK
Master Mode
Slave Mode
C161
C163
Master / Slave
Selection SSCDO
C164
C165
Shift Register
programmable from 1 - 16-bit
SSCDI
C166
C167
Interrupt
Request
Control Unit
with Control
and Status
Registers
MSB- / LSB-First Selection
Receive Buffer
Transmit Buffer
Internal Bus
SSP
Microcontrollers
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Synchronous Serial Port
(SSP)
C161
 Synchronous Serial Port was designed for communication
with external slave devices such as EEPROMs
 SSP can be programmed to...
send command, address or data information to a peripheral
receive data from a peripheral
 Three-wire interface compatible to SPI-protocol
Bi-directional serial data line
Configurable clock control line
Two dedicated configurable chip enable lines
Baudrate up to 12.5 Mbit/s
Heading selectable (LSB / MSB first)
 Busy flag (Check if SSP is busy or idle)
 Interrupt (XP1INT) is generated at the end of a transfer
C163
C164
-
SSP
Microcontrollers
C165
C166
C167
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Synchronous Serial Port
Block Diagram
C161
Control
Logic
Baudrate
Generator
C163
SSPCE0
(P4.5)
Chip
Enable
Control
Output
Control
Clock
Control
Output
Control
SSPCLK
(P4.7)
Input /
Output
Control
SSPDAT
(P4.6)
C164
SSPCE1
(P4.4)
C165
C166
C167
SSPCON1
Shift Unit & Shift Control
SSPTB2
SSPTB1
SSPCON0
Interrupt
(XP1INT)
8 bit
8 bit
In order to use the SSP,
XBUS-Interface
SSP
8 bit
SSPTB0/
SSPRB0
- Bit XPEREN (SYSCON.2) must be set during
initialization (before EINIT instruction)
- Pins P4.4 to P4.7 must not be used as
segment address lines
(max. 5 x 1 Mbyte external memory)
Microcontrollers
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Synchronous Serial Port
Detailed Block Diagram
C161
INTERNAL BUS
XBCON
XADRS
C163
X-BUS CONTROLLER
8
SSPCON0
SIN SSPTB0/ SOUT
SSPRB0
8
0
1
SIN
SSPTB1
C164
8
SOUT
0
1
SIN
C165
SOUT
SSPTB2
1
0
SDATA I/O
(P4.6)
SSPCON1
Clock Generator
SSP
CONTROLLER
Shift / Load
SSP
C166
C167
SCLK
(P4.7)
1-Byte
2-Byte
3-Byte
CS1
CS0
SSPCE1
(P4.4)
SSPCE0
(P4.5)
Microcontrollers
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Synchronous Serial Port
Configurations...
C161
 Configuration of the Chip Enable lines:
Chip Enable lines may be selected separately:
- no Chip Enable line selected
- Chip Enable line 0 (SSPCE0) selected
- Chip Enable line 1 (SSPCE1) selected
- Both Chip Enable lines selected (take care with READoperations)
- Polarity can be selected for each Chip Enable line
(active high / active low)
-
SSP
Microcontrollers
C163
C164
C165
C166
C167
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...Synchronous Serial Port
Configurations
C161
 Configuration of the Clock line (like SSC on C167/C165)
Clock polarity can be selected:
- Idle Clock line high (leading clock edge is high-tolow transition)
- Idle Clock line low (leading clock edge is low-to-high
transition)
Clock edge can be selected:
- Shift data on leading clock edge, latch on trailing edge
- Latch data on leading clock edge, shift on trailing edge
-
C163
C164
C165
C166
C167
-
SSP
Microcontrollers
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Differences between SSP and SSC
SSP (C163)
Synchronous Serial Port
C161
SSC
Synchronous Serial Channel
C163
C164
Up to 10 MBaud @ 20 MHz CPU
clock
Only half duplex communication
possible;
one bidirectional data line
Shift clock can only be generated
(master only)
Data width 1 byte
No error detection mechanisms
Two dedicated chip enable lines
Connected to XBUS
1 interrupt source dedicated to SSP
SSP vs. SSC
Up to 5 MBaud @ 20 MHz CPU
clock
Full duplex communication
possible;
two data lines (Transmit, Receive)
Shift clock can be generated
(master) or received (slave)
Data width can be chosen from 2
bits to 16 bits
Error detection mechanisms
No dedicated chip enable lines
Connected to Internal Bus
3 interrupt sources dedicated to
SSC
Microcontrollers
C165
C166
C167
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Serial E2PROM connected to SSP
C161
C163
EEPROM
C163
(e.g. X25C02)
C164
P4.4 / SSPCE1
C165
CS#
(Chip Select)
C166
C167
P4.5 / SSPCE0
SO
(Serial Data
Output)
P4.6 / SSPDAT
SI
(Serial Data
Input)
P4.7 / SSPCLK
Application for the SSP
SCK
(Clock)
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Single Write Operation to
EEPROM (X25C02)
C161
C163
SSPCLK
C164
C165
SSPDAT
C166
Write
Enable
>500 ns
Write
Command
Address
(e.g. A5h)
C167
Data
(e.g. 99h)
SSPCE0/1
SSPTB0 = 0x06;
/* Write Enable */
Note:
SSPTB2 = 0x02;
SSPTB1 = 0xA5;
SSPTB0 = 0x99;
/* Write Command */
/* Address */
/* Data */
- After the data has been written, the EEPROM needs 10 ms to store the data.
- SSPCON 0 and SSPCON 1 must be configured before the operation.
Application for the SSP
Microcontrollers
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Single Read Operation to
EEPROM (X25C02)
C161
one clock-cycle needed
for EEPROM to respond
C163
C164
C165
SSPCLK
C166
SSPDAT
C167
Read
Command
Address
(e.g. A5h)
Data
(e.g. 99h)
sent by EEPROM
SSPCE0/1
SSPTB1 = 0x03;
SSPTB0 = 0xA5;
/* Read Command */
/* Address */
Note: SSPCON 0 and SSPCON 1 must be configured before the operation.
Application for the SSP
Microcontrollers
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Siemens, The CAN Reference!
C161
C163
C164
C165
C166
C167
CAN Bus
Microcontrollers
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User Benefits...
C161
 CAN is low cost
Serial bus with two wires: good price/performance ratio
Low cost protocol devices available driven by high volume
production in the automotive and industrial markets
About 15.000.000 CAN nodes in use so far
 CAN is reliable
Sophisticated error detection and error handling
mechanisms results in high reliability transmission
Example: 500 kbit/s, 25% bus load, 2000 hours per year:
One undetected error every 1000 years
Erroneous messages are detected and repeated
Every bus node is informed about an error
High immunity to Electromagnetic Interference
 ...
-
CAN Bus
Microcontrollers
C163
C164
C165
C166
C167
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...User Benefits...
C161
 CAN means real-time
Short message length (0 to 8 data bytes / message)
Low latency between transmission request and actual start
of transmission
Inherent Arbitration on Message Priority (AMP)
Multi Master using CSMA/CD + AMP method
 CAN is flexible
CAN Nodes can be easily connected / disconnected
(i.e. plug & play)
Number of nodes not limited by the protocol
 CAN is fast
maximum data rate is 1 MBit/s @ 40 m bus length
(still about 40 kBit/s @ 1000 m bus length)
 ...
-
CAN Bus
Microcontrollers
C163
C164
C165
C166
C167
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...User Benefits
C161
 CAN allows Multi-Master Operation
Each CAN node is able to access the bus
Bus communication is not disturbed by faulty nodes
Faulty nodes self swith-off from bus communication
 CAN means Broadcast Capability
Messages can be sent to single/multiple nodes
All nodes simultaneously receive common data
 CAN is standardized
ISO-DIS 11898 (high speed applications)
ISO-DIS 11519-1 (low speed applications)
-
CAN Bus
Microcontrollers
C163
C164
C165
C166
C167
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Higher Layer Protocols...
C161
 CAN Application Layer (CAL)
Layer-7-standard defined by CiA (CAN in Automation)
Network management service provides initialisation,
surveillance and configuration of nodes in a standardized
way
Takes care of all aspects for the realisation of open
communication via CAN (makes sure manufacturer-specific
systems work together)
Available implementations of CAL make it easy for the user
to define sophisticated standardized Controller Area
Networks
 ...
-
C163
C164
C165
-
C166
C167
-
CAN Bus
Microcontrollers
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...Higher Layer Protocols
C161
 CANopen (CiA DS-301)
Application profile based on CAL
While CAL determines the way of communicating, an
Application Profile determines the meaning of specific
messages for the respective application
Target: device interchangeability for certain applications
 Further higher level protocols / standards:
Automotive Sector: VOLCANO, OSEK (in development)
Industrial Automation: DeviceNet (Allen Bradley),
SDS (Honeywell)
-
C163
C164
C165
-
CAN Bus
Microcontrollers
C166
C167
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Application Examples...
C161
 CAN in motor vehicles (cars, trucks, buses)
Enables communication between ECUs like engine
management system, anti-skid braking, gear control, active
suspension ... (power train)
Used to control units like dashboard, lighting, air
conditioning, windows, central locking, airbag, seat belts
etc. (body control)
 CAN in utility vehicles
e.g. construction vehicles, forklifts, tractors etc.
CAN used for power train and hydraulic control
 ...
-
C163
C164
-
C165
C166
C167
-
CAN Bus
Microcontrollers
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...Application Examples...
C161
 CAN in trains
High need of data exchange between the different
electronic subsystem control units
Mainly data about acceleration, braking, door control, error
messages etc. but also for diagnosis
 CAN in industrial automation
Excellent way of connecting all kinds of automation
equipment (control units, sensors and actuators)
Used for initialization, program and parameter up/download, exchange of rated values / actual values,
diagnosis etc.
Machine control (printing machines, paper- and textile
machines etc.): Connection of the different intelligent
subsystems
Transport systems
 ...
-
C163
C164
C165
C166
-
C167
-
CAN Bus
Microcontrollers
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...Application Examples
C161
 CAN in medical equipment
Computer tomographs, X-ray machines, dentist chairs,
wheel chairs
 CAN in building automation
Heating, air conditioning, lighting, surveillance etc.
Elevator and escalator control
 CAN in household appliances
Dishwashers, washing machines, even coffee machines...
 CAN in office automation
photo copier, interface to document handler, paper feeding
systems, sorter
communicates status, allows in field connection or "hot
swapping"
DocuText Systems, i.e. automatic print, sort and bind on
demand
-
C163
C164
C165
-
CAN Bus
Microcontrollers
C166
C167
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Some things worth knowing about
CAN...
C161
 Developed in the mid-eighties by BOSCH
 Asynchronous serial bus with linear bus structure and
equal nodes (Multi Master bus)
 CAN does not address nodes (address information is
inside the messages combined with message priority)
 Two bus states: dominant and recessive
 Bus logic according to "Wired-AND" mechanism:
dominant bits (Zeros) override recessive bits (Ones)
 Bus Access via CSMA/CD with NDA (Carrier Sense
Multiple Access/ Collision Detection with Non-Destructive
Arbitration)
CAN Bus
Microcontrollers
C163
C164
C165
C166
C167
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...Some things worth knowing about
CAN
recessive
C161
C163
NODE A
C164
dominant
recessive
NODE B
C165
C166
C167
dominant
bus idle
recessive
CAN BUS
dominant
Node B sends out recessive
but reads back dominant level
CAN Bus
Node B loses arbitration
and switches to receive
Microcontrollers
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Typical CAN node structure
C161
Node A
Node B
e.g.
ABS
e.g.
EMS
C163
Application
C164
C165
Host-Controller
e.g.
80C166
CAN-Controller
e.g.
SAE81C90
C166
e.g.
C167CR
or
C515C
CAN
C167
(more nodes)
CANTransceiver
CAN_H
CAN-Bus
UDiff
CAN_L
CAN Bus
Microcontrollers
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CAN Data Frames...
C161
 There are mainly two ways of communicating:
One node is 'talking', all other nodes 'listen'
Node A is asking Node B for something and gets the
answer.
 To 'talk', CAN nodes use Data Frames.
A Data Frame consists of an Identifier, the data to be
transmittedand a CRC-Checksum.
-
C163
C164
C165
-
Identifier
CAN Bus
Data Field (0..8 Bytes)
C166
C167
CRC-Field
Microcontrollers
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...CAN Data Frames
- The identifier specifies the contents of the message
-
C161
C163
('engine speed', 'oil temperature', etc.) and the message
priority
The Data Field contains the corresponding value
('6000 rpm', '110°C', etc.)
The Cyclic Redundancy Check is used to detect
transmission errors.
All nodes receive the Data Frame. Those who do not need
the information, just don't store it.
CAN Bus
Microcontrollers
C164
C165
C166
C167
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CAN Basics...
C161
 To 'ask' for information, CAN nodes use Remote Frames.
A Remote Frame consists of the Identifier and the CRCChecksum.
It contains no data.
-
Identifier
C163
C164
C165
C166
CRC-Field
C167
- The identifier contains the information that is requested
-
('engine speed', 'oil temperature', etc.) and the message
priority.
The node that is supposed to provide the requested
information
(e.g. the sensor for the oil temperature) does so by sending
the corresponding Data Frame (same identifier, the Data
Field contains the desired information).
CAN Bus
Microcontrollers
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...CAN Basics
C161
C163
C164
C165
C166
How hot is the oil ?
Node A
Remote Frame; Identifier 'oil_tmp'
115 °C !
C167
Node B
(oil temp.sensor)
~~~~
~
~~~~
115°C
~
Data Frame; Identifier 'oil_tmp';
contains desired information
CAN Bus
Microcontrollers
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Standard CAN /
Extended CAN...
C161
 Most CAN nodes talk in the 'language' that most other CAN
nodes understand: They use Standard Data or Remote
Frames.
A Standard Frame contains an identifier which is 11 bits
long.
With this 11 bits, 211 (=2048) different messages can be
addressed.
CAN nodes using Standard-CAN-Frames use the CAN
Specification Version 2.0A.
 Some CAN nodes talk with a special 'accent':
They use Extended Data or Remote Frames.
An Extended Frame contains an identifier which is 29 bits
long.
...
C163
-
C164
C165
C166
C167
-
CAN Bus
Microcontrollers
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...Standart CAN /
Extended CAN...
- Over 536 million (2 ) different messages can be
addressed.
- CAN nodes using Extended-CAN-Frames use the CAN
C161
29
C163
C164
Specification Version 2.0B (active).
 Some Standard-CAN nodes don't understand this 'accent',
but they tolerate it and just don't care.
If an Extended Frame is 'on the air', these CAN nodes
cannot store the data, but they as well do not produce
errors.
These CAN nodes use CAN Version 2.0A, but are also
known as Version 2.0B passive.
They can be used in a Controller Area Network where
Extended Frames are used.
 ...
C165
C166
-
C167
-
CAN Bus
Microcontrollers
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...Standart CAN /
Extended CAN
C161
 Some Standard-CAN nodes don't understand and also
don't tolerate this 'accent'.
If an Extended Frame is 'on the air', these CAN nodes
produce errors.
These CAN nodes use only CAN Version 2.0A.
They can not be used in a Controller Area Network where
Extended Frames are used.
C163
-

CAN Bus
C164
C165
C166
C167
16 bit parts: C167CR, C164CI: V2.0B active
Microcontrollers
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Basic CAN /
Full CAN...
C161
 In some CAN controllers, only the basic CAN functions are
implemented. They are called Basic-CAN controllers.
Mostly there's only one transmit buffer and one or two
receive buffers for transmission and reception of the Data- /
Remote Frames.
Each incoming message is stored. The host CPU has to
decide whether the message data is needed or not.
Therefore these controllers should only be used in CANs
with very low baudrates and/or very few messages
because of the high CPU load. Advantage: They use the
least possible silicon area.
Messages
Received
Host CPU
 ...
to be sent
Messages
C163
-
C164
C165
-
Receive Buffer
CAN Bus

low
Transmit Buffer
Basic-CAN Controller
CAN Bus
C166
C167
high
CPU load
Microcontrollers
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...Basic CAN /
Full CAN...
C161
 In the other CAN controllers, also message management
and acceptance filtering are implemented. They are called
Full-CAN controllers.
There are several Message Objects, each with its own
identifier.
Only if a message for one of these preprogrammed
identifier is received, it is stored and the CPU is interrupted.
In this way, the CPU load is low.
 ...
C163
-
Message Object 1
CAN Bus
Acceptance
Filtering
Message Object 2
.
.
Message
Management
Message Object n
Full-CAN Controller
CAN Bus
C164
C165
C166
C167

low
high
CPU load
Host CPU
Microcontrollers
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...Basic CAN /
Full CAN
C161
 All Siemens CAN-Controllers are Full-CAN controllers.
But they also provide Basic-CAN functionality
one message object can be used like a Basic CAN receive
register
C163
-
C164
C165
C166
C167
CAN Bus
Microcontrollers
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Features of the CAN Module on
C167CR / C164CI...
C161
 Functionality corresponds to
AN 82527
 Complies with CAN spec
V2.0B active
(Standard- und Extended-CAN)
 Maximum CAN Transfer Rate
(1 MBit/s)
 Full CAN Device
15 Message Objects with
their own identifier and their
own status- and control bits
Each Message Object can
be defined
as Transmit- or Receive
Object
 ...
C163
C164
C165
C166
C167
-
CAN Module
Microcontrollers
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...Features of the CAN Module on
C167CR / C164CI
C161
 Programmable Mask Registers for Acceptance Filtering
Global Mask for incoming Messages (Full-CAN-Objects)
Additional Mask for Message Object 15
(Basic-CAN-Feature)
 Basic CAN Feature (Message Object 15)
Equipped with two Receive Buffers
Own Global Mask Register for Acceptance Filtering
 Connection to the Host CPU (C166-Core)
Module access via chip-internal XBUS
(16-bit demultiplexed mode)
Interrupt connection to the CPU; Flexible interrupt event
control
 To connect the application to CAN only a CAN transceiver
is needed
-
C163
C164
C165
-
CAN Module
Microcontrollers
C166
C167
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Connecting the to CAN
C161
C163
C164
C167CR/C161CI
Pa.b
Connection
to the
Application
CAN-Bus
Transceiver
CAN_L
P4.5
CAN_RxD
CAN_H
C166
Receive
CAN_H
P4.6
CAN_TxD
Pc.d
C165
C167
Transmit
CAN_L
(Standby)
P2.0
R(opt)
Vref
n.c.
CAN Module
Microcontrollers
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I2C module
C161RI only





C161
7 and 10-bit addressing, 400KHz
2 channels (multiplexed)
master mode
slave mode
multimaster mode
C163
C164
C165
C166
Output
Control
µC
C167
SDAx
I²C
Module
Generic
data line
Generic
clock line
SDA0
SCL0
SCLx
Output
Control
I2C module
Microcontrollers
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Real Time Clock
(RTC) - C161RI / C164CI
C161
 Counts Time Ticks
 Time Ticks are defined by external crystal frequency and
programmable prescaler (trim register)
 Cyclic time based Interrupt (see separate foil)
Cycle Time can be adjusted via Reload Register (trim
register)
Interrupt Request on XPER3 Interrupt Node
 Additional Function
RTC register and programmable prescaler can be
concatenated to build a 48-bit timer unit
C163
C164
C165
-
Real Time Clock
Microcontrollers
C166
C167
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RTC
Block Diagram
C161
Programmable Divider
Interrupt
C163
Trim Register
C164
16 bit Reload Value
C165
C166
RTC High
RTC Low
32-bit Timer
8 bit
Prescaler
T 14
RTC
Clock Driver
Oscillator
XTAL
C167
16-bit Timer
Time between two Interrupts
Crystal or
external
Oscillator
external
Oscillator
Oscillator Frequency
4 MHz
5 MHz
8 MHz
10 MHz
12 MHz
16 MHz
20 MHz
24 MHz
Real Time Clock
Minimal Time
0.064 ms
0.052 ms
0.032 ms
0.026 ms
0.022 ms
0.016 ms
0.013 ms
0.011 ms
Maximal Time
4.1 s
3.35 s
2s
1.6 s
1.3 s
1s
0.8 s
0.6 s
Possible Time Base RTC
1s
1s
1s
1s
1s
1s
0.1 s
0.1 s
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RTC
Cyclic time based Interrupt
C161
C163
Active Mode with flexible
Peripheral Management
Active Mode with flexible
Peripheral Management
C164
C165
C166
IDLE MODE
C167
1 Cycle
 Combination of Active Mode and Idle Mode
 During Active Mode all not used peripherals are disabled (Flexible
Peripheral Management)
 Cyclic waking up from Idle Mode to Active Mode via
programmable RTC interrupt
 Waking up on external events via interrupt (ASC, SSC, CAN, EXIN)
Real Time Clock
Microcontrollers
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Watchdog Timer
(WDT) at 16 MHz
C161
 16-Bit timer overflow results in:
Software reset
Pulls RSTOUT Pin low
Sets identification bit and leaves WDT enabled
 Programmable input clock
 High Byte reload register
 Timer period from 32µs to 588ms
 Can be reloaded with a special instruction
-
Watchdog
Microcontrollers
C163
C164
C165
C166
C167
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Watchdog Timer
(WDT) at 20 MHz
C161
 16-Bit timer overflow results in:
Software reset
Pulls RSTOUT Pin low
Sets identification bit and leaves WDT enabled
 Programmable input clock
 High Byte reload register
 Timer period from 25.6µs to 470ms
 Can be reloaded with a special instruction
-
Watchdog
Microcontrollers
C163
C164
C165
C166
C167
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Watchdog Timer
(WDT) at 25 MHz
C161
 16-Bit timer overflow results in:
Software reset
Pulls RSTOUT Pin low
Sets identification bit and leaves WDT enabled
 Programmable input clock
 High Byte reload register
 Timer period from 20.5µs to 376ms
 Can be reloaded with a special instruction
-
Watchdog
Microcontrollers
C163
C164
C165
C166
C167
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WDT
Block Diagram
C161
8-bit
reload
C163
zero
C164
C165
service
WDT
CPU CLK / 2
C167
16-bit Timer
high Byte
CPU CLK / 128
C166
RSTOUT
low Byte
on
overflow
Software
Reset
WDT control
Watchdog
Microcontrollers
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System Clock Features
PLL
C161
 On-chip PLL circuit implemented
C163
 Variety of different clock options available:
System Clock can be selected to be 0.5, 1, 1.5, 2, 2.5, 3, 4
and 5 times the externally applied frequency at the XTALpins
C164
C165
C166
C167
 In case of external clock failure:
PLL Unlocked Interrupt (XP3INT) is generated
PLL runs on its base frequency (5...10 MHz)
C164 and C163 can perform emergency operation
 External clock is monitored even if clock options 'W'
(direct clock drive) or '0.5' (prescaler mode) are selected
-
PLL
Microcontrollers
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Clock Options
C161
P0H7 P0H6 P0H5
1
1
1
Clock
PLL
Option factor
4
4
Prescalar
Note
OFF
default
1
0
1
2
2
OFF
1
1
0
3
3
1
0
0
5
0
1
1
0
0
0
0
fOSC : f CPU
C163
C164
fOSC
fCPU
C165
fOSC
fCPU
C166
OFF
fOSC
C167
5
OFF
fOSC
W
OFF
OFF
1
0.5
OFF
ON
1
0
1.5
3
ON
0
0
2.5
5
ON
fCPU
fCPU
direct clock
drive
prescalar
mode
fOSC
fCPU
fOSC
fCPU
fOSC
fCPU
fOSC
fCPU
0 = external pull- down
PLL
Microcontrollers
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Power Management
Modular Version 2.0
C161
C163
C164
C165
C166
Power
C167
Management
Power Management
Microcontrollers
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Modular Design
Overview
C161
C163
Power Management
C164
C165
C166
C167
Power
Saving
Modes
Flexible
Clock
Generation
Management
Power Management
Flexible
Peripheral
Management
Real
Time
Clock
Microcontrollers
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Power Saving Modes
C161
 IDLE Mode
Disabling of CPU and internal memory modules
C163
All peripherals can be enabled
C164
Enabling of CPU via interrupt
C165
 Power Down Mode
C166
Disabling of complete controller functionality
C167
Optional running of real time clock
Optional disabling of port output drivers (tristate)
Preservation of internal RAM content for VCC voltage higher than
2.5 V
Enabling of controller functionality via reset
-
Power Management
Microcontrollers
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Flexible Clock Generation Management
Clock Sources
C161
 Basic Clock Source
Selection between different sources via port 0 configuration
- Direct drive (fCPU = fOSC)
- Prescaler (fCPU = fOSC / 2)
- PLL (fCPU = f OSC * PLLfactor)
Selection can not be changed via software
 Slow Down Divider Clock Source
Programmable oscillator clock divider (fCPU = fOSC / SDD
factor)
Dividing factor can be changed by software
Optional lower frequency via second 32 kHz crystal
(C161RI only)
-
C163
C164
C165
C166
-
Power Management
Microcontrollers
C167
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Flexible Clock Generation Management
Overview
XTAL3
32 kHz
OSC2
Software
SYSCON2.SOSC
fOSC2
C163
M
U
X
XTAL4
XTAL1
OSC1
C161
fOSC
C164
SDD
M
U
X
2:1
PLL
Direct Drive
fOSC1
M
U
X
C165
fCPU
C166
C167
XTAL2
Clock
Detection
Software
Hardware Selection on Reset
32:1
M
U
X
RCD
fRTC
Software
SYSCON2.RSC
Power Management
C161RI only
Microcontrollers
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Flexible Clock Generation Management
Slow Down Divider (SDD) - Features
C161
 Significant reduction of power consumption
 Reduced CPU frequency by programmable clock divider
5-bit Reload Counter for programmable divider with factor 1-32
fCPU = fOSC / SDD factor (e.g. 16 MHz / 32 = 0.5 MHz)
 Notes:
Output CLKOUT also shows the reduced frequency
No OWD available, if PLL is stopped during Slow Down Clock
Generation
-
Power Management
Microcontrollers
C163
C164
C165
C166
C167
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Flexible Clock Generation Management
Slow Down Divider (SDD)
Slow Down Divider (SDD)
C161
C163
CLKREL
C164
C165
Reload
C166
fOSC
Reload Counter
C167
fSDDOUT
fOSC
fSDDOUT
CLKREL=3
CLKREL=5
CLKREL=6
CLKREL=9
Power Management
Microcontrollers
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Flexible Clock Generation Management
Optimized Oscillator
C161
C163
 Oscillator Start-up voltage  3 V power supply
 Stable oscillation down to 2.7 V
 Minimum oscillator power consumption at
3 V power supply (oscillator only)
 Crystal frequency range:
3.5 MHz  fcrystal  16 MHz
C164
C165
C166
C167
 External oscillator input frequency range:
1 MHz  foscillator  40 MHz
Power Management
Microcontrollers
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Flexible Clock Generation Management
Register Definition
C161
C163
C164
SYSCON2
Flexible Clock Generation Management
C165
C166
CLK
LOCK
CLKREL
CLKCON
SOSC
RSC
PDCON
SYSRLS
C167
New Bit comparing to V1.1
Moved Bit comparing to V1.1
Power Management
Microcontrollers
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Flexible Peripheral Management
Features
C161
 Peripherals organized in groups with seperate clock
drivers
Interface Clock Driver (ICD):
ASC0, SSC, WDT,
Interrupt Detection
Peripheral Clock Driver (PCD):
all other Peripherals,
Interrupt Controller,
Ports
RTC Clock Driver (RCD): Real Time Clock
 Disabling of Peripherals
PCD including all connected Peripherals can be disabled
Each Peripheral can be disabled individually
All registers are visible for read and write access while a
peripheral is disabled individually
Peripheral continues operation after re-enabling
C163
-
C164
C165
C166
C167
-
Power Management
Microcontrollers
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Flexible Peripheral Management
Overview: C161RI
CLK
CLK
IDLE
EN
CLK
SW
EN
CPU
Clock Driver
C161
CPU
C163
CLK
Peripheral
Clock Driver
MEM
Peripherals
CLK
SW
EN
C164
C165
ADC
C166
CLK
fCPU
CLK
SW
Interface
Clock Driver
CLK
SW
CLK
CLK
SW
New
Modified
Power Management
EN
CLK
SW
EN
EN
CLK
Int.
Detection
ASC
SSC
EN
CLK
SW
EN
CLK
GPT1
C167
GPT2
I2C
Ports
CLK Interrupt
Controller
WDT
Microcontrollers
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Flexible Peripheral Management
Overview: C164CI
CLK
CLK
IDLE
EN
CLK
SW
EN
CPU
Clock Driver
C161
CPU
C163
CLK
Peripheral
Clock Driver
MEM
Peripherals
CLK
SW
EN
C164
C165
ADC
C166
CLK
fCPU
CLK
SW
Interface
Clock Driver
CLK
SW
CLK
CLK
SW
New
Modified
Power Management
EN
CLK
SW
EN
EN
CLK
Int.
Detection
ASC
SSC
WDT
EN
CLK
SW
EN
CLK
SW
EN
CLK
GPT1
C167
CAP
COM2
CAP
COM6
CAN
Ports
CLK Interrupt
Controller
Microcontrollers
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Flexible Peripheral Management
Register Definition
C161
C163
C164
SYSCON3
PCD
DIS
CAN2 CAN1
DIS
DIS
Flexible Peripheral Management
SSP
DIS
I2C
DIS
-
PWM
DIS
CC6
DIS
CC2
DIS
CC1
DIS
-
GPT2 GPT1
DIS
DIS
SSC
DIS
ASC0
DIS
ADC
DIS
C165
C166
C167
New Bit comparing to V1.1
Moved Bit comparing to V1.1
Power Management
Microcontrollers
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Real Time Clock (RTC)
Features
C161
 Counts Time Ticks
 Time Ticks are defined by
external oscillator frequency divided by 32
fixed prescaler (8:1)
programmable prescaler (trim register)
 Cyclic time based interrupt
Cycle time can be adjusted via reload register (trim
register)
Interrupt request shared with PLL interrupt
 Additional Function
RTC register and programmable prescaler are
concatenated to built a 48-bit timer unit
C163
-
Power Management
Microcontrollers
C164
C165
C166
C167
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Real Time Clock (RTC)
Programmable Prescaler
C161
C163
T14REL
C164
C165
Reload
Cyclic Interrupt
C166
fRTC
Optional second
32 KHz crystal
Crystal or
external Oscillator
external
Oscillator
C167
8:1
T14
Oscillator Frequency
32 KHz
4 MHz
5 MHz
8 MHz
10 MHz
12 MHz
16 MHz
20 MHz
Power Management
RTCL
Time between two Interrupts
Minimum Time
Maximum Time
0.250 ms
16.3 s
0.064 ms
4.1 s
0.052 ms
3.35 s
0.032 ms
2s
0.026 ms
1.6 s
0.022 ms
1.3 s
0.016 ms
1s
0.013 ms
0.8 s
RTCH
Possible Time Base RTC
0.1 s
1s
1s
1s
1s
1s
1s
0.1 s
Microcontrollers
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Real Time Clock
Interrupt Sharing
C161
C163
C164
ISNC
Interrupt Sub Node Control
C165
C166
-
-
-
-
-
-
-
-
-
-
-
-
PLL
IE
PLL
IR
RTC
IE
RTC
IR
C167
New Bit comparing to V1.1
Moved Bit comparing to V1.1
Power Management
Microcontrollers
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Power Consumption
Overview
Power Consumption
Power Consumption
C161
C163
Active Mode
Flexible
Peripheral
Management
Active Mode and disabled Peripherals
Idle Mode
Flexible
Peripheral
Management
Idle Mode and disabled Peripherals
Power Down Mode
Ports: ON
Power Down Mode
Ports: OFF RTC / OSC: ON
Power Down Mode
Ports: ON
Power Down Mode
Ports: OFF RTC / OSC: OFF
C164
Active or Idle Mode
S
L
O
W
C165
C166
C167
Existing
Features
New Features
D
O
W
N
RTC / OSC: ON
Active or Idle Mode
RTC / OSC: OFF
Power Management
Microcontrollers
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SYSCON2/3 Access Procedure
State Machine
C161
C163
C164
Step SYSRLS Instruction
0000b
1
1001b BFLDL, OR, ORB, XOR, XORB
2
0011b MOV, MOVB, MOVBS, MOVBZ
3
0111b BSET, BMOV, BMOVN, BOR, BXOR
4
Free access to SYSCON2 and SYSCON3
0000b
C165
C166
C167
Note:
This sequence can be executed in an ATOMIC sequence only!
Power Management
Microcontrollers
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SYSCON2/3 Access Procedure
Programming Example
C161
EXTR
BFLDL
#1
SYSCON2, #0Fh, #00h
ESFR access
set SYSRLS to 0000b
C163
C164
C165
EXTR
BFLDL
MOV
BSET
#4
SYSCON2, #0Fh, #09h
SYSCON2, #0003h
SYSCON2.2
ESFR access
set SYSRLS to 1001b
set SYSRLS to 0011b
set SYSRLS to 0111b
C166
C167
access to SYSCON2 / SYSCON3 enabled; e.g.:
BFLDH
SYSCON2, #03h, #02h
set CLKCON to 10b
=> switch to SDD clock
=> disable PLL (if implemented)
Power Management
Microcontrollers
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Overview Port Structure
C161
 The Port lines provide the connection to the external world
77 Port lines on the SAB 80C166
111 Port lines on the C167
77 Port lines on the C165/C163
59 Port lines on the C164
64 Port lines on the C161V/K/O
77 Port lines on the C161RI
 All Port lines are individually addressable and all I/0 lines
are independently programmable for input or output
 Each Port line is dedicated to one or more peripheral
functions
 Each Port is protected with fast diodes
 Programmable open drain buffers
P2, 3, 6, 7, 8 on the C167
P3, 8 on the C164
-
C163
C164
C165
C166
C167
-
Ports
Microcontrollers
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Overview Port Structure
C161
VCC
Alternate
Output
Alternate
Enable
Write
C163
Direction
Register
C164
C165
C166
Internal Bus
Mux
Read
Buffer
Output
Latch
Port
Pin
Buffer
C167
Direction
Mux
Input
Latch
Vss
ESD structure
Clock
Alternate Input
Ports
Microcontrollers
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Overview Port Structure
C161
VCC
Alternate
Output
Alternate
Enable
Write
Direction
Register
C163
Open Drain
Control
C164
C165
C166
Internal Bus
Mux
Read
Buffer
Output
Latch
Port
Pin
Buffer
C167
Direction
Mux
Input
Latch
Vss
ESD structure
Clock
Alternate Input
Ports
Microcontrollers
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The Summary of the C166 Family
C161
C163
ROM /
Flash
C164
Processor -System
C165
CPU
C166
RAM
C167
Interrupt-System
OSC.
Ext.
Bus
Control
X-Bus
Periphrl.
USART
ADC
GPTs
PEC
WDT
CAPCOM
Sync Communication
PWM
Peripheral-System
PORTS
Summary
Microcontrollers
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Processor System
C161
 High Computational Power: min 80ns Instruction Cycle
Time
Fast algorithms (short sample times for closed loop control)
Fast task execution
 Control Oriented Instruction Set
Boolean processing / bit-handling and processing
Task switch / power saving
 General Purpose Register Oriented Architecture
Managing of multiple quasi-parallel tasks
 Powerful Addressing Capabilities
Large address range and powerful addressing modes
(HLL)
 On-chip RAM, OTP/ROM/Flash
For very fast Memory Access
In-System reprogrammable Flash Memory
one-time programmable ROM
C163
-
C164
C165
C166
C167
-
Summary
Microcontrollers
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Interrupt System
C161
 Extremely Short Interrupt Response Time
of typically min. 320ns
Interrupt execution in small time segments
Ensures highest real-time performance
 Comprehensive Prioritization Scheme
Easy scheduling of complex real-time systems by using up
to 64 Priority levels (4 groups within 16 levels)
 CPU-Independent Interrupt Service via Peripheral Events
Controller (PEC)
Off-loads the CPU from simple but frequent interruptservices
Interrupt-driven “DMA-like” data transfer, without task
switch of CPU
Makes peripheral data transfers independent
of running CPU routine
C163
-
C164
C165
C166
C167
-
Summary
Microcontrollers
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Peripheral System
C161
 Multi-functional Timer/Counter Units (up to 5 Timers /
Counters) with Complex Concatenation Possible
 Comprehensive up tp 32 Channel Capture/Compare Unit
with up to 4 Allocatable Time-Bases
 Capture/Compare unit (CAPCOM6)
for flexible PWM Signal Generation
 4 high resolution PWM channels
 up to 10-bit Multi-Functional A/D-Converter for Fast Data
Acquisition in Control Systems
Summary
Microcontrollers
C163
C164
C165
C166
C167
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Peripheral System
C161
 Bi-directional, Protected and Individually Programmable
External Port-Lines
 Serial Communication Interfaces
Standard asynchronous communication
Fast synchronous communication in master- & slave-mode
(SPI)
 Easy Adaptation to Special Application or Customer
Requirements via Internal X-BUS Architecture
CAN-Bus, Profibus, SSP, etc.
 flexible Power Management
C163
C164
-
C165
C166
C167
-
Summary
Microcontrollers
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2-chip Emulation Technology
C161
 One Bondout chip supports emulation of all related
derivatives, new or existing (i.e. C167, C165, C163, C161)
 New X-Peripherals (XPERs) are emulated using the
standard chip
 In emulation mode the standard IC is sleeping and only the
XPER is active. The Bondout chip has full access to the
XPER over a particular port
 No need for Bondout redesign
 User has full emulation control over the XPER without any
intrusion of real-time
 Full access to target system is maintained
 Supported by all major tool manufacturers
Development Tools
Microcontrollers
C163
C164
C165
C166
C167
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2-chip Emulation Technology
C161
to User Application
C163
C164
Port0
to User
Application
X-Bus
XPER-Interrupts
XPER
I/O
P
O
R
T
Port1
Bus Contr.
BUS
External Bus Interface
X-Bus
CS#
RAM
RAM
BUS
CPU
CORE
Standard
chip
XPER
C165
Bondout
chip
RAM
P6
Port4
P6
External Bus Interface
X-Bus
RAM
Port0
Port4
Port1
ROM
BUS
C166
P
O
R
T
C167
Sim.
ROM
P-Bus
Standard Peripherals & I/O
Bus Contr.
CPU
CORE
GPT
ROM
BUS
ROM /
FLASH
CAPCOM
...
I/O
to User Application
P-Bus
Standard Peripherals & I/O
GPT
CAPCOM
...
I/O
Development Tools
Microcontrollers
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Development Tools are a constant factor
of success for Siemens Microcontrollers...
C161
C163
C164
C165
C166
C167
Development Tools
Directory
...just as Siemens Microcontrollers are a constant
factor of success for the products they are designed into!
Development Tools
Microcontrollers
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Major Tool Partners
Emulators
Compilers, Assemblers CAN/FUZZY
MicroFuzzy
KEIL i+ME
Software
stzp INFORM
HIGHTEC
TASKING
Evaluation Boards
pls PHYTEC
ertec KEIL
Logic Analyzers
HEWLETT
dli PACKARD
C161
KONTRON ELEKTRONIK
hitex
LAUTERBACH
C164
YOKOGAWA
C165
C166
Sockets / Adapters
Yamaichi
C163
C167
ET
EMULATION TECHNOLOGY, INC.
Tektronix
RIGEL Software
HIGHTEC
RTOS
WindRiver
Simulators
Debuggers
hitex KEIL
Systems
KEI
Software
KEIL pls
CM
TASKING Software
Flash Programmers L
tecsi X
Software
TASKING
CEIBO pls
HIGHTEC
Company
hitex ertec
Development Tools
Microcontrollers
HL MC AT, lehmann
16x_all.ppt
13.03.2016, 23:14
27 - 242
Applications for the C166 Family
Processor -System
ROM /
Flash
CPU
Interrupt-System PEC
OSC.
Ext.
Bus
Control
PORTS
X-Bus
Periphrl.
RAM
C161
WDT
C163
GPTs
USART
CAPCOM
ADC Sync Communication PWM
C164
Peripheral-System
C165
C166
C167
Automotive
• Engine
Management
• Transmission
Control
Industrial
Control
Consumer
• Robotics
• DVD / CD-ROM
• PLC’s
• TV / Monitor
• Servo-Drives
• VCR / Sat
Receiver
• ABS/ASK
• Motor Control
• Active
Suspension
• Power-Inverters
• Machine-Tool
Control (CNC)
C166 Family
• Set Top Box
• Games
• Video
Surveillance
Telecom/
Datacom
EDP
• Communication
Boards (LAN)
• Hard Disk
Drives
• Modems
• Tape Drives
• PBX
• Printers
• Mobile
Communication
• Scanners
• Digital Copiers
• FAX Machines
Microcontrollers
HL MC AT, lehmann
16x_all.ppt
13.03.2016, 23:14
28 - 243