Backplane Design
and Optimization Using
28nm FPGAs
Technology Roadshow 2011
© 2011 Altera Corporation - Public
Agenda

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Backplane Challenges
28-nm Transceiver Architecture & Signal Integrity
Features
Simulation Tools, Models and Flows
10GBASE-KR Backplane Design Example
Backplane Solutions
Summary
© 2011 Altera Corporation - Public
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10+ Gbps Backplane Design
Challenges
© 2011 Altera Corporation - Public
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Backplane Applications

Enterprise switching





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Line card and switch fabric
Core switch
Aggregation
Cross-bar applications
Shared memory architecture
Access boxes
 DSLAM, PON
 T1, E1, cable


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Proprietary backplanes/midplanes
Time-slot interchange (TSI)
Transport
 Next-generation Ethernet switching
 Types of transport
 ROADM
 OTN WDM
 MSPP

Broadcast switching
 Serial digital interface (SDI) aggregation
© 2011 Altera Corporation - Public
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10GBASE-KR Backplane Electrical

TX
 Eye mask

Channel
 Channel description
 Insertion loss
 Return loss

RX
 Jitter Tolerance
 Return loss

System
 BER =< 1E-12
© 2011 Altera Corporation - Public
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28-nm Transceiver
Architecture & Signal
Integrity Features
© 2011 Altera Corporation - Public
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Stratix V Transceiver Block Architecture
additional TX clock source
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Analog PLL-based CDR per
receive channel
Advanced TX and receiver (RX)
equalization for 14.1-Gbps
backplane support
 Including 10GBASE-KR


Optimized PCS / Hard IP for
multiple protocol support
Additional 28G transceivers
© 2011 Altera Corporation - Public
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Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Hard PCS
Clock networks
 More LC oscillators
 Programmable LC tuning range
 Multipurpose fractional PLLs (fPLLs) for
Hard PCS
LC Transmit PLLs

Embedded HardCopy Block)

Up to 66 full-duplex transceivers
at 14.1 Gbps
Scalability and flexibility with
continuous bank of transceivers with
complete PMA and PCS per channel
Multiple transmitter (TX) PLL sources
Fractional PLLs (fPLL)

Transceiver PMA
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
.
.
.
.
Dedicated Circuitry for Advanced Signal Conditioning
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LC PLL for sub-ps transmit jitter
Analog-PLL CDR for improved jitter tolerance
4-tap pre-emphasis and linear equalization for 14.1-Gbps backplane applications
Advanced signal conditioning including 5-tap DFE and ADCE
 Mitigate backplane losses and crosstalk

Targeted 10GBASE-KR and CEI-11G electricals
LC TX PLL
Rx
Linear
Equalizer
+
Analog CDR

-
ADCE
TX
RX
PreEmphasis
Backplane Channel:
Including 10GBASE-KR
© 2011 Altera Corporation - Public
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DFE
EQ
CDR
Arria V Transceiver Architecture
Scalability and flexibility through a
continuous bank of transceivers

Complete physical medium attachment
(PMA)+ physical coding sublayer (PCS) per
channel


Unused channels can be utilized as
clock multiplier unit (CMU) PLLs
Flexible transmit clock sources enable up to
24 independent data rates in a single device
Transmit Clock Source
Maximum Number
Data Range (Gbps)
CMU PLL
12
0.6 – 6.375
fPLL
12
0.6 – 3.75
CMU PLL
6
0.6 – 10.3125
.
.
.
.
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Hard PCS
Clock Networks

Transceiver PMA
Transceiver PMA
Hard PCS
Transceiver PMA
Hard PCS
Transceiver PMA
.
.
.
.
Arria V FPGAs Offer Up to 36 Full-Duplex Transceiver
Channels with PCS and PMA
© 2011 Altera Corporation - Public
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Altera 28nm Transceiver Summary
Transceiver SI Feature
Stratix V
Transmit Equalization
(pre-emphasis)
Main tap
Main tap, 2 post tap, 1 pre-tap
Receive Equalization
(Continuous Time Linear
Equalization)
1 stage (4 dB)
around 6.25 Gbps
4 stage (20dB)
Programmable bandwidth up to 12.5
Gbps
Adaptive Dispersion
Compensation Engine (ADCE)
N/A
Decision Feedback
Equalization (DFE)
N/A
5-tap with auto adaption
Backplane Support
Up to 30” at 6.375 Gbps
Up to 40” at 14.1 Gbps
Optical Module Support
SFP+
Short Reach (SR)
Long Reach (LR) requires external EDC
chip
Full compliance (SR, LR and LRM) for
SFP+
EyeQ
N/A
Vertical & horizontal eye (12.5 Gbps)
Serial bit checker for unknown data
pattern
On-Die Instrumentation
Jitter Injection / Stress
N/A
Jitter modulation of transmitter &
receiver
© 2011 Altera Corporation - Public
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Arria V
Up to 12.5 Gbps
Simulation Tools, Models
and Flows
© 2011 Altera Corporation - Public
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Transceiver Simulation Models

Altera’s suite of transceiver
design tools
 Evaluate performance in custom
application
 Run “What if” simulations for
early analysis
 Create design constraints in
layout and design
 Run in-system verification for
board bring-up and live debug


HSPICE full circuit models
IBIS-AMI behavioral models
 Fast simulation
 Analog and algorithmic description
of all major transceiver components
 Analysis of millions of bits
© 2011 Altera Corporation - Public
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PELE – Pre-emphasis/Equal Link Estimator
TX
model
RX
model
Customer provided
S-parameters
PELE
Coefficients
Backplane



Optimize the equalization coefficients for the transceiver
Early estimate of link performance
Inputs: Channel / settings
© 2011 Altera Corporation - Public
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Simulation Model Comparison
HSPICE
IBIS-AMI
PELE
High
High/medium
Medium
Hours to days
Minutes to hours
Minutes
Corner model availability
Full
Full
TT/NormV/85C
Flexible data inputs
Yes
Yes
PRBS-7/10
Link to other devices
Yes
Yes
No
EDA tool requirement
Synopsys HSPICE
Yes, independent
NA
64-bit Linux,
8 GB memory
EDA-tool
dependent
32-bit system,
1 GB memory
Accuracy
Time consumption
Simulation platform
requirement
© 2011 Altera Corporation - Public
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HST Jitter and BER Estimator

Custom characterization
 Quickly and accurately estimate
system link reliability (BER)
 Utilize customer-specific channel
(S-Parameter)
 Run statistical analysis using
characterization data

Margin analysis
 TX
 RX
 Channel

Reduction of system cost
 Cost-effective alternatives for the
same system performance
Currently Available
for Stratix IV and V FPGAs
© 2011 Altera Corporation - Public
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Link Simulation Flow – Early Stage

Use generic S-parameter file




From backplane model provider, EDA
simulation tool extraction or VNA
measurement
Use PELE/JBE to see if the
selected device compensates
channel losses using preemphasis or equalization, or both
Check to see if the eye opening
meets the protocol requirements
or device requirements
Proceed to device selection
© 2011 Altera Corporation - Public
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Generic S-Parameters
(model provider/fab)
PELE/HST JBE
No
Eye Mask
Requirements
Yes
Device Selection
(TX and RX)
Link Simulation Flow – Design Phase


Device selection
Channel design




Extract Backplane
S-Parameters
Further analysis
Pre-emphasis and/or
equalization settings selection
Fine tune/validate settings



Channel Design
HSPICE
IBIS-AMI behavioral models
Use JBE to include the
statistical data
Use the transceiver toolkit to
verify and debug
PELE
EDA Simulations
(Fine-tune/Validate Settings)
Yes
HST JBE
Include Statistical
Data (RJ)?
No
Eye Mask
Requirements
Yes
Board Design
Use Transceiver Toolkit
Debug/Verification
© 2011 Altera Corporation - Public
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No
10GBASE-KR Backplane
Design Example
© 2011 Altera Corporation - Public
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PELE Configuration

Standalone mathematical tool
 Requires MATLAB run-time library

Inputs
 Data rate
 VOD
 Backplane
Optimization
Method
TX
Pre-emphasis
RX CTLE
1
Manual
Auto
2
Auto
Auto
3
Auto
Manual
4
Manual
Manual
Optimization Method
DFE
 TX pre-emphasis setting
1
Disable
 RX equalization setting
2
Auto
3
Manual
 AC gain (CTLE)
 DC gain
Auto/Manual
Mode
 DFE

Outputs
 Deterministic eye opening at TX, RX,
and post equalization
 Optimal pre-emphasis and
equalization setting
© 2011 Altera Corporation - Public
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Backplane (*.s4p)
Data Rate
VOD
Pre-emphasis
Stratix V GX
PELE Tool
Equalization
Eye Opening
PELE Configuration

Standalone mathematical tool
 Requires MATLAB run-time library

Inputs
 Data rate: 10.3125 Gbps
 VOD : 1000 mV
 Backplane:
Optimization
Method
TX
Pre-emphasis
RX CTLE
1
Manual
Auto
2
Auto
Auto
3
Auto
Manual
4
Manual
Manual
Optimization Method
DFE
1
Disable
2
Auto
3
Manual
“30inches_2connectors_backplane.s4p”
 TX pre-emphasis setting: Auto
 RX equalization setting
 AC gain (CTLE) : Auto
 DC gain: 4 (0-8 dB)
 DFE: Auto

Outputs
 Deterministic eye opening at TX, RX,
and post equalization
 Optimal pre-emphasis and
equalization setting
© 2011 Altera Corporation - Public
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Auto/Manual
Mode
Backplane (*.s4p)
Data Rate
VOD
Pre-emphasis
Stratix V GX
PELE Tool
Equalization
Eye Opening
PELE Simulation (30” link @10.3125G)
Rx
Linear
Equalizer
+

-
TX
© 2011 Altera Corporation - Public
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ADCE
DFE
PELE Simulation Output


Refer to Stratix V user guide on PELE instructions
PELE output results:
Starting point for
optional simulation
analysis
0.75 UI = deterministic eye opening
1- 0.75 UI = 0.25 UI = non compensated jitter
© 2011 Altera Corporation - Public
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10GBASE KR Requirements
1.
TX Jitter Characteristics


2.
Channel Characteristics

3.

Eye width > 0.6 UI
Eye height > 100mV
RX Jitter Tolerance Requirements

5.
Insertion loss < 25dB @ 5.15625 GHz
Altera RX Requirements – Post EQ

4.
RJ < 0.15 UI, DJ < 0.15, DCD < 0.035
Overall TJTX < 0.28 UI = 27ps @ 10.3125 Gbps
SJ > 0.115, RJ > 0.13, DCD > 0.130
System Performance

BER = 1E-12
1
3
2
RX
TX
10GBASE-KR channel
5
© 2011 Altera Corporation - Public
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EQ
4
CDR
Transmitter

10GBASE-KR transmit jitter
requirements

RJ < 0.15 UI, DJ < 0.15, DCD < 0.035
 Overall TJTX < 0.28 UI = 27ps @ 10.3125
Gbps

PELE Eye opening @ TX output

TX TJ = 1- Eye opening at TX output
 = 1-0.92313 = 0.07687 UI
 < 0.185 UI (DJ + DCD)
© 2011 Altera Corporation - Public
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TX
RX
Backplane Channel

TX
Channel:

Length: 30”
 Connectors: 2

Loss @ 5.15 GHz:

Approx -20dB
10GBASE-KR Insertion loss spec: < 25dB @ 5.15625 GHz
© 2011 Altera Corporation - Public
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RX
Receiver

RX Jitter Tolerance Requirements
o
o

RX
TX
SJ > 0.115, RJ > 0.13, DCD > 0.130
Altera data sheet and characterization report
Altera RX Requirements at 10.3125Gbps
o
Deterministic eye opening
X1_eye
Above 5 Gbps with DFE:
X1_eye = 0.5 UI
X2_eye = 0.7 UI
Y_eye = 100 mV
Y_eye
Above 5 Gbps without DFE:
X1_eye = 0.4 UI
X2_eye = 0.6 UI
Y_eye = 100 mV
X2_eye
CTLE Eye Height
CTLE Eye Width
DFE Eye Height
DFE Eye Width
Requirement
100 mV
0.60 UI
100 mV
0.70 UI
Actual
326 mV
0.74 UI
352 mV
0.75 UI
© 2011 Altera Corporation - Public
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System Performance


TX
RX
PELE analysis is a deterministic simulator
Jitter and BER Estimator (JBE) incorporates
random jitter components of transmitter and
receiver through characterized data
 Early version (EAP) of Stratix V JBE is based on Stratix IV data
 Final version will incorporate actual silicon measurement

JBE will determine Bit Error Ratio performance of
link
© 2011 Altera Corporation - Public
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Jitter and BER Estimator Tool
© 2011 Altera Corporation - Public
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JBE Configuration Steps
1.
Setup global
parameters



2.
Target BER
Data Rate (Gbps)
Test Pattern
Link configuration


Analysis mode
selection/eye
mask setup
Options: Full
Link, TX, RX
© 2011 Altera Corporation - Public
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Step1
Step 2
JBE Configuration Steps
3.
4.
5.
Configure TX
settings
Configure RX
settings
Input the nonequalized
channel DJ
from PELE
simulation
output


“1 – Eye opening”
post equalization
May add margin
to this number to
account for
cross-talk
© 2011 Altera Corporation - Public
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Step 3
Step 4
Step 5
Link Analysis: Full Link Mode


Full link simulation shows that the link meets the
BER target of 10-15
Margin analysis
© 2011 Altera Corporation - Public
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Backplane Solutions
© 2011 Altera Corporation - Public
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10GBASE-KR Backplane PCS




Auto-negotiation
Link Training
Forward Error
Correction
MoreThanIP offers a
complete PCS solution
for 10GBASE-KR
applications for
Stratix V
© 2011 Altera Corporation - Public
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Connectors


Major component of link reliability
Evaluation of link includes
 Insertion Loss
 Return Loss
 Crosstalk


Advanced EDA simulation
tools
Hardware analysis
© 2011 Altera Corporation - Public
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Stratix V 5-Tap Decision Feedback Equalizer
From linear
equalizer
Rx
Linear
Equalizer
+
_
To CDR
Z-1

C1
-
Z-1
ADCE
DFE
C2
Z-1
C3
Z-1




Improves signal-noise-ratio (SNR)
With CTLE, addresses
pre-cursor and post-cursor ISI
Mitigates the effects of crosstalk
Automatically adapts to PVT conditions
© 2011 Altera Corporation - Public
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C4
Z-1
C5
Stratix V FPGA EyeQ Eye Viewer
View receiver signal margin with Altera’s EyeQ® eye viewer
Complete vertical and horizontal reconstruction of eye opening
Uninterrupted data path for live debug capability



EyeQ®
PreEmphasis
EQ
CDR
Lossy medium
Rx
Tx
Minimize board bring up / debug time with
Dynamic reconfiguration and EyeQ
© 2011 Altera Corporation - Public
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Summary



Link simulation flow enabled through Altera
simulation tools and models
10GBASE-KR backplane system performance
achieved
Altera offers complete solution for 10+ Gbps
backplane analysis and design
Stratix V FPGAs offer the optimum
platform for 10Gbps+ backplane systems
© 2011 Altera Corporation - Public
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Thank You
Backplane Design and
Optimization Using 28-nm FPGAs
© 2011 Altera Corporation - Public
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