FPGAs for HIL and Engine Simulation
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Field-Programmable Gate Array (FPGA)
Memory Blocks
Store data sets or values in user defined RAM
Configurable Logic Blocks (CLBs)
Implement logic using flip-flops and LUTs
Multipliers and DSPs
Implement signal processing using
multiplier and multiplier-accumulate circuitry
Programmable Interconnects
Route signals through the FPGA matrix
I/O Blocks
Directly access digital and analog I/O
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FPGAs - Why Are They Useful?
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Hard determinism – Realistic simulation timing, local intelligence
•
Off-load processing – Achieve real-time performance with more complex
simulations
•
Custom Hardware – Create custom H/W instruments
•
Reconfigurable hardware personalities – Adapt to multiple UUT types and
changing UUT interfaces
•
Industry standard technology – Off the shelf chips used for specific
applications get COTS benefits like Moore’s Law
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FPGAs in HIL Test Systems
IO
µP
Test Application
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Signal
Conditioning
4
UUT
FPGAs in HIL Test Systems
µP
Test Application
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FPGA
IO
FPGA
Personality
Signal
Conditioning
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UUT
FPGAs in HIL Test Systems
NI Reconfigurable I/O (RIO) Platform
µP
Test Application
FPGA
IO
FPGA
Personality
Signal
Conditioning
Test Application
Interfaces
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Hardware I/O
Interfaces
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UUT
Mechanical Systems – Engine Sensor Simulation
RPMs
µP
ni.com
FPGA
I/O
(Engine
Simulation)
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Crank
UUT
Free Engine Simulation Toolkit
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Fully featured for Engine Control Unit (ECU) testing
FPGA-based sensor simulation and measurement for ultra-fast pin-to-pin
response time & lifetime upgradability
Seamless integration with NI FPGA hardware and NI VeriStand
Scalable design for simple to complex ECU testing
Suitable for open loop or closed loop
Open source architecture customizable with LabVIEW FPGA
•
Supports any NI FPGA device
•
Deploy with NI VeriStand 2013 or later
Design with LabVIEW 2013 or later
•
•
•
•
•
•
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Engine Simulation Toolkit Building Blocks
CPU
FPGA
ECU
Event
ECU
ECUEvent
Event
Waveform
Waveform
Waveform
Capture
Capture
Capture
Angle
Processing
Unit (APU)
Digital Pattern
Digital
Pattern
Digital
Pattern
Generation
Generation
Generation
(i.e.
Hall)
Directional
Directional
Directional
Sensor
Sensor
Sensor
Simulation
Simulation
Simulation
Analog
Replay
Analog
AnalogData
Data
(i.e.
VR)
Replay
Replay
Knock
Sensor
Knock
KnockSensor
Sensor
Simulation
Simulation
Simulation
ECU Event
ECU
Event
ECU
Event
Timing
Timing
Timing
Capture
Capture
Capture
(Inject
& Ignite)
Speed, Crank Angle, Cycle Angle
Engine Simulation Toolkit Roadmap
Item
Angle Processing Unit
(APU)
Old AES Library
2 and 4 stroke engines
Digital Pattern
Generation
N-M Teeth Generation
Custom Edges Generation
Analog Replay
Play back any file by angle
ECU Event
Measurement
Digital input timing capture
of single event per cycle
Knock Sensor
N/A
Directional Speed
Sensor
N/A
FPGA space utilization
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Baseline
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Engine Simulation Toolkit Roadmap
Item
Old AES Library
Engine Simulation
Toolkit
2 and 4 stroke engines
Improved usability
Digital Pattern
Generation
N-M Teeth Generation
Custom Edges Generation
Improved usability
Analog Replay
Play back any file by angle
Improved usability
ECU Event
Measurement
Digital input timing capture
of single event per cycle
Windowing, multi-event
per cycle, error detection,
& improved usability
N/A
Pseudorandom,
amplitude & probability
per cylinder.
N/A
Different forward/reverse
digital pulse width
triggered at tooth centers
Baseline
3x Reduction
Angle Processing Unit
(APU)
Knock Sensor
Directional Speed
Sensor
FPGA space utilization
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Engine Simulation Toolkit Roadmap
Item
Old AES Library
Engine Simulation
Toolkit
2 and 4 stroke engines
Improved usability
Digital Pattern
Generation
N-M Teeth Generation
Custom Edges Generation
Improved usability
Analog Replay
Play back any file by angle
Improved usability
ECU Event
Measurement
Digital input timing capture
of single event per cycle
Windowing, multi-event
per cycle, error detection,
& improved usability
N/A
Pseudorandom,
amplitude & probability
per cylinder.
N/A
Different forward/reverse
digital pulse width
triggered at tooth centers
Baseline
3x Reduction
Angle Processing Unit
(APU)
Knock Sensor
Directional Speed
Sensor
FPGA space utilization
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Q4 2014
Analog input thresholding
and waveform capture
Space and performance comparison
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7854R
PXIe 8130
PXIe 1082
AES Library
1 APU
1 N-M generation
4 Fully Custom generation
1 Analog Replay
12 Event Capture
Engine Simulation Toolkit
1 APU
5 Digital Pattern Generation
1 Analog Replay
12 Event Capture
Slices
6,703 of 17,280 (38.8%)
3,159 of 17,280 (18.3%)
Registers
14,882 of 69,120 (21.5%)
5,912 of 69,120 (8.6%)
LUTs
19,702 of 69,120 (28.5%)
8,239 of 69,120 (11.9%)
DSP
24 of 64 (37.5%)
2 of 64 (3.1%)
BRAM
21 of 128 (37.5%)
13 of 128 (10.2%)
40 Mhz Max
42.69
65.35
Compile time
37 minutes
21.7 minutes
RT Loop
Duration
305 to 335 uS
138 to 186 uS w/ RIO 13.1
132 to 165 uS w/ RIO 15.0
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Reconfigurable I/O Interfaces
V6 ECU
µP
FPGA
I/O
Multiple UUT types
Evolution of UUT interface
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V8 ECU
NI VeriStand System Explorer
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Analog Replay
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Analog Replay Configuration
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Analog Replay: Voltage Scaling Configuration
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Example FPGA: APU + 1 Analog Replay
APU
Load Look Up Table
Play Look Up Table
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Example FPGA : APU + 2 Analog Replay
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Digital Pattern Generation
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Digital Pattern Generation of Two Cams and a Crank
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Digital Pattern Generation Design
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Digital Pattern Generation supports complex patterns easily
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Example FPGA: 2 Digital Pattern Generations
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Knock Sensor Simulation
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Knock Sensor Simulation Configuration
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Example FPGA: Knock Sensor Simulation Loop
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Knock Sensor with 4 Cylinders
(Probably had been set to 100% with 4 different amplitudes)
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Directional Speed Sensor Simulation
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Directional Speed Sensor
•
•
Generates pulses of different widths, depending on forward (Tf) or reverse
(Tr) rotation, when passing tooth centers
Pulse slightly delayed from center by variable microseconds (Td)
Directional sensor: forward
Directional sensor: reverse
Crank
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Directional Speed Sensor
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Example FPGA: 1 Directional Speed Sensor
Load Tooth Centers
Look Up Table
ni.com
From APU
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ECU Event Capture
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Example FPGA : Typical MPI Injection Measurement (1 x
Cylinder)
Event measurement block outputs:
Digital Input
•
•
•
•
Event measurement block
settings:
• Angle Max (degrees)
• Angle Min (degrees)
• Active High (Boolean)
• Time based ‘stuck active’ timeout
ni.com
(milliseconds)
Stuck active (Boolean)
Window all active (Boolean)
Window orphan start edge (Boolean)
Window orphan end edge (Boolean)
Event capture block outputs:
• Event Present (Boolean)
• Start Angle (degrees)
• End Angle (degrees)
• Duration (milliseconds)
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Example FPGA : Typical GDI or Diesel Injection Measurement
(1 x Cylinder)
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Example FPGA : Typical GDI or Diesel Injection Measurement
(2 x Cylinder)
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Example FPGA : Customize Windowing Per Event
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ECU Event Capture Configuration
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ECU Event Capture Configuration
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Generation and measurement of two events neither wrapping 0
and window does not wrap 0
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Generation of one event wrapping zero and one not wrapping
zero; window wraps zero and measures both
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Start of a full cycle event within window, causing an orphan
start edge and a stuck active flag
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End of full cycle event within next window, causing an orphan
end edge
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Future* FPGA : Typical GDI or Diesel Injection Timing &
Waveform Measurement
Analog Input
Timing Measurement and Capture
Thresholding
Waveform capture
*Q4 2014
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Case Study
Application
Creating a flexible HIL test system
with I/O interfaces that require
custom timing and synchronization
schemes not easily implementable
with traditional hardware.
NI Products
LabVIEW FPGA Module, PXI,
and Reconfigurable I/O (RIO)
hardware
"With LabVIEW FPGA and RIO
hardware we were able to quickly and
efficiently design custom analog and
digital interfaces for our HIL test
system.”
Key Benefit
Gaining the ability to efficiently
create custom hardware interfaces
that can be reconfigured after
deployment to adapt to different
ECU types and changes to ECU
interfaces.
ni.com
– Roy Kranz, Wineman Technology Inc.
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Summary
•
FPGA-based I/O interfaces are used to expand the capabilities and
performance of HIL test systems.
ni.com
•
Hard determinism – Realistic simulation timing and local intelligence with 25 ns
resolution
•
Off-load processing – Achieve real-time performance with more complex simulations
•
Custom Hardware – Create custom H/W instruments
•
Industry standard technology – Off the shelf chips used for specific applications get
COTS benefits
•
Reconfigurable hardware personalities – Test multiple UUT types and adapt to
changes in UUT interfaces without changing hardware
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