Technion - Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
‫ מכון טכנולוגי לישראל‬- ‫הטכניון‬
‫הפקולטה להנדסת חשמל‬
‫המעבדה למערכות ספרתיות מהירות‬
Full sniffer system for
PCIe
Preliminary Design Review
Performed by: Omer Blecher , Roy Fridman
Instructor: Boaz Mizrachi
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Agenda
•Main Goal
•Motivation
•Multi level level block diagram
(sub level goals and risk assessment)
•Data flow
•Learning stages
•Dependencies
•Schedule
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Main Goal
• Providing a fully operational Sniffer who is able
to connect on a PCIe bus ,stream a PCIe packet to
a analyzer and perform a complete packet
analysis of the signals in an analysis and control
PC .
• General purpose of project utilizing/modifying
existing components of the system and creating
missing components for full system integration).
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Why creating a sniffer:
• cost effective :
company
Price of analyzer
+/- 58000$
• experiment System available today
works in sterile environment and doesn't
“feel” real PCIe traffic.
+/- 30000$
+/- 30000$
+/- 45000$
•Can be modified and contain features
with educational values
The need for an integration project:
•utilizes already spent/available lab resources
•Verify and modify existing tools
+/- 45000$
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
System overview
PCI-e Card
PC
x1
x1
x1
x1
x1
x1
Sniffing system
x16
x16
x16
x16
PCI-e MB
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
PCI-e Card
?
!
?
!
Vertex II Pro
Sniffer board
PCIe
RS232
?
?
PCIe
!
?
?
PCI EXPRESS x16 link
Block Diagram
RS232
?
PCI-e MB
‫המעבדה למערכות ספרתיות מהירות‬
High speed digital systems laboratory
Data flow
Analysis and
control PC
Sniffer board
RS232
PCIe
RS232
PCIe
PCI EXPRESS x16 link
Vertex II Pro
PCI-e Card
start
PCI-e MB
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Dependencies
So far the two other groups working on the project are in the following
stage:
•
Sniffer board (Roee Mesinger):
1. Current stage - starting layout.
2. Expected result - a board after assembly on 02/05.
3. Date of transfer – 04/06 (after debugging).
• Analyzer core (Danny Volkind and Amir Shmuel):
1. Current stage - finishing simulation in 3 weeks and ready
to start building transmitter.
2. Expected result - basic function tested analyzer on
05/06
3. Date of transfer (if we will fully use the core) - 05/06
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
Learning stages (beginning)
• PCIe protocol (packet analysis)
• PCIe physical data transfer (on the connections
between the system blocks.
• Predecessor work: Analyzer core,TGA,sniffer
board.
• investigating known PCI and PCIe analyzers a
and sniffers and creating a feature list for
feature use .
I.P
I.P
I.P
I.P
High speed digital systems laboratory
‫המעבדה למערכות ספרתיות מהירות‬
schedule
•08/01/06 - Presenting final stage of system characterization
•04/02/06 - 1. Full report on the design/algorithm of analysis and
control PC s/w.
2. Full report on the h/w design/algorithm mostly
analyzer related)
3. Start of Debugging stages of the sniffer board with
Roee Mesinger.
• 01/04/06 – Presenting Part A of the integration project:
1. Full control of all s/w and h/w design and test tools
2. Partly ready chosen architecture of analyzer and
analysis and control PC s/w.
•Schedule also depends on other groups.
•Minimum time spent on project on a weekly base(toghter) – 2 full work days
and 6 hour.