MAC Controller Implementation
Delta Network ASIC Division
Project Manager
Roger Lin
Content
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Project Initialization
System Specification
Data Flow
ASIC Specification
ASIC Block Diagram
Implementation Target
Design Flow
Content
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Interface Definition
MAC Controller Sub-Block
Design Phase
Synthesis Phase
Backend Phase
System Engineering
Project Initialization
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Target : Ethernet Switch
Evolve from Multi-port Bridge
Kapana Network
Market v.s. Technical
Information Re-assembly
– International Showcase
– DataBook
– Standards
Product Hierarchic
Internet
Intranet
Bridge
TP-HUB
Router
Application Trend
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Standalone Computer Process
Database Share Localization
Centralize Information Maintain
Internet Access
Remote Branch Office Handle
E-Commerce
Multi-port Bridge
EEPROM
SRAM
High-End
RISC CPU
SRAM
SRAM
CAM
Serial
Port
MAC Controller
MAC Controller
MAC Controller
MAC Controller
PHY
ChipSet
PHY
ChipSet
PHY
ChipSet
PHY
ChipSet
RJ-45
BNC
RJ-45
RJ-45
System Specification
• Same with Multi-port Bridge
– 802.3 MAC
– 802.1D Bridging
• Switching Technology
– Hardware Forward
– Cut Through/Store and Forward
– Unique Media Access
Media Access Control
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Ethernet/802.3
Token Ring
Token Bus
FDDI
LLC
802.3
10B2
Token
Bus
10B5
Token
Ring
TP
FDDI
Ethernet/802.3
Y
Transmit
Receive
Defer
on ?
Rx
done ?
Y
Send jam
Start Tx
Defer
on ?
Frame
Small ?
(Col)
Increment
attempts
Valid
FCS ?
Y
Y
Tx
done ?
Defer
on ?
Compute
Backoff
Extra bits ?
Y
Valid
Lengh Field ?
Y
Y
Y
Done:
OK
Wait backoff
time
Done:
excessiveColError
Done:
Align Error
Done:
OK
Done:
FCS Error
Done:
Length Error
Y
Recog
addr ?
Y
802.1D Bridging
• Forwarding
– Outgoing Port
• Learning
RELAY
MAC
MAC
PHY
PHY
– Host Location
• Database
– Network Topology
• Spanning Tree
– solve loop
B
B
Ethernet Switch System Block
EEPROM
Low-End
CPU
Serial
Port
SRAM
Switching Fabric
SRAM
MAC
Controller
SRAM
MAC
Controller
SRAM
MAC
Controller
SRAM
MAC
Controller
PHY
ChipSet
PHY
ChipSet
PHY
ChipSet
PHY
ChipSet
RJ-45
BNC
RJ-45
RJ-45
Data Flow
• Multi-port Bridge
– Concentrate on the High-End CPU
– Compute and Move Data by CPU
• Ethernet Switch
– Multiple Channel in Switch Fabric
– Dynamic Connect by Hardware
ASIC Specification
• New MAC Controller
– Major Function of CSMA/CD
– Major Function of Bridging
– Interface with Switch Fabric
• Switch Fabric
– Crossbar
– Share Bus
– Share Memory
New MAC Block Diagram
Memory
Access
Interface
To Switch
Interface
From Switch
Interface
Packet Buffer
Read
Controller
Packet Buffer
Write
Controller
CPU Interface
Controller
Bridging
Function
Controller
Packet Buffer
Write
Controller
Packet Buffer
Read
Controller
802.3
Receive
Controller
802.3
Transmit
Controller
Carrier Handle Controller
ASIC Block Diagram
• Separate MAC Controller Module
– Easy to Re-use/Replace
• Mirror Packet Buffer Controller
– Reduce the Corner Case
• Separate Bridging Controller
– Easy to Upgrade to Layer 3 Operation
Implementation Target
• FPGA v.s. ASIC
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Low Development Cost
Short Time-to-Market
Easy to Debug
Bad Timing Budget
More Effort to Partition
Proprietary “Generic Logic Block”
Difficult to Estimate
Design Flow
Critical point
to Success
HDL Coding
Easy to Maintain,
Re-use and Expand
Functional
Verification
Library Survey
Synthesis
First Step for
Link-to-Layout
FloorPlan
Pre-Simulation
Static Timing Analysis
Layout
Post-Simulation
(STA)
Toggle Rate for
pattern driven,
STA for Synchronous
Design
802.3 Receive Controller
Highlights
• Collision Handle
– Collision Drop
– Late Collision to CPU
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Physical Layer Error Handle - Drop
Runt Frame Handle - to Packet Buffer
Long Frame Handle - to Packet Buffer
Frame Check Sum Error Handle - Drop
802.3 Receive Controller
Highlights
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Alignment Error Handle - Drop
Clock Synchronization
Lose by Packet Alignment
Wire Speed Receive
Interface with Packet Buffer Controller
802.3 Transmit Controller
Highlights
• Collision Handle
– Re-transmit Function
– Skip Transmit Function
• Jam Function
• Backoff Function
– [0, 2ek) where k = min (n, 10)
• Defer Function
802.3 Transmit Controller
Highlights
• Wire Speed Transmit
• Clock Synchronization
Interface Definition
DATA[7:0]
802.3
Receive
Controller
DATA_VALID
DATA_END
DATA_ERR
Packet Buffer
Write
Controller
TXD[7:0]
802.3
Transmit
Controller
TXS[1:0]
TXACK[1:0]
Packet Buffer
Read
Controller
Interface Definition - RX
MII[3:0]
Network Data Payload
DATA[7:0]
DATA_VALID
DATA_END
MII[3:0]
DATA[7:0]
DATA_VALID
DATA_ERR
Network Data Payload
Interface Definition - TX
MII[3:0]
Network Data Payload
TXD[7:0]
TXS[1:0]
TXACK[1:0]
Valid
Valid
Idle
Idle
Valid
Valid
MII[3:0]
End
Idle
Valid
Network Data Payload
TXD[7:0]
TXS[1:0]
TXACK[1:0]
Valid
Valid
Idle
Idle
Valid
Re/Sk
Idle
Idle
RX/TX Block Diagram
To Packet
Buffer
Write Interface
Interface
Command
Decoder
Statistic
Counter
Byte to
Word
Word to
Byte
Phy
Management
FIFO
Clock
Synchronization
Nibble to
Word
MII TX
Controller
Defer
CRC Check
Carrier Handle Controller
Backoff
Design Phase
• Clock Domain Partition
– Meta Stable
• State Machine
– Merely
– Moore
– One-hot
• Combinational
– Product Term
Design Phase
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Naming Rule
Exclusion Logic
Datapath Sharing
Power Consumption
– FlipFlop
– Gated Clock
– State Bit Transition
tx_ctrl tx_ctrl (
dffex8 DFFEx8_1(
.Q(bus1[7:0]),
.txack(txack[1:0]),
.data_shift(data_shift),
.pre_end(pre_end),
.vartest4(vartest4),
.txs(txs[1:0]),
.fifo_full(fifo_full),
.err(err),
.retx(retx),
.montx(montx),
.CP(CP),
.QN(),
.D(txd[7:0]),
.E(data_shift),
.NC(NC),
.CP(CP)
//load 3
.NC(NC)
.D({pre_end, bus1[7:0]}),
.E(data_shift),
.NC(NC),
.CP(CP)
);
tx_write tx_write (
.tx_cmd_write(tx_cmd_write),
.vartest5(vartest5),
.data_shift(data_shift),
.endtag(tx_cmd_data[8]),
.full(fifo_full),
.err(err),
.CP(CP),
.NC(NC)
);
//load 3
//load 8
);
dffex9 DFFEx9_2(
.Q(tx_cmd_data[8:0]),
.QN(),
);
//load 8
assign
assign
vartest4 = {data_shift, stateQ};
txack[1]
txack[0]
pre_end
data_shift
always
= (stateQ == x_start)
//idle
| (stateQ == x_valid)
//valid
| (stateQ == x_err)
//idle
| (stateQ == x_idle),
//idle
= (stateQ == x_start)
| (stateQ == x_err)
//idle
| (stateQ == x_idle)
| (stateQ == x_sktx),
= (txs == 2'b01) & (txack == 2'b10),
= ((txs == 2'b10) | (txs == 2'b01))
& (txack == 2'b10) & (stateQ == x_valid);
@(
txs or
fifo_full or
err or
retx or
montx or
stateQ
)
begin
stateD
case (stateQ)
= stateQ;
x_start
x_valid
// synopsys parallel_case
:
if (txs == 2'b10 & montx & ~err & ~fifo_full)
stateD
= x_valid;
:
if (err)
stateD
= x_err;
else if (txs == 2'b01)
stateD
= x_start;
else if (fifo_full)
stateD
= x_idle;
x_idle
:
if (~fifo_full)
x_err
:
if (retx)
stateD
= x_valid;
stateD
= x_retx;
stateD
= x_sktx;
else if (~retx)
x_retx
x_sktx
default
:
stateD
:
stateD
:
stateD
= x_start;
= x_start;
= x_start;
endcase
end
//----------------------FLIP FLOP AREA-----------------always @(
posedge CP or
negedge NC )
begin
if (~NC)
stateQ[2:0]
= #2 3'h0;
else
stateQ[2:0]
= #2 stateD[2:0];
end
//DFFC_d1 DFF0 (.Q(stateQ[0]), .D(stateD[0]), .CP(CP), .NC(NC));
//DFFC_d1 DFF1 (.Q(stateQ[1]), .D(stateD[1]), .CP(CP), .NC(NC));
//DFFC_d1 DFF2 (.Q(stateQ[2]), .D(stateD[2]), .CP(CP), .NC(NC));
Synthesis Phase
• Strategy
– Bottom Up
– Synthesis - Characterize - Re-synthesis
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Critical Path
Fine Tune Constraint
Register Re-timing
Re-code RTL
Backend Phase
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Floor Plan
ECO ( Engineering Change Order )
Clock Skew
Layout Density
System Engineering
• Test Environment
• Q&A