How The Next Generation Converters Will Help Change
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“What Will You Invent With The Latest Converter Innovations?” Gil Engel Senior Staff Design Engineer Analog Devices High Speed Converter Group January 29, 2014 Introduction • There is a rapid expansion of consumer demand for data services of all types. • Cable service providers – Work to improve video quality from analog to digital to high definition. – Include internet service at higher and higher data rates. • Wireless service providers – Move from analog to digital cellular to support more voice services. – Upgrading networks from 3G to LTE and beyond. • Backhaul service providers – Must upgrade systems to support increased traffic bandwidth – Move to optical. January 29, 2014 2 Introduction • There is a rapid expansion of consumer demand for data services of all types. • Cable service providers – Work to improve video quality from analog to digital to high definition. – Include internet service at higher and higher data rates. • Wireless service providers – Move from analog to digital cellular to support more voice services. – Upgrading networks from 3G to LTE and beyond. • Backhaul service providers – Must upgrade systems to support increased traffic bandwidth – Move to optical. • Customers still expect data services at a nominal cost regardless of amount of data transferred! January 29, 2014 3 Outline I. II. III. IV. V. Driving Applications for Mixed Signal Next Generation Converter Capabilities ADC & DAC Innovations New Architectural Opportunities Conclusions January 29, 2014 4 Outline I. Driving Applications for Mixed Signal January 29, 2014 5 ADC Timeline: Driving Application 1980 Driving Applications 85 90 95 Mil/Aero Instrumentation Consumer Computer January 29, 2014 00 Telecom Broadband 05 2010 Networked Multimedia 6 The Driving Applications January 29, 2014 7 Automotive Applications January 29, 2014 8 Advanced TV: Analog Content Will Double in Three Years January 29, 2014 9 Converters: Doorway Between Analog & Digital Analog Domain RF Digital Domain Analog Domain Motion Temp Amp ADC Digital Signal Processing DAC Amp Sound I2C SPI Shared Memory … Pressure & Flow SPI I2C Control / MCU Proximity Light Speed SPI Power Management January 29, 2014 10 Converter Performance = Capacity 0 -20 SNR THD SFDR NSD dB -40 -60 BW -80 2nd 3rd -100 -120 0 Frequency (MHz) January 29, 2014 37.5 11 Outline I. Driving Applications for Mixed Signal II. Next Generation Converter Capabilities January 29, 2014 12 Applications (Speed vs. Accuracy) Precision in Parts per Unit 100 1,000 10,000 100,000 1,000,000 10M 10GHz SONET 1GHz Defense/Aero Comms Radar Spectrum Analyzer Flat Panel 100MHz Speed / Bandwidth Digital Oscilloscope DVC Ultrasound DVD Video Auto Radar Distance/ Level 10MHz Wireless Infrastructure Digital Camera Digital X-Ray MRI DSL Precision Optics Motor Control 1MHz Low-Performance 100kHz High-Performance Frontier Industrial Automation Monitor & Control Bio Instruments DVD Audio CT Precision Measurement Process Control 10kHz Patient Monitoring PLC/DCS Water Analysis Building Automation Weigh Scale 1kHz 6 8 10 12 14 16 18 20 22 24 Bits of Resolution (also dynamic range, SNDR) January 29, 2014 13 Applications (Speed vs. Accuracy) Precision in Parts per Unit 100 1,000 10,000 100,000 1,000,000 10M 10GHz SONET 1GHz Defense/Aero Comms Radar Spectrum Analyzer Flat Panel 100MHz Speed / Bandwidth Digital Oscilloscope DVC Ultrasound DVD Video Auto Radar Distance/ Level 10MHz Wireless Infrastructure Digital Camera Digital X-Ray MRI DSL Precision Optics Motor Control 1MHz Low-Performance 100kHz High-Performance Frontier Monitor & Control Industrial Automation Bio Instruments DVD Audio Precision Process Control 10kHz CT Precision Measurement Patient Monitoring PLC/DCS Water Analysis Building Automation Weigh Scale 1kHz 6 8 10 12 14 16 18 20 22 24 Bits of Resolution (also dynamic range, SNDR) January 29, 2014 14 Raw performance dimensions for HS ADCs/DACs HF Noise and Linearity HS Data Converters performance dimensions Power efficiency Trade-off January 29, 2014 Higher integration 15 Performance Metrics – f70, FOM, BW, SNDR • SFDR – Spurious Free Dynamic Range • f70 – Frequency at which SFDR falls below 70dBc. • FOM – Efficiency of conversion Simply put: higher score to the converter consuming lower power for a given SNDR and given bandwidth. R. Schreier’s figure of merit: π΅π ππΆπ΄πΊ = πΊπ΅π«πΉπ π© + ππ β log π • BW – Bandwidth synthesized or received. • SNDR – Signal to Noise plus Distortion Ratio January 29, 2014 16 Digital-to-Analog Converter Trends 10000 Next Gen f70[MHz] 1000 Tseng Engel/ADI Lin/Broadcom 100 Schafferer/ADI Van den Bosch Schofield/ADI 10 Mercer/ADI 1 1995 2000 2005 2010 2015 Year January 29, 2014 17 Analog-to-Digital Converter Trends January 29, 2014 18 Analog-to-Digital Converter Trends Precision January 29, 2014 19 Performance Survey (ISSCC 1997-2007) (courtesy of Dr. Boris Murmann, Stanford) 1.E+11 Flash Folding Pipeline SAR Oversampling Ideal Sampler with 1psrms Jitter 1.E+10 BW [Hz] 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 10 20 30 40 50 60 70 80 90 100 110 120 SNDR [dB] January 29, 2014 20 Outline I. Driving Applications for Mixed Signal II. Next Generation Converter Capabilities III. ADC & DAC Innovations January 29, 2014 21 DAC - Code Dependent Output Impedance With digital input x: ο1 ο£ x ο£ 1 I OP 2N ο½ ο I 0 ο ο¨1 ο« x ο© 2 I ON 2N ο½ ο I 0 ο ο¨1 ο x ο© 2 Ref. Lin, et al., ISSCC, 2009 January 29, 2014 22 DAC - Code Dependent Output Impedance (cont.) It can be shown: Z OP ο½ 2 ο Z0 2 N ο (1 ο« x) Z ON ο½ 2 ο Z0 2 N ο (1 ο x) VOUT ο½ VOP ο VON ο½ RL Z OP ο I OP ο RL Z ON ο I ON VOUT N ο¦ ο¦ R ο 2 ο½ RL ο 2 N ο I 0 ο§ x ο« ο§ο§ L ο§ 2 ο¨ ο¨ ο¦ RL ο 2 HD3 ο½ ο§ο§ 4 ο¨ N 2 οΆ οΆ 1 3 ο·ο· ο x ο« ....ο· ο· οΈ Z 0 (2 ο f ) ο Z 0 ( f ) οΈ 2 οΆ 1 ο·ο· ο οΈ Z 0 (2 ο f ) ο Z 0 ( f ) Biased on cascode minimizes “Zon-Zoff” improving HD3. Ref. Lin, et al., ISSCC, 2009 January 29, 2014 23 DAC – Timing Error Dependent Distortion Process mismatch will result in clock-to-out mismatch (σt). Every segment will have a different timing error resulting in data dependent timing errors. Ref. Doris, et al., Proc. ISCS, 2003 Y. Tang, et al., JSSC, 2011 January 29, 2014 24 DAC – Timing Error Dependent Distortion (cont.) Data-dependent σt timing error Each segment has a random timing error and may also have a systematic error. The timing error is integrated among the bits toggling within a period. Sample Period ο΅ Timing error limits performance for high frequency applications. ο΅ Timing Error Compensation demonstrated recently. Ref. Doris, et al., Proc. ISCS, 2003 Y. Tang, et al., JSSC, 2011 January 29, 2014 25 DAC – Quad-switch current steering: Minimizes data-dependent settling errors ο΅ By introducing a second pair of switches transitions occur even when data is not changing. Ref. - Schafferer, ISSCC 2004 G. Engel, ISSCC 2012 January 29, 2014 26 LTE Carrier centered at 2.9GHz @3.2GSPS >66dBc ο΅ ACLR >66dBc for 18MHz BW output at 2.9GHz Ref. - G. Engel, ISSCC 2012 January 29, 2014 27 Time-interleaved ADCs: the basic idea • Sample Vin with M identical converters in a round-robin (cyclic) fashion • The sample rate of each converter is only fs/M • Power and area grow linearly with M January 29, 2014 28 Time-interleaved ADCs: the reality M=4 in this example January 29, 2014 29 Discrete versus Continuous Time DS LOOP FILTER QUANTIZER + DECIMATION FILTER ADC Pushes the switches “back” DAC MODULATOR • Discrete time DS samples the input directly – Input structure same as Nyquist rate pipeline ADC, switched cap – Loop filter is discrete time, H(z)– switched cap poles and zeros • Continuous time DS samples after the loop filter – Input structure is passive – Loop filter is continuous time, LF(f)ο “real” poles and zeros, generally need tuning • Either loop filter can be lowpass or bandpass Ref. H. Shibata, et al., ISSCC, 2012 G. Manganaro, “Advanced Data Converters” January 29, 2014 30 Continuous Time DS Low pass Band pass Measured spectra from: H.Shibata, “A DC-to-1GHz Tunable RF ΔΣ ADC Achieving DR = 74dB and BW = 150MHz at f0 = 450MHz Using 550mW”, ISSCC 2012 • Multiple possibilities of digitization – Low pass – Band pass – Quadrature, Complex… Ref. H. Shibata, et al., ISSCC, 2012 January 29, 2014 31 Outline I. Driving Applications for Mixed Signal II. Next Generation Converter Capabilities III. ADC & DAC Innovations IV. New Architectural Opportunities January 29, 2014 32 Wireless Infrastructure Microwave Radio Links and Topologies Mobile Backhaul Cell Sites Pre-Aggr. Site Aggr. Site January 29, 2014 Aggr. Site Metro Network Radio Controller Site 33 Transmit Architectures Low/High IF Sampling with Image Rejection LO Feedthrough Unsuppressed Sideband PTARGET +ωRF -ωDAC/4 ωRF +ωDAC/4 Power Amplifier Gain, Phase & offset errors BPF DAC LPF Band Select Filter Antenna Channel Select Filter DSP Cluster 90 DUC & PAPR 0 Network Interface DAC LPF Power Detect and Gain Control DSP DSP Tuning Control Clock Distribution BPF ADC DSP • Familiar Heterodyne Architecture PA pre-distortion observation path – Quadrature Balance Errors need to be managed – Offset and gain corrected in DAC – Phase corrected in DUC January 29, 2014 34 Move Converter Closer to Antennae Gain, Phase & offset errors Power Amplifier BPF DAC LPF Band Select Filter Antenna Channel Select Filter DSP Cluster 90 DUC & PAPR 0 Network Interface DAC LPF Power Detect and Gain Control DSP DSP Tuning Control Clock Distribution BPF ADC DSP • Familiar Heterodyne Architecture PA pre-distortion observation path – Quadrature Balance Errors need to be managed – Offset and gain corrected in DAC – Phase corrected in DUC January 29, 2014 35 Transmit Architectures Direct RF Synthesis • Potential for Direct to RF Synthesis – Eliminate Quadrature balance errors. – No gain or offset errors between converters. – No phase error. January 29, 2014 36 Multi-Band: 1800MHz + 2100MHz + 2600MHz • • • Fdac = 2457.6MHz 4C WCDMA: PAR = 11.7dB, (no additional backoff) FSC = 28mA January 29, 2014 37 Transmit Architectures Multi-Band Direct RF Synthesis • Transmit multiple bands from a single converter January 29, 2014 38 Heterodyne Receive Architectures Clock Distribution Antenna DSP Cluster DSP BPF BPF ADC DSP Network Interface DSP • Conventional Heterodyne Receiver Architecture – Need frequency planning for MxN Mixer spurious – Different circuit & network optimization for different bands January 29, 2014 39 Move Converter Closer to Antennae Clock Distribution Antenna DSP Cluster DSP BPF BPF ADC DSP Network Interface DSP • Conventional Heterodyne Receiver Architecture – Need frequency planning for MxN Mixer spurious – Different circuit & network optimization for different bands January 29, 2014 40 Receive Architectures Direct RF Conversion As the converter moves, performance requirements increase Clock Distribution Antenna DSP Cluster DSP LPF RFADC DSP Network Interface DSP • Potential to Directly to Convert from Antennae – Single LPF for full band. – Tremendous dynamic range requirement. January 29, 2014 41 The Dynamic Range Problem: Analog, Digital and the Converter • Signal processing is the extraction of the desired signal from the “noise.” • Moving to digital processing requires much better converter performance January 29, 2014 42 Conclusions Enables Innovative Technology Advanced HighPerformance Converters The Cloud Innovative Technology Enabled by Innovative Technology January 29, 2014 43 Conclusions • Market shifts drive converter technology • New converter technologies enable innovative technology – Communication Architectures – Defense/Aerospace Technology – Integrated functionality • Next generation instrumentation and measurement equipment enables development of next generation converters • WHAT WILL YOU INVENT WITH THE LATEST CONVERTER INNOVATIONS! January 29, 2014 44 References 1. DATA-OVER-CABLE SERVICE INTERFACE SPECIFICATIONS, DOWNSTREAM RF INTERFACE SPECIFICATION, ISSUE 12, CM-SP-DRFI-I12-111117, CABLE TELEVISION LABORATORIES, INC., 17 NOVEMBER 2011. 2. “3GPP TS 45.005 RADIO TRANSMISSION AND RECEPTION (RELEASE 10)”, v10.4.0, MARCH 2012. 3. B. RAZAVI, “PRINCIPLES OF DATA CONVERSION SYSTEM DESIGN”, IEEE PRESS, PISCATAWAY, NJ, 1995. 4. RUDY J. VAN DE PLASSCHE, “CMOS INTEGRATED ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS 2ND ED.”, KLUWER, DORDRECHT, THE NETHERLANDS, 2003. 5. G. MANGANARO, “ADVANCED DATA CONVERTERS”, CAMBRIDGE UNIVERSITY PRESS, 2011. 6. A. RODRIGUEZ-VAZQUEZ, F. MEDEIRO, & E. JANSSENS, “CMOS TELECOM DATA CONVERTERS”, KLUWER ACADEMIC PUBLISHERS, 2003. 7. C.-H. LIN, “A 12-BIT 2.9 GS/S DAC WITH IM3< -60DBC BEYOND 1GHZ IN 65NM CMOS”, IEEE JSSC, DECEMBER 2009. 8. S. LUSCHAS AND H.-S. LEE, “OUTPUT IMPEDANCE REQUIREMENTS FOR DACS”, IEEE INTERNATIONAL SYMPOSIUM OF CIRCUITS AND SYSTEMS”, VOL. 1, 2003, PP. 861-864. 9. G. ENGEL, “THE POWER SPECTRAL DENSITY OF PHASE NOISE AND JITTER: THEORY, DATA ANALYSIS, AND EXPERIMENTAL RESULTS”, ANALOG DEVICES, AN-1067. 10. P. SMITH, “LITTLE KNOWN CHARACTERISTICS OF PHASE NOISE”, ANALOG DEVICES, AN-741. 11. K. DORIS, “MISMATCH-BASED TIMING ERRORS IN CURRENT STEERING DACS”, IEEE PROCEEDINGS OF ISCAS, 2003. 12. G. ENGEL, “A 14B 3/6GHZ CURRENT-STEERING RF DAC IN 0.18UM CMOS WITH 66DB ACLR AT 2.9GHZ”, IEEE ISSCC, 2012. January 29, 2014 45 References 13. K. POULTON, “A 7.2-GSA/S, 14-BIT OR 12-GSA/S, 12-BIT DAC IN A 165-GHZ FT BICMOS PROCESS”, VLSI SYMPOSIUM, 2011. 14. Y. TANG, “A 14 BIT 200MS/S DAC WITH SFDR >78DBC, IM3 <-83DBC AND NSD <-163DBM/HZ ACROSS THE WHOLE NYQUIST BAND ENABLED BY DYNAMIC MISMATCH MAPPING”, IEEE JSSC JUNE 2011. 15. H. Shibata, “A DC-to-1GHz tunable RF ΔΣ ADC achieving DR = 74dB and BW = 150MHz at f0 = 450MHz using 550mW”, ISSCC 2012. January 29, 2014 46 January 29, 2014 47
