CS/IT- 402(GS)
B.E
(Fourth Semester) EXAMINATION, june, 2012
(Grading System)
(common for CS & IT Engg. branch)
COMPUTER SYSTEM ORGANIZATION
time : Three Hours
maximum marks : 70
Minimum Pass Marks : 22 (D Grade)
www.rgpvonline.com
Note : attempt all questions. all question carry equal marks.
1. (a) Describe the von-neumann model and explain the functioning of its
components.
(b) Explain and draw a diagram of a bus system that use multiplex k, register of n bits each to produce an
n-line common bus.
OR
2. (a) what is instruction cycle ? explain different phases of instruction cycle and show flow chart for
instruction cycle.
(b) explain various addressing modes with the help of example.
3. (a) discuss in brief microprogram control unit and hardwired control unit.
(b) draw and explain flowchart for addition and subtraction of floating point number.
4. (a) represent the number (+ 46.5)10 as a floating point binary number with 24-bits. the normalized
fraction mantissa has 16 bits and the exponent has 8 bits.
(b) define the following :
(1) micro-operation
(2) microcode
(3) microinstruction
(4) microprogram
5. (a) explain with suitable example the working principle of DMA controller.
(b) what do you mean by interrupt? explain the various interrupt handling techniques?
OR
6. (a) what do you mean by synchronous and asynchronous data transfer ? explain handshaking method of
asynchronous data transfer.
(b) explain the use of the following instructions:
(1) DAA
(2) RIM
(3) MOV reg, M
(4) PUSH D
7. (a) what is cache coherency? why is it necessary? explain different approaches for cache coherency.
(b) explain associative memory with its hardware organization. discuss the procedure for reading and writing data in
associative memory.
8. (a) explain in short the following:
(1) memory hierarchy
(2) memory management hardware
(b) what is paging? explain how paging can be implemented in CPU to access virtual memory.
9. (a) formulate a six segment instruction pipeline for a computer. specify the operation to be performed in
each segment.
(b) draw and explain the typical functional structure of a SIMD array processor.
OR
10. explain the following terms :
(1) data dependency
(2) pipeline conflicts
(3) interprocessor communication (4) interconnection structure.
B.E. (fourth semester) EXAMINATION, Dec,2011
(Common for CS, EC&IT, Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
401(N) www.rgpvonline.com
Note: Attempt one questions from each unit. Total question to be attempted are five. All question carry equal mark.
1.(a) Discuss the organization of 8085 microprocessor . What are the different flag s of
8085 flag register?
(b) Explain the following
(i) Micro operation
(ii) Macro operation
(iii) Program counters (iv) Instruction cycle
(iv) Input output instruction
2. (a) Draw a conman bus system with four register with the help of multiplexers.
(b) A digital computer has common bus system for 16 register of 32 bits each. The bus is
with multiplexer.
(i) How many selection input are in each multiplexer?
(ii) What size of multiplexer in need?
(iii) How many multiplexer are there in the bus?
3. (a) Explain how the mapping from an instruction code to a microinstruction address can be done by means of a read
only memory.
(b) With the help of block diagram , describe the organization of a microprogramming unit.
4. (a) Explain the following in detail.
(i) Address sequencing (ii) Hardwired control unit.
(b) Draw and explain the organization of a CPU showing the connections between the
Register to a common bus.
5. (a) Differentiate between the following –
(i) Synchronous and asynchronous modes of serial data transfer
(ii) interrupt initialized I/O and direct memory access.
(b) Explain in brief the instruction set of 8085 microprocessor (Give only types of Instruction)
6. (a) What are the different types of DMA techniques ? Explain the basic principle of DMA.
(b) Explain priority interrupts and polling in context to interrupt initialled I/O
7. (a) What is meant by memory hierarchy in a computer system also explain what is
Meant by associative memory and virtual memory?
(b) Explain the following relation to cache memory(i) Locality of reference (ii) Hit ratio (iii) Mapping (iv) Writing into cache
(v) Cache initialization
8. (a) Explain memory protection and memory segmentation by memory management
hardware .
(b) The access time of a cache memory is 100 ns and that of main memory is 1000 ns .It
is estimated that 80 % of the memory requests are for read and 20% for write. The
hit ratio for read access is 0.9 . A write through procedure is used –
(i) What is the average access time of the system considering only memory read cycle?
(ii) What is the average access time of the system for both read and write requests
(iii) What is the hit ratio taking into taking into consideration write cycle ?
9. What is pipelining? What is the need of pipelining? Explain the pipeline organization of an arithmetic pipelines .
10. Write short notes on any two of the following:
(i) Vector processor and array processor.
(ii) Interconnection structure
(iii) Interposes communication
(iv) Memory interleaving.
Note:
B.E. (fourth semester) EXAMINATION, June, 2011
(Common for CS,EC &IT, Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
401(N) www.rgpvonline.com
Attempt one question from each unit. All question carry equal marks.
1 (a) Draw the Von-Neumann model of a digital computer . Explain is various subsystem.
(b) Explain with the help of examples, the addressing modes of a basic computer
OR
2. (a) Draw and explain architecture of 8085 microprocessor
(b) A computer uses a memory iunit5 with 265 k words of 32 bits each. A binary is stored in one word of memory. The
instruction has four parts: An indirect address, An operation the register code part to specify one of 64 register and
address part:
(i) How many bits are there on the operation code The register code part and the address part?
(ii) Draw the instruction words format and indicate the number of bits in each part.
(iii) How many bits are there in the data in address inpu5t of the memory?
3. (a)
Explain the following terms .
(i) Microinstruction (ii) Microprogramming
(iii) Control address register (iv) Sequencer
(iv) Control memory
(b) Explain the concept of address sequencing. Also explain making of an instruction
OR
4. (a) Write down the algorithm for addition and subtraction with sign magnitude data .
Also draw the flowchart.
(b) Draw and explain 2-bit by 2 bit array multiplier.
5. (a) Differentiate between the following
(i) Isolated and memory – mapped I/O
(ii) Synchronous and Asynchronous serial data transfer
(b) Explain polling and daisy changing methods for establishing priority interrupt.
6. (a) Explain the following modes of data transfer
(i) Program controlled
(ii) Interrupt driven
(iii) Direct memory access
(b) What is an IOP? Explain the process of communication between a CPU and IOP
7. (a) Draw and explain the memory hierarchy in a digital computer. What are the
advantages of cache memory over main memory?
(b) What is associative memory? Explain the concept of address space and memory
space in virtual memory
8. Write short notes on any two of the following
(a) Mapping techniques of cache memory.
(b) Cache initialization and written into cache
(c) Types of RAM and ROM
(d) Memory management hardware
9. (a) Write down the Flynn’s classification of computer?
(b) What does pipeline , vector and array processor mean in parallel processing ?
10. Draw and explain the pipeline for floating point addition and subtraction .
B.E. (fourth semester) EXAMINATION, Dec, 2010
(Common for CS/ EC &IT, Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
401 www.rgpvonline.com
Note: The question paper is divided into five units. Each unit carries an internal choice. Attempt one question from each
unit. Thus attempted five questions in all. All question carries equally
marks. Assume suitable data whenever necessary.
1. (i)
Explain with an example , how effective address is calculated in different types of addressing modes.
(ii) Describe the major hardware functional unit of 8085 microprocessor eighth a neat complete functional diagram.
(iii) What is the difference between the two complement representation of a number and the two’s complement of a
number?
OR
2. (i)
A machine support 16 –bit instruction format. The size of address fields is 4-biy. The computer uses expanding
oppose technique. Calculate:
(a) The number of two-address instruction supported by this machine if it has n zero address instruction and m oneaddress instruction.
(b) The number of zero-address instruction supported by this machine if it has n zero
address instruction and m one-address instruction.
(ii) Write program to evaluate the arithmetic statement:
P = (x-y+z)* (m*n-0) / Q+R*S
By using :
(i) Two-address instruction
(ii) One-address instruction (iii) Zero address instruction
3. (i) Explain booth’s multiplication algorithm .Show the step-by-step multiplication process
using booth’s algorithm to multiply the number (+15) (-13) in binary
(ii) What is the need of a control unit in a computer? What is a hardwired control unit?
What are its advantage and disadvantage?
OR
4. (i)
Give the flowchart for add and subtract operation of two signed 2’s complement data. Explain the logic of each
operation.
(ii) Draw and explain the circuit diagram of 4-bit array multiplier.
(iii) With a neat block diagram, explain the working principle of microprogram
sequencer.
5. (I) List various commands that an interface may receive from control line of the Bus.
(ii) Explain the process of handling an interrupt that occurs during the execution of a program, with the help of an
example.
(iii) A DMA controller transfer 16-bits words to memory using cycle stealing. The words are assembled from a device that
transmits character at a rate of 2400 characters per second. The CPU be is fetching and executing instruction at an
average rate of 1 million instructions per second. By how much the CPU be slowed down because of the DMA
transfer?
OR
6(i) Define the following :
(a) I/O versus Memory Bus
(b) I/O interface
(c)
parallel versus Serial data transfer
(ii)
Explain the different techniques used for interfacing I/O device with 8085 processor.
State the merits and demerits of each.
7(i) A digital computer has a memory unit of 64 K ×16 and a cache memory of 1K words.
The cache uses direct mapping with a block size of four words :
(a)
How many bits are there in tag, index, block and word fields of the address format ?
(b)
How many bits are there in each word of cache and how are they divided in to function ?
includes a valid bit.
(c)
How many block does the cache accommodate?
(ii) What is associative memory? Explain the concept of match-logic for associative
memories.
(iii) A computer uses RAM chips of 1024×1 capacity:
(a) How many chips are needed and how should their address lines be connected to provide
a memory capacity of 1024 bytes?
(b) How many chips are needed to provide a memory capacity of 16 Kbytes? Explain in
words how the chips are to be connected to the address bus.
OR
8. (i) A CPU has 32 bit memory address and 256 KB cache memory. The cache is organized
as 4-way set associative cache with cache block size of 16 bytes :
(a) What is the number of sets in the cache?
(b) What is the size of the tag field per cache block ?
(c) How many address bits are required to find the byte offset within a cache block ?
(d) What is the total amount of extra memory (in bytes) required for the tag bits ?
(ii) A virtual memory system has 6k words of address space. Page references are made
by CPU in the following sequence :
3,2,0,3,4,1,2,2,0
Find out the pages that are available at the end if the replacement algorithm used is
(a) LRU (b) FIFO.
Assume the page and block size of 1K words.
9. (i) A non-pipelined system takes 100 ns to process a task. The same task can be processed in a six- segment pipeline
with a clock cycle of 20ns . Determine the speedup ratio of the pipeline for 200 tasks .What is maximum speedup that can
be achieved?
(ii) Explain the various dynamics and static interconnection networks which interconnect Multiprocessor system.
OR
10. (i) Discuss all factor which affect the performance of pipelining processor based systems.
(ii) Explain the operation of a multiprocessor system with multi port memory.
(iii) Explain any one vector processing method with suitable illustration
********************************************************************************************************
B.E. (fourth semester) EXAMINATION, June, 2010
(Common for CS, EC & IT, Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
401(N) www.rgpvonline.com
Note:
Attempt one question from each unit. All question carry equal marks.
1. (a) Draw and explain the functional block diagram of 8085 microprocessor . Also draw its
flag Structure.
(b) Write down the instruction format of a basic computer . Explain the fetch. Decode and
execution cycle of any one.
OR
2. Write short notes on the following :
(a) Computer register (b) Stored program organization (c) Micro operation
(d) Instruction cycle
3. (a) Compare hardwired microprogrammed control units giving their relatives merits and demerits.
(b) Draw the format of a microinstruction and explain how a microprogramming .
Sequencer works
OR
4. (a) Explain the algorithm for division of a signed magnitude data. What is divide overflow?
(b) Draw the block diagram of a BCD adder . Explain How decimal subtraction can be performed.
5. (a) Explain how I/O interface supervise and synchronize the processor bus and peripheral
devices.
(b) What are the different methods of DMA transfer ? Explain the actual process of direct
memory access.
OR
6. (a) Enlist the data transfer instruction of 8085 microprocessor . Write an assembly language program to add two 8 bit
numbers 46 H and 52 H and t store the result at 4008 H.
(b) What are the advantages of handshaking during asynchronous data transfer? Which signed are used for
handshaking?
7.(a) Explain the following terms:
(a) Destructive and non-destructive memory readout. (b) Read and virtual memory
(c) Associative and set associative mapping. (d) Memory management unit.
OR
8.(a) Explain cache memory organization which mapping techniques are used in cache
memory ?
(b) A virtual memory system has an address space of 8K words, a memory space of 4 k
words and page and block size of k words. The following page reference changes occur
during a given time interval .(only page changes are listed . If the same page is referenced
again it is not listed twice)
42016140102357
Determine the 4 pages that are resident in main memory after each reference change if the
replacement algorithm used is :
(a) FIFO
(b) LRU
9. (a) Draw a four segment instruction pipeline . Also draw the timing diagram >
(b) Explain the following terms in relation to pipeline.
(i) Throughput (ii) Space time diagram (iii) Speedup
(iv) Hardware interlocks (v) Operand forwarding.
OR
10. (a) Explain how branch instruction are handled in pipeline ?
(b) Write a short on supercomputers.
B.E. (fourth semester) EXAMINATION, June, 2008
(Common for CS EC & IT. Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
401 www.rgpvonline.com
Note:
Attempt any five questions. All question carry equal marks.
1. (a) Draw and explain the structure of Von Neumann machine.
(b) Define the following
(i) Memory address register
(ii) Memory data register
(iii)
Instruction registers (iv) Accumulator
(v)
Programme counter
(c) Show that the statement:
A ? A+A
Symbolize a shift-left micro-operation
(d) Explain the function of the following instruction .also list the micro operation of control
function associate with each.
(i) AND
(ii) ADD
2. (a) Define the following terms :
(i) Control memory
(ii) Microprogramming sequencing
(iii) Address sequencing (iv) Microinstruction sequencing
(iv) Register transfer language
(b) Differentiate between the following:]
(i) Hardwired control unit and microprogrammed control unit.
(ii) Instruction level and microinstruction level instruction execution.
(c) A microprogram sequences uses a register stock eight level deep. Draw the block
diagram of the sequence formulate the sequence of internal operation which are
required to implement the call and return from subroutine microinstruction.
3. (a) Derive the algorithm in flowchart from for the addition and the subtraction of fixed point
Binary number in sign magnitude representation with subtraction done by a parallel sub
tractor (E.A?A-B).Show one stage of the adder subtractor circuit with an addsubtract control (ASC).
(b) Show that contents of register A,E,Q and SC during the process of multiplication
of to binary numbers 11111 (multiplicand) and 10101 (multiplier) .The signs are not
included.
4. (a)
Differentiate between the following
(i) I/O program control transfer and DMA transfer
(ii) Isolated I/O and memory mapped I/O
(b) How many character per second can be transmitted over a 1200 band line in each
of the following modes? (Assume a character code of eight bits) :
(i) Asynchronous transmission with two stop bits.
(ii) Asynchronous transmission with one stop bits.
(c)
What is basic advantages of priority interrupt over a non-priority system? It is possible to
have a priority interrupt without a mask register?
5.
(a) What is cache memory ? Discuss the basic design of cache.
(b) A microprocessor uses RAM chips of 1024 × one capacity
(i) How many chips are needed and how should there address lines be connected to
provide a memory capacity of 1024 bits?
(ii) How many chips are needed to provide a memory capacity of 16K bytes? Explain in
words how the chip are to be connected to the address bus.
6.(a) Draw the diagram for a pipeline processor structure. Explain the necessity of a lotus
or input register and processing circuits within a segment.
(b) Explain the following terms:
(i) Pipeline conflicts
(ii) Data dependency
(iii) Priority interrupts
(iv) Memory hierarchy
7.(a) Draw the flowchart and explain how division of two fixed point binary numbers in sig–
magnitude representation is carried out.
(b) With the help of suitable flowchart explain the interrupt initiated data transfer operation.
Discuss its relative advantages and disadvantages.
8. (a) Microinstruction format
(b) Virtual memory
(c) Universal asynchronous receiver transmitter.
B.E. (fourth semester) EXAMINATION, Nov,Dec, 2007
(Common for CS, EC & IT Engg.)
(COMPUTER SYSTEM AND ORGANIZATION)
www.rgpvonline.com
Note: Solve any one question from each unit. Answer should be logical . All question carry
equal marks.
1. (a) What is difference between direct and an direct address instruction?
(b) Represent the following conditional control statement by two register transfer statement
wit function:
IF (P=1) Then (R1?R2) else (?=1) then (R1 ?R3)
OR
2. (a) A digital computer has a memory unit with a capacity of 16348 words , 40 bits per words,
The instruction code format consists of six bits for the operation part and 14 bits for the
address part (no indirection mode bit.) Two instruction are packed in one memory word
and a 40-bit instruction register . It is available in control unit . Formulate a procedure for
fetching and executing instruction for this computer.
(b) Explain implicit and register addressing mode with example.
3. (a) Formulate a mapping procedure that provides eight consecutive microinstruction for
each routine The operation code has six bits and the control memory has 2048 words.
(b) Explain the difference between hardwired control and micro programmed control .Is it
possible to have a hardwired control associate with a control memory ?
OR
4. Explain the following:
(i) Micro –operation
(ii) Microinstruction
(iii) Microcode (iv) Microcode
(iv) Pipeline register
5. (a) Explain Booth Multiplication Algorithm.
(b) Represent the number (+46.5)10 as a floating point binary number with 24 bits. The
normalized fraction Mantissa has 16 bits and the exponent has 8 bits.
OR
6. (a) Draw and Explain the flowchart for hardware divide operation.
(b) Explain the hardwire for signed magnitude addition and subtraction with blockd iagram.
7. (a)
Why does DMA have priority over the CPU when both request are memory transfer ?
Explain
(b) Explain daisy chaining priority interrupt.
OR
8. (a) Why are the read and write control line in DMA controller bidirectional? Under what
condition for what purpose are the used as input? Under what condition and for
purpose are they used as output?
(b) Difference between memory mapped I/O and isolate I/O. What are the advantages
and disadvantages of each?
9. (a) An address space is specified by 24 bits and the corresponding memory space by 16
bits . How many words are there in address space in how many words are in there
memory space?
(b) Explain two-way set associative mapping cache.
OR
10. (a) Describe by means by block diagrams . How multiple matched words can be reads out
of an associative memory.
(b) Formative a six segment instruction for pipeline for a computer. Specify the operation
to be performed in each segment.
*******************************************************************************************************
B.E. (fourth semester) EXAMINATION, Dec, 2006
(COMPUTER SYSTEM AND ORGANIZATION)
CS/EC/IT-401 www.rgpvonline.com
Note:
Attempt any five questions. All question carry equal marks.
1. (a) Describe the Von Neumann model and functions of the following:
(I) Memory Buffer Register
(ii) Memory Address Register
(iii) Instruction Register
(iv) Instruction Buffer Register
(v) Program counter
(vi) Accumulator and multiplier quotient
2. (a)
How many 128×8 memory capacity of 4096×16?
(b)
Write in brief different types of instruction formats.
3. (a) Describe the role of addressing mode used in computers.
(b) Proved that a K-stage liner pipeline can be at most K-time faster them that of nonpipeline serial processor.
4. (a) Explain of the role of virtual Memory.
(b)
What must the address field to an Indexed addressing mode instruction be to make it the
same as the register indirect mode instruction?
5. (a) Describe the procedure for addition and subtraction for fixed point number. Explain by
use of Flowchart?
(b) Explain Booth multiplication algorithm and its hardware.
6. (a) Why does DMA have priority over the CPU when booth request a memory transfer?
(b) What is an interrupt service subroutine? How can the interrupt priority be resolved?
7. (a) Differentiate between following:
(i) Write through and write –back
(ii) Associative memory and cache memory
(b) What is the difference between instruction pipeline and Arithmetic pipeline? What
are the advantages of pipeline?
8. Write short notes on any for the following:
(i) Microinstruction format
(ii) Daisy chaining
(iv) Locality of reference
(v)Memory Management Hardware
*********
B.E. (fourth semester) EXAMINATION, June, 2005
(COMPUTER SYSTEM AND ORGANIZATION)
CS/EC/IT-401 www.rgpvonline.com
Note: Attempt any five questions. All question carry equal marks.
1. (a) What is von newmann model of computer ? Discuss its features.
(b) Define the following –
(i) Clock (ii) Executive cycle
(iii) Fetch cycle (iv) Instruction cycle
(v) Micro- operation
(c)
Consider the following register transfer statements for two 4-bit register R1 and R2 :
xT : R1 ? R1 +R2
xT: R1 ? R2
Every time that variable T=1, either the content of R2 s added to the content of R1 if x=1 or the
content of R2 is transferred to R1 if x=0 . Draw a diagram showing the hardware
implementation of the two statements. Use block diagram for the two 4-bit register, a4- bit
adder and a quadruple 2 to 1 line multiplexer that select the inputs to R1 .In the diagram show
how the control variables x to T select the inputs of the multiplexer and the load input of
register R1.
2. (a) Discuss in brief microprogramming control unit and hardwired control unit.
(b) Draw the function block diagram of control unit of basic computer.
(c) How the selection of address is done in control memory? Explain.
3. (a) Draw and explain flowchart for additional and subtraction of floating points number.
(b) Draw the required register configuration to carry out multiplication using both multiplication
algorithm and hence multiply (-6) and (4)
4. (a) Explain in short programmed I/O and interrupt initiated I/O
(b) What do you mean by synchronous and asynchronous data transfer? Explain hand sacking
method asynchronous data transfer?
5. (a) Explain associative memory with its hardware organization . Explain how the data is read and
write in the associative memory.
(b) An address is specified by 32-bits and corresponding memory space by 24-bits
(i) How many words are there in address space?
(ii) How many words are there in the memory space?
(iii) If a page consists of 4 k words , How many pages and blogs are there in in the system
6. (a) How the pipeline processing is done and instruction pipeline? Explain with timing diagram for 4
segment instruction pipeline
(b) What do mean by instruction pipeline conflicts? Explain in short.
7. Explain the need of cache memory in the computer system Explain direct mapping of cache
organization .
8. Write short notes on any three of the following
(i) Addressing mode (ii) Microprogramming (iii) Decimal Arithmetic unit
(iv) DMA (v) Arithmetic pipeline
*****************************************************************************