Bharati Vidyapeeth’s
Institute of Computer Applications and Management
A-4, Paschim Vihar, New Delhi-63.
MCA – 2nd Semester (2012-15)
IInd Internal Test
Computer Organization – MCA - 107
Max. Marks: 45
Max. Time: 02 Hrs.
Note. Attempt any four of the following.Q1. is compulsory Marks are indicated against each
question
Q1.
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.
xi.
xii.
xiii.
xiv.
xv.
Attempt any TEN of the following
(1.5*10=15)
Formulate a mapping procedure that provides eight consecutive microinstructions for each
routine. The operation code has six bits and the control memory has 2048 words.
A computer has 16 registers, an ALU with 32 operations and a shifter with eight operations,
all connected to a common bus system. Formulate a control word for the micro-operation.
Why I/O interface is required?
A non pipeline system takes 50 ns to process a task .The same task can be processed in a six
segment pipeline with a clock cycle 10 ns .Determine the speedup ratio of the pipeline for
100 tasks. What is the maximum speed up ratio that can be achieved
What is memory interleaving?
Discuss Horizontal and Vertical instruction
What must the address field of an indexed addressing mode instruction be to make it the
same as a register indirect mode instruction?
The content at the top of a memory stack is 5320. The content of the stack pointer SP is
3560. A two word call subroutine instruction is located in memory at address 1121. What are
the content of PC, SP and the top of the stack before the call instruction is fetched from the
memory.
Consider a computer with four floating-point pipeline processors. Suppose that each
processor uses a cycle time of 40 ns. How long will it take to perform 400 floating-point
operations?
What is the difference between Single, General Register and Stack organizations?
Define different types of interrupt.
Write symbolic micro program for Exchange
How many characters per seconds can be transmitted over a 1200 baud lines in Synchronous
serial transmission? (Assume a character code of 8 bits)
What is priority interrupt?
Why does DMA have priority over the CPU when both request a memory transfer.
Section -B
Attempt any FOUR of the following
Q2.
Design micro program sequencer for control memory.
(5)
Q3.
Explain various possible hardware schemes that can be used in an instruction pipeline in
order to minimize the performance degradation caused by instruction branching.
(5)
Q4.
a) What programming steps are required to check when a source when a source interrupts the
computer while it is still being serviced by a previous interrupt request from the same source.
(2.5)
b) A DMA controller transfers 16-bit words to memory using cycle stealing. The words are
assembled from a device that transmit characters at a rate of 2400 characters per second
The CPU is fetching and executing instructions at an average rate of 1 millions
instructions per second. By how much will the CPU be slowed done because of the DMA
transfer.
(2.5)
Q5. Explain DMA transfer in a computer system
(5)
Q6. Design parallel priority interrupt with 8 interrupt sources.
(5)
Q7. Discuss DMA transfer in a computer system using block diagram in detail.
(5)
Q8. Write short notes on any one of the following
(5)
i. Isolated I/O and memory mapped I/O
ii. RISC pipeline
iii. Array Processors
Attempt any ONE of the following
Q1. Write a program to evaluate the arithmetic statement:
i. Using a general register computer with three address instructions.
ii. Using an accumulator type computer with two address instructions.
iii. Using an accumulator type computer with one address instructions.
iv. Using a stack organized computer with zero address instructions.
Q2. Discuss ten addressing modes with examples
(10)
(10)
Q3.
a) A commercial interface unit uses different manes for handshake lines associated with
the transfer of data from I/O devices into interface unit. The interface input handshake line is
labeled STB (strobe), and the interface output handshake line is labeled IBF (input buffer
full). A low-level signal on STB loads data from the I/O bus into the interface data register.
A high level signal on IBF indicates that the data item has been accepted by the interface.
IBF goes low after an I/O read signal from the CPU when it reads the content of the data
register.
i. Draw a block diagram showing the CPU, the interface, and the I/O device together with
the pertinent interconnection among the three units.
(2.5)
ii. Draw a timing diagram for the handshaking transfer
(2.5)
iii. Obtain a sequence-of-events flowchart for the transfer from the device to the interface
and from the interface to the CPU
(2.5)
b) Discuss the destination initiated transfer using handshaking
(2.5)
Q3. a) Explain instruction pipleling and list the factors that cause the problems for instruction
pipleling. What are the different techniques that can reduce performance degradation?