CENG 252 Computer Organization QUIZ III
Each wrong answer for multiple-choice questions costs you 10 points!
Name :
1. (20) The first two bytes of a 2M x 16 main memory have the following hex values:
Byte 0 is FE
Byte 1 is 01
If these bytes hold a 16-bit two's complement integer, what is its actual decimal value if:
a. memory is big endian?
b. memory is little endian?
a. FE0116 = 1111 1110 0000 00012 = -51110
b. 01FE16 = 0000 0001 1111 11102 = 51010
2. (20) A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150
different operations. All instructions have an operation code part (opcode) and an address part (allowing for
only one address). Each instruction is stored in one word of memory.
a. How many bits are needed for the opcode?
b. How many bits are left for the address part of the instruction?
c. What is the maximum allowable size for memory?
d. What is the largest unsigned binary number that can be accommodated in one word of memory?
a. 150 instructions implies 28 (27 will only give us 128 instructions), or 8 bits for the
opcode.
b. 24 - 8 = 16.
c. 216, or 32M.
d. 24 1's, or 224 -1.
3. (10) Suppose that a 2M x 16 main memory is built using 256K x 8 RAM chips and memory is wordaddressable.
a. How many RAM chips are necessary?
b. How many RAM chips are there per memory word?
c. How many address bits are needed for each RAM chip?
d. How many address bits are needed for all of memory?
a. 16 (8 rows of 2 columns)
b. 2
c. 256K = 218, so 18 bits
d. 2M = 221, so 21 bits
4. (40) Suppose we have the instruction Load 1000. Given memory and register R1 contain the values below:
Memory Address
1000
--1100
--1200
--1300
--1400
Value
1400
400
1000
1100
1300
Assuming R1 is implied in the indexed addressing mode, determine the actual value loaded into the
accumulator if R1= 200 and fill in the table below:
Mode
Value loaded into AC
CENG 252 Computer Organization QUIZ III
Each wrong answer for multiple-choice questions costs you 10 points!
Immediate
Direct
Indirect Memory
Indexed
1000
1400
1300
1000
5. (10) A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this
organization is that
a) It does not allow simultaneous access to the intended data and its tag
b) It is more expensive than other types of cache organizations
c) The cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in
the cache
d) Its access time is greater than that of other cache organizations
e) The number of blocks required for the cache increases linearly with the size of the main memory.
6. (20) A hypothetical microprocessor communicates with its memory and peripheral over an 8-bit data bus
and a 16-bit address bus. It contains an 8-bit accumulator A and two 16-bit registers: program counter PC
and index register X (see diagram below) The opcode of each instruction is one byte (8 bits) long. Assume
that any internal processor time is negligible, and that the time to address memory and transfer one byte in
either direction over the data bus equals unity (one memory cycle).
The time taken to fetch and execute the 3-byte instruction “store A in some address indexed by X” is
a) 3
b) 4 (3 cycle for fetch and 1 cycle for store. Then total is 3+1 = 4)
c) 5
d) 6
e) 7
7. (30) If a cache access requires one clock cycle and handling cache misses stalls the processor for an
additional five cycles, which of the following cache hit rates comes closest to achieving an average memory
access of 2 cycles?
a)
b)
c)
d)
e)
75
80 (2 = h*1 + (1-h)*6 Î h=0.8)
83
86
98
8. (80) Write the microinstruction sequence to implement the two word machine level instruction OR R1, X
where the address mode is indicated as “indexed based addressing”, and R6 and R7 are the index and base
registers, respectively
a) On a single bus organization
b) On a double bus organization
For single bus
// For fetching first word
PCout, MARin, READ, INC, Zin
WFMFC, Zout, PCin
MDRout, IRin
//For fetching second word
PCout, MARin, READ, INC, Zin
WFMFC, PCin
MDRout, Yin //Y register contains offset X
// Add R6+R7+X
CENG 252 Computer Organization QUIZ III
Each wrong answer for multiple-choice questions costs you 10 points!
R6out, ADD, Zin
Zout, Yin
R7out, ADD, Zin
Zout, MARin, READ //Get the data at address pointed to by (R6+R7+X)
WFMFC, R0out, Yin // To save time, copy R0 into Y register
MDRout, OR, Zin
Zout, R0in
END
9. (40) The parameters of a hierarchical memory system are specified as follows:
Main memory size = 8K blocks
Cache memory size = 512 blocks
Block size = 16 words
Determine the size of the tag field under the following conditions:
a. Fully associative mapping
b. Direct mapping
c. Set associative mapping with 16 blocks/set
TAG
13
4
8
a)
b)
c)
SET/BLOCK
0
9
5
WORD
4
4
4
10. (30) What is the average access time of a system having three levels of memory hierarchy: a cache memory,
a semiconductor main memory, and magnetic disk secondary memory. The access times of these memories
are 20 ns, 200 ns, and 2 ms, respectively. The cache hit ratio is 80 per cent and the main memory hit ratio is
99 per cent.
h1 = 0.8 : cache hit ratio,
h2 = 0.99 : main memory hit ratio
atc = access time for cache
atm = access time for main memory
ats = access time for secondary memory
Then the formula for average access time is (if access time for upper memories does not include lower memory
accesses)
Aat = h1*atc + (1-h1)[atc + h2*atm + (1-h2)*(atm + ats)]
If it includes
Aat = h1*atc + (1-h1)[h2*atm + (1-h2)*ats]
11. (20) If the clock frequency of a computer system is 50 Mhz, what is the period of this clock in ns?
F*T = 1 Î T = 1/(50*106)sn = (1*109) /(50*106)ns = 20ns