III BSC ECS
8085 MICROPROCESSOR AND APPLICATIONS
UNIT I INTRODUCTION TO 8085
Pin Diagram – Architecture – Demultiplexing the bus – Generation of control signals – Fetching, decoding
and execution of instruction – Instruction timing and operation status.
UNIT II INSTRUCTION SET AND ADDRESSING MODES
Instruction set – Addressing modes – Instruction format – Simple program – Memory Read machine cycle
– Memory write machine cycle.
UNIT III INTERFACING CONCEPTS
Peripheral I/O instructions – device selection and data transfer – Input Interfacing – Practical Input
interfacing using decoders – Interfacing O/P Devices: LED and 7 segment Display – Interfacing memory – Memory
time and unit states.
UNIT IV PARALLEL AND SERIAL INTERFACE
Introduction to programmable Peripheral Interface 8255 – Pin Diagram – Architecture – Modes of
Operation: I/O and BSR – Architecture and operation of 8251 (USART).
INTERRUPT AND TIMER LOGIC
8085 interrupts - Architecture of programmable interrupt controller 8259 –– Architecture of 8254 Programmable
Interval timer / counter – Modes of Operation of 8254 – Generating square wave using 8254.
UNIT V APPLICATIONS
Time delay program – Traffic Light Control System – Water Level Controller – Stepper Motor Control –
Interfacing DAC – Interfacing ADC – Temperature measurement.
TEXT BOOKS
1. R.S.Gaonkar “Microprocessor Architecture, Program And Its Application With 8085”, New Age
International (P) Ltd,
2. S.Malarvizhi, “Microprocessor and Its Application”, - Anuradhe Agencies Publications – I edition, March
1999.
SYLLABUS
: INTRODUCTION TO 8085
Pin Diagram – Architecture – Demultiplexing the bus – Generation of control signals – Fetching,
decoding and execution of instruction – Instruction timing and operation status.
INSTRUCTION SET AND ADDRESSING MODES
Instruction set – Addressing modes – Instruction format – Simple program – Memory Read
machine cycle – Memory write machine cycle.
Microprocessor

A microprocessor is a clock-driven semiconductor device consisting of electronic logic
circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.

The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.

In large computers, a CPU performs these computing functions.The Microprocessor
resembles a CPU exactly.

The microprocessor is in many ways similar to the CPU, but includes all the logic
circuitry including the control unit, on one chip.

The microprocessor can be divided into three segments for the sake of clarity. – They are:
arithmetic/logic unit (ALU), register array, and control unit.

A comparison between a microprocessor, and a computer is shown below:

Arithmetic/Logic Unit: This is the area of the microprocessor where various computing
functions are performed on data. The ALU unit performs such arithmetic operations as
addition and subtraction, and such logic operations as AND, OR, and exclusive OR.

Register Array: This area of the microprocessor consists of various registers identified
by letters such as B, C, D, E, H, and L. These registers are primarily used to store data
temporarily during the execution of a program and are accessible to the user through
instructions.

Control Unit: The control unit provides the necessary timing and control signals to all
the operations in the microcomputer. It controls the flow of data between the
microprocessor and memory and peripherals.

Memory: Memory stores such binary information as instructions and data, and provides
that information to the microprocessor whenever necessary. To execute programs, the
microprocessor reads instructions and data from memory and performs the computing
operations in its ALU section. Results are either transferred to the output section for
display or stored in memory for later use. Read-Only memory (ROM) and Read/Write
memory (R/WM), popularly known as Random- Access memory (RAM).
1. The ROM is used to store programs that do not need alterations. The monitor program of
a single-board microcomputer is generally stored in the ROM. This program interprets
the information entered through a keyboard and provides equivalent binary digits to the
microprocessor. Programs stored in the ROM can only be read; they cannot be altered.
2. The Read/Write memory (RIWM) is also known as user memory It is used to store user
programs and data. In single-board microcomputers, the monitor program monitors the Hex
keys and stores those instructions and data in the R/W memory. The information stored in
this memory can be easily read and altered.
I/O (Input/Output): It communicates with the outside world. I/O includes two types of
devices: input and output; these I/O devices are also known as peripherals.
System Bus: The system bus is a communication path between the microprocessor and
peripherals: it is nothing but a group of wires to carry bits.
Applications of microprocessors:
Microprocessor is a multi-use device which finds applications in almost all the fields.Here is
some sample applications given in variety of fields.
Electronics:

Digital clocks & Watches

Mobile phones

Measuring Meters
Mechanical:

Automobiles

Lathes

All remote machines
Electrical:

Motors

Lighting controls

Power stations
Medical:

Patient monitoring

Most of the Medical equipments

Data loggers
Computer:

All computer accessories

Laptops & Modems

Scanners & Printers
Domestic:

Microwave Ovens

Television/CD/DVD players

Washing Machines
PIN DIAGRAM AND PIN DESCRIPTION OF 8085

8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows :
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
1. Power supply and Clock frequency signals:





Vcc
+ 5 volt power supply
Vss
Ground
X1, X2 : Crystal or R/C network or LC network connections to set the frequency of
internal clock generator.
The frequency is internally divided by two. Since the basic operating timing frequency is
3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.
2. Address Bus:


A8 - A15 (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
3. Multiplexed Address / Data Bus:





AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower
order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.
4. Control and Status signals:










ALE (output) - Address Latch Enable.
This signal helps to capture the lower order address presented on the multiplexed address
/ data bus.
RD (output 3-state, active low) - Read memory or IO device.
This indicates that the selected memory location or I/O device is to be read and that the
data bus is ready for accepting data from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device.
This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.
IO/M (output) - Select memory or an IO device.
This status signal indicates that the read / write operation relates to whether the memory
or I/O device.
It goes high to indicate an I/O operation.
It goes low for memory operations.
5. Status Signals:

It is used to know the type of current operation of the microprocessor.

The microprocessor is a clock-driven semiconductor device consisting of electronic logic
circuits manufactured by using either a large-scale integration (LSI) or very-large-scale
integration (VLSI) technique.

The microprocessor is capable of performing various computing functions and making
decisions to change the sequence of program execution.

In large computers, a CPU implemented on one or more circuit boards performs these
computing functions.

The microprocessor is in many ways similar to the CPU, but includes the logic circuitry,
including the control unit, on one chip.

The microprocessor can be divided into three segments for the sake clarity,
arithmetic/logic unit (ALU), register array, and control unit.
6. Interrupts and Externally initiated operations:


They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
There are five hardware interrupts called,
On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low
INTA (Interrupt Acknowledge) signal.
Reset In (input, active low)
This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.
The buses are tri-stated.
Reset Out (Output)
It indicates CPU is being reset.
Used to reset all the connected devices when the microprocessor is reset.
7. Direct Memory Access (DMA):
Tri state devices:
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1,
otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters
into a high impedance state.
Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.






For both high and low states, the output Q draws a current from the input of the OR gate.
When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.
When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the
one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an
I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer
of data.
READY (input)




Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:



SID (input)
- Serial input data line
SOD (output)
- Serial output data line
These signals are used for serial communication.
Architechture of 8085 Microprocessor:
8085 Bus Structure:
Address Bus:



The address bus is a group of 16 lines generally identified as A0 to A15.
The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral
devices.
The MPU uses the address bus to perform the first function: identifying a peripheral or a
memory location.
Data Bus:





The data bus is a group of eight lines used for data flow.
These lines are bi-directional - data flow in both directions between the MPU and
memory and peripheral devices.
The MPU uses the data bus to perform the second function: transferring binary
information.
The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =
256 numbers).
The largest number that can appear on the data bus is 11111111.
Control Bus:


The control bus carries synchronization signals and providing timing signals.
The MPU generates specific control signals for every operation it performs. These signals
are used to identify a device type with which the MPU wants to communicate.
Registers of 8085:



The 8085 have six general-purpose registers to store 8-bit data during program execution.
These registers are identified as B, C, D, E, H, and L.
They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.
Accumulator (A):



The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical operations.
The result of an operation is stored in the accumulator.
Flags:



The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most commonly used flags are Sign, Zero, and Carry.
The bit position for the flags in flag register is,
1.Sign Flag (S):
After execution of any arithmetic and logical operation, if D7 of the result is 1, the signflag
is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the
magnitude of number.
If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be
viewed as positive number.
2.Zero Flag (z):
If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is
reset.
3.Auxiliary Carry Flag (AC):
If D3 generates any carry when doing any arithmetic and logical operation, this flag is
set. Otherwise it is reset.
4.Parity Flag (P):
If the result of arithmetic and logical operation contains even number of 1's then this flag
will be set and if it is odd number of 1's it will be reset.
5.Carry Flag (CY):
If any arithmetic and logical operation result any carry then carry flag is set otherwise it is
reset.
Arithmetic and Logic Unit (ALU):

It is used to perform the arithmetic operations like addition, subtraction, multiplication,
division, increment and decrement and logical operations like AND, OR and EX-OR.

It receives the data from accumulator and registers.

According to the result it set or reset the flags.
Program Counter (PC):

This 16-bit register sequencing the execution of instructions.

It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.

The function of the program counter is to point to the memory address of the next
instruction to be executed.

When an opcode is being fetched, the program counter is incremented by one to point to
the next memory location.
Stack Pointer (Sp):

The stack pointer is also a 16-bit register used as a memory pointer.

It points to a memory location in R/W memory, called the stack.

The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).
Timing and Control unit:

It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.

ALE is used for provide control signal to synchronize the components of microprocessor
and timing for instruction to perform the operation.

RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.

IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
Interrupt Control Unit:

It receives hardware interrupt signals and sends an acknowledgement for receiving the
interrupt signal.
Demultiplexing AD7-AD0
–
–
–
From the above description, it becomes obvious that the AD7– AD0 lines are
serving a dual purpose and that they need to be demultiplexed to get all the
information.
The high order bits of the address remain on the bus for three clock periods.
However, the low order bits remain for only one clock period and they would be
lost if they are not saved externally. Also, notice that the low order bits of the
address disappear when they are needed most.
To make sure we have the entire address for the full three clock cycles, we will
use an external latch to save the value of AD7– AD0 when it is carrying the
address bits. We use the ALE signal to enable this latch.
8085
A15-A8
ALE
AD7-AD0
Latch
A7- A0
D7- D0
•
Given that ALE operates as a pulse during T1, we will be able to latch the address. Then
when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their
purpose as the bi-directional data lines.
Generation of control signals:
•
The 8085 generates a single RD signal. However, the signal needs to be used with both
memory and I/O. So, it must be combined with the IO/M signal to generate different
control signals for the memory and I/O.
– Keeping in mind the operation of the IO/M signal we can use the following circuitry
to generate the right set of signals:
Timing diagram:
Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states.
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle:
The time required to access the memory or input/output devices is called machine cycle.
T-State:


The machine cycle and instruction cycle takes multiple clock periods.
A portion of an operation carried out in one system clock period is called as T-state.

Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when
the 8085 processor executes an instruction, it will execute some of the machine cycles in
a specific order.

The processor takes a definite time to execute the machine cycles. The time taken by the
processor to execute a machine cycle is expressed in T-states.

One T-state is equal to the time period of the internal clock signal of the processor.

The T-state starts at the falling edge of a clock.
Opcode fetch machine cycle of 8085 :





Each instruction of the processor has one byte opcode.
The opcodes are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
Hence, every instruction starts with opcode fetch machine cycle.
The time taken by the processor to execute the opcode fetch cycle is 4T.
In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.
Fig - Timing Diagram for Opcode Fetch Machine Cycle
UNIT-II
INSTRUCTION SET & ADDRESSING MODES
The 8085 instruction set can be classified into the following five functional headings.
1. DATA TRANSFER INSTRUCTIONS:
It includes the instructions that move (copies) data between registers or between memory
locations and registers. In all data transfer operations the content of source register is not altered.
Hence the data transfer is copying operation.
Ex: (1) Mov A,B (2) MVI C,45H
2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction, increment or decrement
operations. The flag conditions are altered after execution of an instruction in this group.
Ex: (1) ADD A,B (2) SUI B,05H
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, EXCLUSIVE- OR,
complement, compare and rotate instructions are grouped under this heading. The flag conditions
are altered after execution of an instruction in this group.
Ex: (1) ORA A (2) ANI B, 01H
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory location to
another memory location are grouped under this heading.
Ex: (1) CALL (2) JMP 4100
5. MACHINE CONTROL INSTRUCTIONS:
It includes the instructions related to interrupts and the instruction used to stop the program
execution.
Ex: (1) NOP (2) END
Addressing modes of 8085:



Every instruction of a program has to operate on a data.
The method of specifying the data to be operated by the instruction is called Addressing.
The 8085 has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
1. Immediate Addressing:


In immediate addressing mode, the data is specified in the instruction itself. The data will
be a part of the program instruction.
EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP,
2700H.
2. Direct Addressing:


In direct addressing mode, the address of the data is specified in the instruction. The data
will be in memory. In this addressing mode, the program instructions and data can be
stored in different memory.
EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator;
SHLD 3000H
3. Register Addressing:


In register addressing mode, the instruction specifies the name of the register in which the
data is available.
EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.
4. Register Indirect Addressing:


In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. Here the data will be in memory and the
address will be in the register pair.
EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX
B.
5. Implied Addressing:


In implied addressing mode, the instruction itself specifies the data to be operated.
EX. CMA - Complement the content of accumulator; RAL
DATA TRANSFER INSTRUCTIONS
Opcode Operand
MOV
Rd, Rs
Explanation of
Instruction
Description
Copy from
source(Rs) to
This instruction copies the contents of the source
register into the destination register; the contents of the
source register are not altered. If one of the operands is
M, Rs
destination(Rd)
a memory location, its location is specified by the
contents of the HL registers.
Rd, M
MVI
Rd, data
M, data
LDA
LDAX
LXI
16-bit
address
B/D Reg.
pair
Reg. pair,
16-bit data
Example: MOV B, C or MOV B, M
The 8-bit data is stored in the destination register or
memory. If the operand is a memory location, its
Move immediate 8location is specified by the contents of the HL
bit
registers.
Load accumulator
Load accumulator
indirect
Load register pair
immediate
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a 16bit address in the operand, are copied to the
accumulator. The contents of the source are not altered.
Example: LDA 2034H
The contents of the designated register pair point to a
memory location. This instruction copies the contents
of that memory location into the accumulator. The
contents of either the register pair or the memory
location are not altered.
Example: LDAX B
The instruction loads 16-bit data in the register pair
designated in the operand.
Example: LXI H, 2034H or LXI H, XYZ
LHLD
16-bit
address
Load H and L
registers direct
The instruction copies the contents of the memory
location pointed out by the 16-bit address into register
L and copies the contents of the next memory location
into register H. The contents of source memory
locations are not altered.
Example: LHLD 2040H
STA
16-bit
address
16-bit address
The contents of the accumulator are copied into the
memory location specified by the operand. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address.
Example: STA 4350H
STAX
Reg. pair
Store accumulator The contents of the accumulator are copied into the
memory location specified by the contents of the
indirect
operand (register pair). The contents of the
accumulator are not altered.
SHLD
XCHG
SPHL
XTHL
16-bit
address
none
none
none
Store H and L
registers direct
Example: STAX B
The contents of register L are stored into the memory
location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
contents of registers HL are not altered. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address.
Example: SHLD 2470H
The contents of register H are exchanged with the
Exchange H and L contents of register D, and the contents of register L
are exchanged with the contents of register E.
with D and E
Example: XCHG
The instruction loads the contents of the H and L
registers
into
the
stack
pointer
register,
the
contents
of
the
H
register
Copy H and L
provide the high-order address and the contents of the
registers to the stack L register provide the low-order address. The contents
pointer
of
the
H
and L registers are not altered.
Example: SPHL
The contents of the L register are exchanged with the
stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
Exchange H and L
exchanged with the next stack location (SP+1);
with top of stack however, the contents of the stack pointer register are
not altered.
Example: XTHL
PUSH
Reg. pair
Push register pair
onto stack
The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is decremented
and the contents of the highorder register (B, D, H, A)
are copied into that location. The stack pointer register
is decremented again and the contents of the low-order
register (C, E, L, flags) are copied to that location.
Example: PUSH B or PUSH A
POP
Reg. pair
The contents of the memory location pointed out by the
stack pointer register are copied to the low-order
register (C, E, L, status flags) of the operand. The stack
pointer is incremented by 1 and the contents of that
memory location are copied to the high-order register
(B, D, H, A) of the operand. The stack pointer register
is again incremented by 1.
Pop off stack to
register pair
Example: POP H or POP A
OUT
IN
8-bit port
address
Output data from
accumulator to a
port with 8-bit
address
The contents of the accumulator are copied into the
I/O port specified by the operand.
Example: OUT F8H
Input data to
The contents of the input port designated in the
8-bit port accumulator from a
operand are read and loaded into the accumulator.
port with 8-bit
address
address
Example: IN 8CH
ARITHMETIC INSTRUCTIONS
Opcode Operand
R
ADD
M
Explanation of
Instruction
Add register or
memory, to
accumulator
Description
The contents of the operand (register or memory) are
added to the contents of the accumulator and the result is
stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the
addition.
Example: ADD B or ADD M
ADC
R
M
Add register to The contents of the operand (register or memory) and M
accumulator with the Carry flag are added to the contents of the accumulator
and the result is stored in the accumulator. If the operand
carry
is a memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the addition.
ADI
ACI
LXI
Example: ADC B or ADC M
The 8-bit data (operand) is added to the contents of the
Add immediate to accumulator and the result is stored in the accumulator.
8-bit data
All flags are modified to reflect the result of the addition.
accumulator
Example: ADI 45H
The 8-bit data (operand) and the Carry flag are added to
Add immediate to the contents of the accumulator and the result is stored in
8-bit data accumulator with the accumulator. All flags are modified to reflect the result
of the addition.
carry
Example: ACI 45H
The instruction loads 16-bit data in the register pair
Reg. pair, Load register pair
designated in the operand.
immediate
16-bit data
Example: LXI H, 2034H or LXI H, XYZ
DAD
Reg. pair
The 16-bit contents of the specified register pair are added
Add register pair to the contents of the HL register and the sum is stored in
the HL register. The contents of the source register pair
to H and L
are not altered. If the result is larger than 16 bits, the CY
registers
flag is set. No other flags are affected.
Example: DAD H
SUB
R
M
The contents of the operand (register or memory ) are
subtracted from the contents of the accumulator, and the
Subtract register result is stored in the accumulator. If the operand is a
or memory from memory location, its location is specified by the contents
of the HL registers. All flags are modified to reflect the
accumulator
result of the subtraction.
Example: SUB B or SUB M
R
SBB
M
The contents of the operand (register or memory ) and M
the Borrow flag are subtracted from the contents of the
Subtract source accumulator and the result is placed in the accumulator. If
and borrow from the operand is a memory location, its location is specified
by the contents of the HL registers. All flags are modified
accumulator
to reflect the result of the subtraction.
Example: SBB B or SBB M
SUI
8-bit data
Subtract
The 8-bit data (operand) is subtracted from the contents of
the accumulator and the result is stored in the
immediate from accumulator. All flags are modified to reflect the result of
the subtraction.
accumulator
Example: SUI 45H
SBI
Subtract
The contents of register H are exchanged with the contents
immediate from of register D, and the contents of register L are exchanged
8-bit data
accumulator with with the contents of register E.
borrow
Example: XCHG
R
INR
M
INX
R
R
DCR
M
DCX
DAA
R
none
The contents of the designated register or memory) are
incremented by 1 and the result is stored in the same
Increment register
place. If the operand is a memory location, its location is
or memory by 1 specified by the contents of the HL registers.
Example: INR B or INR M
The contents of the designated register pair are
Increment register incremented by 1 and the result is stored in the same
place.
pair by 1
Decrement
register or
memory by 1
Example: INX H
The contents of the designated register or memory are M
decremented by 1 and the result is stored in the same
place. If the operand is a memory location, its location is
specified by the contents of the HL registers.
Example: DCR B or DCR M
The contents of the designated register pair are
decremented by 1 and the result is stored in the same
Decrement
register pair by 1 place.
Decimal adjust
accumulator
Example: DCX H
The contents of the accumulator are changed from a
binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the auxiliary
flag to perform the binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY
flags are altered to reflect the results of the operation.
If the value of the low-order 4-bits in the accumulator is
greater than 9 or if AC flag is set, the instruction adds 6 to
the low-order four bits.
If the value of the high-order 4-bits in the accumulator is
greater than 9 or if the Carry flag is set, the instruction
adds 6 to the high-order four bits.
Example: DAA
BRANCHING INSTRUCTIONS
Opcode
Operand
16-bit
address
JMP
Explanation of
Instruction
Description
The
program
sequence
is
transferred to the memory location
Jump
specified by the 16-bit address
unconditionally given in the operand.
Example: JMP 2034H or JMP
XYZ
Opcode
Flag
Status
Description
JC
Jump on Carry CY = 1
JNC
Jump
Carry
JP
Jump
positive
on
no
on
CY = 0
S=0
JM
Jump on minus S = 1
JZ
Jump on zero
JNZ
Jump on no zero Z = 0
JPE
Jump on parity
P=1
even
JPO
Jump on parity
P=0
odd
16-bit
address
Jump
conditionally
The
program
sequence
is
transferred to the memory location
specified by the 16-bit address
given in the operand based on the
specified flag of the PSW as
described below.
Z=1
Example: JZ 2034H or JZ XYZ
Description
Flag
Status
CC
Call on Carry
CY = 1
CNC
Call
on
Carry
CP
Call on positive S = 0
CM
Call on minus
S=1
CZ
Call on zero
Z=1
CNZ
Call on no zero Z = 0
CPE
Call on parity
P=1
even
CPO
Call on parity
P=0
odd
Opcode
no
CY = 0
RET
16-bit
address
The
program
sequence
is
transferred to the memory location
specified by the 16-bit address
given in the operand. Before the
Unconditional transfer, the address of the next
subroutine call instruction after CALL (the
contents of the program counter) is
pushed onto the stack.
Example: CALL 2034H or CALL
XYZ
none
The
program
sequence
is
transferred from the subroutine to
Return from the calling program. The two bytes
from the top of the stack are copied
subroutine
into the program counter,and
unconditionally program execution begins at the
new address.
Example: RET
Opcode
Flag
Status
Description
RC
Return on Carry CY = 1
RNC
Return
Carry
RP
Return
positive
on
no
on
none
CY = 0
Return from
subroutine
conditionally
The
program
sequence
is
transferred from the subroutine to
the calling program based on the
specified flag of the PSW as
described below. The two bytes
from the top of the stack are copied
into the program counter, and
program execution begins at the
new address.
S=0
Example: RZ
RM
Return on minus S = 1
RZ
Return on zero
Z=1
RNZ
Return
zero
Z=0
RPE
Return on parity
P=1
even
RPO
Return on parity
P=0
odd
on
PCHL
RST
no
none
0-7
The contents of registers H and L
are copied into the program
Load program counter. The contents of H are
counter with HL placed as the high-order byte and
the contents of L as the low-order
contents
byte.
Restart
Example: PCHL
The RST instruction is equivalent
to a 1-byte call instruction to one of
eight memory locations depending
upon the number. The instructions
are generally used in conjunction
with interrupts and inserted using
external hardware. However these
can be used as software instructions
in a program to transfer program
execution to one of the eight
locations. The addresses are:
Instruction
Restart
Address
RST 0
0000H
RST1
0008H
RST 2
0010H
RST 3
0018H
RST 4
0020H
RST 5
0028H
RST 6
0030H
RST 7
0038H
The 8085 has four additional
interrupts and these interrupts
generate RST instructions internally
and thus do not require any external
hardware. These instructions and
their Restart addresses are:
Interrupt
Restart
Address
TRAP
0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH
LOGICAL INSTRUCTIONS
Opcode Operand
CMP
R
M
Explanation of
Instruction
Description
Compare register
or memory with
accumulator
The contents of the operand (register or memory) are M
compared with the contents of the accumulator. Both
contents are preserved . The result of the comparison is
shown by setting the flags of the PSW as follows:
if
(A)
<
(reg/mem):
carry
flag
is
if
(A)
=
(reg/mem):
zero
flag
is
if (A) > (reg/mem): carry and zero flags are reset
CPI
8-bit
data
set
set
Example: CMP B or CMP M
The second byte (8-bit data) is compared with the contents
of the accumulator. The values being compared remain
unchanged. The result of the comparison is shown by
setting the flags of the PSW as follows:
Compare
immediate with
if
(A)
<
data:
carry
flag
accumulator
if
(A)
=
data:
zero
flag
if (A) > data: carry and zero flags are reset
is
is
set
set
Example: CPI 89H
ANA
R
M
Logical AND
register or
memory with
accumulator
The contents of the accumulator are logically ANDed with
M the contents of the operand (register or memory), and
the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANA B or ANA M
ANI
XRA
8-bit
data
R
M
XRI
8-bit
data
The contents of the accumulator are logically ANDed with
Logical AND the
8-bit data (operand) and the result is placed in the
immediate with accumulator. S, Z, P are modified to reflect the result of the
accumulator
operation. CY is reset. AC is set.
Exclusive OR
register or
memory with
accumulator
Example: ANI 86H
The contents of the accumulator are Exclusive ORed with
M the contents of the operand (register or memory), and
the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRA B or XRA M
The contents of the accumulator are Exclusive ORed with
Exclusive OR the 8-bit data (operand) and the result is placed in the
immediate with accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
accumulator
Example: XRI 86H
ORA
R
M
ORI
8-bit
data
Logical OR
register or
memory with
accumulator
The contents of the accumulator are logically ORed with M
the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORA B or ORA M
The contents of the accumulator are logically ORed with
Logical OR
the 8-bit data (operand) and the result is placed in the
immediate with accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
accumulator
Example: ORI 86H
RLC
RRC
RAL
none
none
none
Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in
Rotate
the Carry flag. CY is modified according to bit D7. S, Z, P,
accumulator left AC are not affected.
Example: RLC
Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in
Rotate
the Carry flag. CY is modified according to bit D0. S, Z, P,
accumulator right AC are not affected.
Example: RRC
Each binary bit of the accumulator is rotated left by one
position through the Carry flag. Bit D7 is placed in the
Rotate
Carry flag, and the Carry flag is placed in the least
accumulator left significant position D0. CY is modified according to bit
through carry D7. S, Z, P, AC are not affected.
Example: RAL
RAR
none
Each binary bit of the accumulator is rotated right by one
position through the Carry flag. Bit D0 is placed in the
Rotate
Carry flag, and the Carry flag is placed in the most
accumulator right significant position D7. CY is modified according to bit
through carry D0. S, Z, P, AC are not affected.
Example: RAR
CMA
none
Complement
accumulator
The contents of the accumulator are complemented. No
flags are affected.
Example: CMA
CMC
none
Complement
carry
The Carry flag is complemented. No other flags are
affected.
Example: CMC
STC
none
Set Carry
Set Carry
Example: STC
CONTROL INSTRUCTIONS
Opera
Opcode
nd
NOP
Explanation
of
Instruction
Description
No operation is performed. The instruction is fetched and
none No operation decoded. However no operation is executed.
Example: NOP
HLT
none
Halt and
enter wait
state
The CPU finishes executing the current instruction and halts
any further execution. An interrupt or reset is necessary to exit
from the halt state.
DI
none
Example: HLT
T
the
interrupt enable flip-flop is reset and all the in
Disable teinterrupts except the TRAP are disabled. No flags are
interrupts afaffected.
Example: DI
EI
none
Enable
interrupts
The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flipflop
is reset, thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI
This is a multipurpose instruction used to read the status of
interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the
following interpretations.
RIM
none
Read
interrupt
mas
Example: RIM
This is a multipurpose instruction and used to implement the
8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM
SIM
none
Set interrupt
mask
Memory Read Machine Cycle of 8085:

The memory read machine cycle is executed by the processor to read a data byte from
memory.


The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine cycle
after the opcode fetch machine cycle.
Fig- Timing Diagram for Memory Read Machine Cycle
Memory Write Machine Cycle of 8085:


The memory write machine cycle is executed by the processor to write a data byte in a
memory location.
The processor takes, 3T states to execute this machine cycle.
Fig - Timing Diagram for Memory Write Machine Cycle
Programs
Addition of two 8-bit numbers program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
ADD M : Add second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H
HLT : Terminate program execution
Flowchart:
Subtraction of two 8-bit numbers program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
SUB M : Subtract second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H
HLT : Terminate program execution
SYLLABUS
: INTERFACING CONCEPTS
Peripheral I/O instructions – device selection and data transfer – Input Interfacing
– Practical Input interfacing using decoders – Interfacing O/P Devices: LED and 7
segment Display – Interfacing memory – Memory
time and unit states.
8085 I/O INTERFACING
I/O STRUCTURE OF A TYPICAL MICROCOMPUTER:
There are three major types of data transfer between the microcomputer and art I/O device. They
are,



Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O
port and controlled by software.
Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor,
and initiate data transfer.
Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can
be performed by bypassing the microprocessor.
INTERFACING I/O AND PERIPHERAL DEVICES:
1. For data transfer from input device to processor the following operations are performed.




The input device will load the data to the port.
When the port receives a data, it sends message to the processor to read the data.
The processor will read the data from the port.
After a data have been read by the processor the input device will load the next data into
the port.
2. For data transfer from processor to output device the following operations are performed.

The processor will load the data to the port.










The port will send a message to the output device to read the data.
The output device will read the data from the port.
After the data have been read by the output device the processor can load the next data to
the port.
The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755.
8212
The 8212 is a 24 pin IC.
It consists of eight number of D-type latches.
It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8
The 8212 can be used as an input or output device
It has two selecting device DS1 (low) and DS2.
Fig - Internal address of 8155
8155:

It has two numbers of 8-bit parallel I/O port (port-A and B)




One number of 6-bit parallel I/O port (port-C).
It has 14 bit timer (operating in 4 modes).
It has six internal addresses.
It has one chip select pin CS (low).
8156:





It has two numbers of 8-bit parallel I/O port (port-A and B)
One number of 6-bit parallel 1 port (port-C).
It has 14 bit timer (operating in 4 modes).
It has six internal addresses.
It has one chip select pin CS (low).
Fig - Internal address of 8156
8255:






It has 3 numbers of 8-bit parallel I/O ports (port A, B and C).
Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port.
Port-B can be programmed in mode-1 and mode-2 as 1/Oport.
When ports A and B are in mode-0, the port-C can be used as I/O port.
One logic low chip select (CS) pin.
It requires four internal addresses
8355:




It has 2KB ROM.
It has two number of 8 bit port (A,B).
It has one CS(low).
It has four internal addresses.
8755:



It has 2Kb EPROM.
It has two number of 8 bit port (A,B).
It has one CS(low).

It has four internal addresses.
Fig - Internal address of 8255
Fig - Internal address of 8355
Fig - Internal address of 8755
Fig - Internal address of 8255
Fig - Memory and I/O Port Interfacing with 8085
7 SEGMENT LED INTERFACING
Statement: Interface an 8-digit 7 segment LED display using 8255 to the 8085 microprocessor
system and write an 8085 assembly language routine to display message on the display.
HARDWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY INTERFACE
Fig. shows the multiplexed eight 7-segment display connected in the 8085 system using 8255. In
this circuit port A and port B are used as simple latched output ports. Port A provides the
segment data inputs to the display and port B provides a means of selecting a display position at
a time for multiplexing the displays. A0-A7 lines are used to decode the addresses for 8255. For
this circuit different addresses are:
PA = 00H PB = 01H
PC = 02H CR = 03H.
The register values are chosen in Fig. such that the segment current is 80 mA. This current is
required to produce an average of 10 mA per segment as the displays are multiplexed. In this
type of display system, only one of the eight display position is 'ON' at any given instant. Only
one digit is selected at a time by giving low signal on the corresponding control line. Maximum
anode current is 560 mA (7-segments x 80 mA = 560 mA), but the average anode current is 70
mA.
INTERFACING SCHEME
SOFTWARE FOR EIGHT DIGIT SEVEN SEGMENT DISPLAY
For 8255, Port A and B are used as output ports. The control word format of 8255
according to hardware connections is:
Source program:



SOFTWARE TO INITIALIZE 8255:
MVI A, 80H : Load control word in AL
OUT CR : Load control word in CR
SUBROUTINE TO DISPLAY MESSAGE ON MULTIPLEXED LED DISPLAY:
SET UP REGISTERS FOR DISPLAY:



MVI B, 08H : load count
MVI C, 7FH : load select pattern
LXI H, 6000B : starting address of message
DISPLAY MESSAGE:












DISP 1: MOV A, C : select digit
OUT PB
MOV A, M : get data
OUT PA : display data
CALL DELAY : wait for some time
DISP 1: MOV A, C
RRC
MOV C, A : adjust selection pattern
INX H
DCR B : Decrement count
JNZ DISP 1 : repeat 8 times
RET
Note: This "display message subroutine" must be called continuously to display the 7-segment coded
message stored in the memory from address 6000H.
Delay Subroutine:


Delay: LXI D, Count
Back: DCX D




MOV A, D
ORA E
JNZ Back
RET
MEMORY INTERFACING WITH 8085
TYPICAL EPROM AND STATIC RAM:

A typical semiconductor memory IC will have n address pins, m data pins (or
output pins).

Having two power supply pins (one for connecting required supply voltage (V and
the other for connecting ground).

The control signals needed for static RAM are chip select (chip enable), read control
(output enable) and write control (write enable).

The control signals needed for read operation in EPROM are chip select (chip
enable) and read control (output enable).
DECODER:
It is used to select the memory chip of processor during the execution of a program. No of
IC's used for decoder is,

2-4 decoder (74LS139)

3-8 decoder (74LS138)
Table - Number of Address Pins and Data Pins in Memory ICs
Examples of Memory Interfacing..(Contd) - Page2
Fig - Block diagram and Truth table of 2-4 decoder
Fig - Block diagram and Truth table of 3-8 decoder
SYLLABUS
:
PARALLEL AND SERIAL INTERFACE
Introduction to programmable Peripheral Interface 8255 – Pin Diagram – Architecture – Modes
of Operation: I/O and BSR – Architecture and operation of 8251 (USART).
INTERRUPT AND TIMER LOGIC
8085 interrupts - Architecture of programmable interrupt controller 8259 –– Architecture of 8254
Programmable Interval timer / counter – Modes of Operation of 8254 – Generating square wave
using 8254.
APPLICATIONS
Time delay program – Traffic Light Control System – Water Level Controller – Stepper Motor
Control –Interfacing DAC – Interfacing ADC – Temperature measurement.
Programmable Peripheral Interface (PPI)
Data Bus BuffeThis three-state bi-directional 8-bit buffer is used to interface the 8255 to the
system data bus. Data is transmitted or received by the buffer upon execution of input or output
instructions by the CPU. Control words and status informa-tion are also transferred through the
data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and
Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn,
issues commands to both of the Control Groups.
(CS) Chip Select. A "low" on this input pin enables the communcation between the 8255 and the
CPU.
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information to the
CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
(WR) Write. A "low" on this input pin enables the CPU to write data or control words into the
8255.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and
WR inputs, control the selection of one of the three ports or the control word register. They are
normally connected to the least significant bits of the address bus (A0 and A1).
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports (A, B,
C) are set to the input mode.
A1
A0
SELECTION
0
0
PORT A
0
1
PORT B
1
0
PORT C
1
1
CONTROL
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the
CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each
of the Control blocks (Group A and Group B) accepts "commands" from the Read/Write Control
logic, receives "control words" from the internal data bus and issues the proper commands to its
associated ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of
functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and
"pull-down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input).
This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a
4-bit latch and it can be used for the control signal output and status signal inputs in conjunction
with ports A and B.
Block Diagram of the 8255 Programmable Peripheral Interface (PPI)
Mode Definition Format
Features:

3 8-bit IO ports PA, PB, PC

PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and
2 are interrupt driven.

PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently
for I or O. Each PC bit can be set/reset individually in BSR mode.

PA and PCU are Group A (GA) and PB and PCL are Group B (GB)

Address/data bus must be externally demux'd.

TTL compatible.

Improved dc driving capability
Pinout
A1 A0 Select
0 0 PA
0 1 PB
1 0 PC
1 1 Control reg.
Block diagram
BSR mode
Bit set/reset, applicable to PC only. One bit is S/R at a time. Control word:
D7
D6
D5
D4
D3
D2
D1
D0
0 (0=BSR)
X
X
X
B2
B1
B0
S/R (1=S,0=R)
Bit select: (Taking Don't care's as 0)
B2 B1 B0 PC bit Control word (Set) Control word (reset)
0
0
0
0
0000 0001 = 01h
0000 0000 = 00h
0
0
1
1
0000 0011 = 03h
0000 0010 = 02h
0
1
0
2
0000 0101 = 05h
0000 0100 = 04h
0
1
1
3
0000 0111 = 07h
0000 0110 = 06h
1
0
0
4
0000 1001 = 09h
0000 1000 = 08h
1
0
1
5
0000 1011 = 0Bh 0000 1010 = 0Ah
1
1
0
6
0000 1101 = 0Dh 0000 1100 = 0Ch
1
1
1
7
0000 1111 = 0Fh
0000 1110 = 0Eh
I/O mode
D7
D6
D5
D4
D3
D2
D1
D0
1 (1=I/O)
GA mode select
PA
PCU
GB mode select
PB
PCL

D6, D5: GA mode select:
o
00 = mode0
o
01 = mode1
o
1X = mode2

D4(PA), D3(PCU): 1=input 0=output

D2: GB mode select: 0=mode0, 1=mode1

D1(PB), D0(PCL): 1=input 0=output
Mode 0: No interrupts. Plain I/O. Two 8 bit ports PA, PB. Two 4 bit ports PCU and PCL.
Outputs latched, inputs buffered.
Mode 1
(Input and output data are latched)
PC bits in input mode:
D7
D6
PC7
PC6
D5
D4
D3
D2
IBF- INTE-A / STB- INTR- INTE-B / STBA
A-bar
A
B-bar
D5
D4
D3
D2
D1
IBF-B
D0
INTRB
PC bits in output mode:
D7
D6
OBF-A- INTE-A / ACKbar
A-bar
PC5 PC4
D1
D0
INTR- INTE-B / ACK- OBF-B- INTRA
B-bar
bar
B
Input mode:

D4, D2: Set/Reset INTE using BSR. STB-bar input is connected to external peripheral's
strobe output (i.e. PC2, PC4 pin to external strobe).

INTE is internal connection. STB-bar is external connection.
Output mode:

D6, D2: Set/Reset INTE using BSR. ACK-bar input is connected to external peripheral's
acknowledge output (i.e. PC2, PC6 pin to external ack).

INTE is internal connection. ACK-bar is external connection.
Mode 2
Only for PA
Status:
D7
OBF-A-bar
D6
INTE1(O/P)
ACK-A-BAR
D5
/
IBF-A
D4
INTE2(I/P)
STB-A-bAR
INTERFACING WITH INTEL 8251A (USART)
/
D3
D2 D1 D0
INTR-A
X
X
X

The 8251A is a programmable serial communication interface chip designed for
synchronous and asynchronous serial data communication.

It supports the serial transmission of data.

It is packed in a 28 pin DIP.
Read/Write control logic:

The Read/Write Control logic interfaces the 8251A with CPU, determines the
functions of the 8251A according to the control word written into its control
register.

It monitors the data flow.

This section has three registers and they are control register, status register and
data buffer.

The active low signals RD, WR, CS and C/D(Low) are used for read/write
operations with these three registers.

When C/D(low) is high, the control register is selected for writing control word or
reading status word.

When C/D(low) is low, the data buffer is selected for read/write operation.

When the reset is high, it forces 8251A into the idle mode.

The clock input is necessary for 8251A for communication with CPU and this clock
does not control either the serial transmission or the reception rate.
Transmitter section:

The transmitter section accepts parallel data from CPU and converts them into
serial data.

The transmitter section is double buffered, i.e., it has a buffer register to hold an 8bit parallel data and another register called output register to convert the parallel
data into serial bits.

hen output register is empty, the data is transferred from buffer to output register.
Now the processor can again load another data in buffer register.

If buffer register is empty, then TxRDY is goes to high.

If output register is empty then TxEMPTY goes to high.

The clock signal, TxC (low) controls the rate at which the bits are transmitted by the
USART.

The clock frequency can be 1,16 or 64 times the baud rate.
Receiver Section:

The receiver section accepts serial data and convert them into parallel data

The receiver section is double buffered, i.e., it has an input register to receive serial
data and convert to parallel, and a buffer register to hold the parallel data.

When the RxD line goes low, the control logic assumes it as a START bit, waits for
half a bit time and samples the line again.

If the line is still low, then the input register accepts the following bits, forms a
character and loads it into the buffer register.

The CPU reads the parallel data from the buffer register.

When the input register loads a parallel data to buffer register, the RxRDY line goes
high.

The clock signal RxC (low) controls the rate at which bits are received by the
USART.

During asynchronous mode, the signal SYNDET/BRKDET will indicate the break
in the data transmission.

During synchronous mode, the signal SYNDET/BRKDET will indicate the reception
of synchronous character.
MODEM Control:

The MODEM control unit allows to interface a MODEM to 8251A and to establish
data communication through MODEM over telephone lines.

This unit takes care of handshake signals for MODEM interface.
Block Diagram:
The functional block diagram of 825 1A consists five sections. They are:

Read/Write control logic

Transmitter

Receiver

Data bus buffer

Modem control.
The functional block diagram is shown in fig:
Functional block diagram of 8251A-USART
8085 INTERRUPTS
Interrupt is signals send by an external device to the processor, to request the processor to
perform a particular task or work.
•
Mainly in the microprocessor based system the interrupts are used for data transfer
between the peripheral and the microprocessor.
•
The processor will check the interrupts always at the 2nd T-state of last machine cycle.
•
If there is any interrupt it accept the interrupt and send the INTA (active low) signal to
the peripheral.
•
The vectored address of particular interrupt is stored in program counter.
•
The processor executes an interrupt service routine (ISR) addressed in program counter.
•
It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts.
•
Hardware
•
Software
Software interrupts:
•
The software interrupts are program instructions. These instructions are inserted at
desired locations in a program.
•
The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for
these interrupts can be calculated as follows.
•
Interrupt number * 8 = vector address
•
For RST 5,5 * 8 = 40 = 28H
•
Vector address for interrupt RST 5 is 0028H
The Table shows the vector addresses of all interrupts.
Hardware interrupts:

An external device initiates the hardware interrupts and placing an appropriate signal at
the interrupt pin of the processor.

If the interrupt is accepted then the processor executes an interrupt service routine.
The 8085 has five hardware interrupts
(1) TRAP
(2) RST 7.5
(3) RST 6.5
(4) RST 5.5
(5) INTR
TRAP:

This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt
enable.

TRAP bas the highest priority and vectored interrupt.

TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and
remain high until it is acknowledged.

In sudden power failure, it executes a ISR and send the data from main memory to
backup memory.

The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives
HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is
recognized).

There are two ways to clear TRAP interrupt.
1.By resetting microprocessor (External signal)
2.By giving a high TRAP ACKNOWLEDGE (Internal signal)
RST 7.5:

The RST 7.5 interrupt is a maskable interrupt.

It has the second highest priority.

It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.

Maskable interrupt. It is disabled by,
1.DI instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.
RST 6.5 and 5.5:

The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high
until it recognized.

Maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.

The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:

INTR is a maskable interrupt. It is disabled by,
1.DI, SIM instruction
2.System or processor reset.
3.After reorganization of interrupt.

Enabled by EI instruction.

Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.

It has lowest priority.

It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high
state until it recognized.

The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.
2. If INTR signal is high, then 8085 complete its current instruction and sends active low
interrupt acknowledge signal, if the interrupt is enabled.
3. In response to the acknowledge signal, external logic places an instruction OPCODE on the
data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles
are generated by the 8085 to transfer the additional bytes into the microprocessor.
4. On receiving the instruction, the 8085 save the address of next instruction on stack and
execute received instruction.
8254 Programmable Interval Timer/Counter

Status read-back command

Counter latch command

Read/write least significant bit (LSB) only, most significant bit (MSB) only, or LSB first
then MSB

Six programmable counter modes
o
Interrupt on terminal count
o
Hardware retriggerable one-shot
o
Rate generator
o
Square wave mode
o
Software-triggered strobe
o
Hardware-triggered strobe (retriggerable)

Binary or binary coded decimal strobe

Developed in VHDL and synthesizes to approximately 5,000 gates

Functionally based on the Intel 82C54 device
Block Diagram
Figure 1 shows the block diagram for the 8254 programmable interval timer/counter
megafunction.
Figure 1. Block Diagram
Description
The 8254 programmable interval time/counter megafunction is a high-performance function that
is designed to solve the common timing control problems in microcomputer system design. It
provides three independent 16-bit counters, and each counter may operate in a different mode.
All modes are software programmable. The 8254 megafunction solves one of the most common
problems in any microcomputer system: the generation of accurate time delays under software
control. Instead of setting up timing loops in software, the 8254 megafunction can be
programmed to match requirements by programming one of the counters for the desired delay.
History
In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its
functionality is included as part of the motherboard's southbridge chipset. In some modern
chipsets, this change may show up as measurable timing differences in accessing a PIT using the
x86 I/O address space. Reads and writes to such a PIT's registers in the I/O address space may
complete much faster.
Newer x86 PITs include a counter through the Advanced Configuration and Power Interface
(ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and
a Time Stamp Counter (TSC) introduced on the Pentium.
Features
The timer has three counters, called channels. Each channel can be programmed to operate in
one of six modes. Once programmed, the channels can perform their tasks independently. The
timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical
function it performs and because so many devices depend on it.
Typical Components
Counters
There are 3 counters (or timers), which are labeled as Counter 0, Counter 1 and Counter 2.
Each counter has 2 input pins - CLK (clock input) and GATE - and 1-pin, OUT, for data output.
The 3 counters are 16-bit down counters independent of each other, and can be easily read by the
CPU.
The first counter (selected by setting A1=A0=0, see Control Word Register below) helps
generate a clock interrupt. The second counter (A1=0, A0=1) assists in generating timing, which
will be used to refresh the DRAM memory. The last counter (A1=1, A0=0) generates tones for
the PC speaker.
Besides the counters, a typical Intel 8253 microchip also contains the following components:
Data/Bus Buffer
This block contains the logic to buffer the data bus to / from the microprocessor, and to the
internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.
Read/Write Logic
The Read/Write Logic block has 5 pins, which are listed below. Notice that /X denotes an active
low signal.

/RD: read signal

/WR: write signal

/CS: chip select signal

A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For example, to
write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Control Word Register
Port
Port
43h
53h
R/W
-
R/W
second
chip
...
This register contains the programmed information which will be sent (by the microprocessor) to
the device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.
To initialize the counters, the microprocessor must write a control word (CW) in this register.
This can be done by setting proper values for the pins of the Read/Write Logic block and then
by sending the control word to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB).
Bit# D7 D6 D5
D4
D3 D2 D1 D0
Short Description
Name SC1 SC0 RW1 RW0 M2 M1 M0 BCD
0
0
x
x
x
x
x
x
Counter 0 at port 40h R/W
0
1
x
x
x
x
x
x
Counter 1 at port 41h R/W
1
0
x
x
x
x
x
x
Counter 2 at port 42h R/W
Counter Latch, value can be read out in the
X
x
0
0
x
x
x
x
way RW1, RW0 was set before. The value is
held until it is read out or overwritten.
X
x
0
1
x
x
x
x
Read/Write bits 0..7 of counter value
X
x
1
0
x
x
x
x
Read/Write bits 8..15 of counter value
X
x
1
1
x
x
x
x
X
x
x
x
0
0
0
x
Mode 0: Interrupt on Terminal Count
X
x
x
x
0
0
1
x
Mode 1: Hardware Retriggerable One-Shot
X
x
x
x
0
1
0
x
Mode 2: Rate Generator
2xRead/2xWrite bits 0..7 then 8..15 of
counter value
X
x
x
x
0
1
1
x
Mode 3: Square Wave
X
x
x
x
1
0
0
x
Mode 4: Software Triggered Strobe
X
x
x
x
1
0
1
x
X
x
x
x
x
x
x
0
X
x
x
x
x
x
x
1
Name 1
1
Mode
5:
Hardware
Triggered
Strobe
(Retriggerable)
Counter
is
a
16
bit
binary
counter(0..65535,FFFFh)
Counter is a 16 bit decimal counter 4 x 4bit
decades(0..9999)
_____ _____
C2 C1 C0 0
count status
1
1
0
1
x
x
x
0
1
1
1
0
x
x
x
0
Couter(C0..C2) value(s) can be read out.
Couter's(C0..C2) state(s) can be read out.
see below Status Byte
1
1
0
0
x
x
x
0
error !
When setting the PIT, the microprocessor first sends a control message, then a count message to
the PIT. The counting process will start after the PIT has received these messages, and, in some
cases, if it detects the rising edge from the GATE input signal.
On PCs the address for timer0 (chip) ist at port 40h..43h like described and the second timer1
(chip) is at 50h..53h. Nowadays[when?] there are used HPET chips instead of 8253 timer chips.
Operation Modes
The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6
modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases
for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable
counting. For mode 5, the rising edge of GATE starts the count. For details on each mode, see
the reference links.
Mode 0 (000): Interrupt on Terminal Count
In this mode, the counter will start counting from the initial COUNT value loaded into it, down
to 0. Counting rate is equal to the input clock frequency.
The OUT pin is set low after the Control Word is written, and counting starts one clock cycle
after the COUNT programmed. OUT remains low until the counter reaches 0, at which point
OUT will be set high until the counter is reloaded or the Control Word is written.The Gate
signal should remain active high for normal counting.If Gate goes low counting get terminated
and current count is latched till Gate pulse goes high again.
Mode 1 (001): Hardware-Triggered One Shot
In this mode 8253 can be used as monostable multivibrator. GATE input is used as trigger input.
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the
one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and
remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in
loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot
pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger.
The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has
no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current
one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with
the new count and the oneshot pulse continues until the new count expires.
Mode 2 (X10): Rate Generator
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a
real-time clock interrupt.
Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT
will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will
then go high again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is
calculated using the following formula:
Value to be loaded into counter =
Note that the values in the COUNT register range from n to 1; the register never reaches zero.
Mode 3 (X11): Square Wave Generator
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the
output will be different from mode 2.
Suppose n is the number loaded into the counter (the COUNT message), the output will be

high for counts, and low for counts, if n is even.

high for counts, and low for counts, if n is odd.
Mode 4 (100): Software Triggered Strobe
After Control Word and COUNT is loaded, the output will remain high until the counter
reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) - after that
the output will become high again.
Mode 5 (101): Hardware Triggered Strobe
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.
After receiving the Control Word and COUNT, the output will be set high. Once the device
detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the
output will go low for one clock cycle - after that it will become high again, to repeat the cycle
on the next rising edge of GATE.
Status Byte
8
bit
The Status Byte is read like a 8 bit counter value (port 40h..42h R).
Bit#
D7
D6
D5
D4
D3
D2
D1
D0
Name output null RW1 RW0
M2
M1
M0 BCD
count
------------------------------------------0
x
x
x
x
x
x
x
Out Pin is 0
1
x
x
x
x
x
x
x
Out Pin is 1
------------------------------------------x
0
x
x
x
x
x
x
The value of the latch is loaded into the counter.
A new value can be written to the latch.
x
1
x
x
x
x
x
x
Counter value is 0.
------------------------------------------x
x
=
=
=
=
=
= like defined in the Control Word Register
Programming Considerations
On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for
their own use. Reprogramming typically happens during video mode changes, when the video
BIOS may be executed, and during system management mode and power saving state changes,
when the system BIOS may be executed. This prevents any serious alternative uses of the timer's
second counter on many x86 systems.
The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical
value of 1193181.8181... Hz, i.e. one third of the NTSC color subcarrier frequency. This is a
holdover of the very first CGA PCs - they derived all necessary frequencies from a single quartz
crystal, and to make TV output possible, this quartz had to run at a multiple of the NTSC color
subcarrier frequency.
As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the
counter is set by sending bytes to the Control, then Data I/O Port registers (the value 36h sent to
port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts
down to zero, then sends a hardware interrupt (IRQ 0, INT 8) to the CPU. The counter then
resets to its initial value and begins to count down again. The fastest possible interrupt frequency
is a little over a megahertz. The slowest possible frequency, which is also the one normally used
by computers running MS-DOS or compatible operating systems, is about 18.2 Hz. Under these
real mode operating systems, the BIOS accumulates the number of INT 0 calls that it receives in
real mode address 0040:006c, which can be read by a program.
As a timer counts down, its value can also be read directly by reading its I/O port twice, first for
the low byte, and then for the high byte. The first read latches the value, so that both bytes read
will belong to one and the same value.
8259 Programmable Interrupt Controller
Features:

8 levels of interrupts.

Can be cascaded in master-slave configuration to handle 64 levels of interrupts.

Internal priority resolver.

Fixed priority mode and rotating priority mode.

Individually maskable interrupts.

Modes and masks can be changed dynamically.

Accepts IRQ, determines priority, checks whether incoming priority > current level being
serviced, issues interrupt signal.

In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector
number.

Polled and vectored mode.

Starting address of ISR or vector number is programmable.

No clock required.
Pinout
D0-D7
RD-bar
Bi-directional, tristated, buffered data lines. Connected to
data bus directly or through buffers
Active low read control
WR-bar Active low write control
A0
Address input line, used to select control register
CS-bar
Active low chip select
Bi-directional, 3 bit cascade lines. In master mode, PIC
CAS0-2
places slave ID no. on these lines. In slave mode, the PIC
reads slave ID no. from master on these lines. It may be
regarded as slave-select.
SP-bar /
EN-bar
INT
Slave program / enable. In non-buffered mode, it is SP-bar
input, used to distinguish master/slave PIC. In buffered
mode, it is output line used to enable buffers
Interrupt line, connected to INTR of microprocessor
INTA-
Interrupt ack, received active low from microprocessor
bar
IR0-7
Asynchronous IRQ input lines, generated by peripherals.
Block diagram
ICW1 (Initialisation Command Word One)
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
A7
A6
A5
1
LTIM
ADI
SNGL
IC4
D0:
IC4:
D1:
SNGL:
0=no
1=Single
ICW4,
PIC,
1=ICW4
0=Cascaded
required
PIC
D2: ADI: Address interval. Used only in 8085, not 8086. 1=ISR's are 4 bytes apart (0200, 0204,
etc)
0=ISR's
are
8
byte
apart
(0200,
0208,
etc)
D3: LTIM: level triggered interrupt mode: 1=All IR lines level triggered. 0=edge triggered
D4-D7: A5-A7: 8085 only. ISR address lower byte segment. The lower byte is
A7 A6 A5 A4 A3 A2 A1 A0
of which A7, A6, A5 are provided by D7-D5 of ICW1 (if ADI=1), or A7, A6 are provided if
ADI=0. A4-A0 (or A5-A0) are set by 8259 itself:
ADI=1 (spacing 4 bytes)
ADI=0 (spacing 8 bytes)
IRQ A7 A6 A5 A4 A3 A2 A1 A0
IRQ A7 A6 A5 A4 A3 A2 A1 A0
IR0 A7 A6 A5 0
0
0
0
0
IR0 A7 A6 0
0
0
0
0
0
IR1 A7 A6 A5 0
0
1
0
0
IR1 A7 A6 0
0
1
0
0
0
IR2 A7 A6 A5 0
1
0
0
0
IR2 A7 A6 0
1
0
0
0
0
IR3 A7 A6 A5 0
1
1
0
0
IR3 A7 A6 0
1
1
0
0
0
IR4 A7 A6 A5 1
0
0
0
0
IR4 A7 A6 1
0
0
0
0
0
IR5 A7 A6 A5 1
0
1
0
0
IR5 A7 A6 1
0
1
0
0
0
IR6 A7 A6 A5 1
1
1
0
0
IR6 A7 A6 1
1
0
0
0
0
IR7 A7 A6 A5 1
1
1
0
0
IR7 A7 A6 1
1
1
0
0
0
ICW2 (Initialisation Command Word Two)
Higher byte of ISR address (8085), or 8 bit vector address (8086).
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
A15
A14
A13
A12
A11
A10
A9
A8
ICW3 (Initialisation Command Word Three)
D7
D6
D5
D4
D3
D2
D1
D0
Master
S7
S6
S5
S4
S3
S2
S1
S0
Slave
0
0
0
0
0
ID3
ID2
ID1
A0
1

Master mode: 1 indicates slave is present on that interrupt, 0 indicates direct interrupt

Slave mode: ID3-ID2-ID1 is the slave ID number. Slave 4 on IR4 has ICW3=04h (0000
0100)
ICW4 (Initialisation Command Word Four)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
SFNM
BUF
M/S
AEOI
Mode

SFNM: 1=Special Fully Nested Mode, 0=FNM

M/S: 1=Master, 0=Slave

AEOI: 1=Auto End of Interrupt, 0=Normal

Mode: 0=8085, 1=8086
OCW1 (Operational Command Word One)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
M7
M6
M5
M4
M3
M2
M1
M0
IRn is masked by setting Mn to 1; mask cleared by setting Mn to 0 (n=0..7)
OCW2 (Operational Command Word Two)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
R
SL
EOI
0
0
L3
L2
L1
R SL EOI Action
0 0
1
0 1
1
1 0
1
Rotate priorities on non-specific EOI
1 0
0
Rotate priorities in auto EOI mode set
0 0
0
Rotate priorities in auto EOI mode clear
1 1
1
1 1
0
EOI
Auto
rotation
of
priorities
(L3L2L1=000)
Specific rotation of priorities (Lowest
Non specific EOI (L3L2L1=000)
Specific EOI command (Interrupt to clear
given by L3L2L1)
Rotate priority on specific EOI command
(resets current ISR bit)
priority ISR=L3L2L1)
Set priority (does not reset current ISR bit)
0 1
0
No operation
OCW3 (Operational Command Word Three)
A0
D7
D6
D5
D4
D3
D2
D1
D0
1
D7
ESMM
SMM
0
1
MODE
RIR
RIS
ESMM SMM Effect
0
X
No effect
1
0
Reset special mask
1
1
Set special mask
Interrupt sequence (single PIC)
1. One or more of the IR lines goes high.
2. Corresponding IRR bit is set.
3. 8259 evaluates the request and sends INT to CPU.
4. CPU sends INTA-bar.
5. Highest priority ISR is set. IRR is reset.
6. 8259 releases CALL instruction on data bus.
7. CALL causes CPU to initiate two more INTA-bar's.
8. 8259 releases the subroutine address, first lowbyte then highbyte.
9. ISR bit is reset depending on mode. 8254 Programmable Interval Timer/Counter
UNIT V
APPLICATIONS
DELAY PROGRAM:

DELAY: LXI D, Count : Load count to give 0.5 sec delay

BACK: DCX D : Decrement counter

MOV A, D

ORA E : Check whether count is 0

JNZ BACK : If not zero, repeat

DCR C : Check if multiplier zero, otherwise repeat

JNZ DELAY

RET : Return to main program
HARDWARE FOR TRAFFIC LIGHT CONTROL
Fig. shows the interfacing diagram to control 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to control lights on W-E road. Actual pin connections
are listed in Table 1 below.
The electric bulbs are controlled by relays. The 8255 pins are used to control relay on-off
action with the help of relay driver circuits. The driver circuit includes 12 transistors to
drive 12 relays. Fig. also shows the interfacing of 8255 to the system.
INTERFACING DIAGRAM
SOFTWARE FOR TRAFFIC LIGHT CONTROL
Source Program 1:

MVI A, 80H : Initialize 8255, port A and port B

OUT 83H (CR) : in output mode

START: MVI A, 09H

OUT 80H (PA) : Send data on PA to glow R1 and R2

MVI A, 24H

OUT 81H (PB) : Send data on PB to glow G3 and G4

MVI C, 28H : Load multiplier count (40ıο) for delay

CALL DELAY : Call delay subroutine

MVI A, 12H

OUT (81H) PA : Send data on Port A to glow Y1 and Y2

OUT (81H) PB : Send data on port B to glow Y3 and Y4

MVI C, 0AH : Load multiplier count (10ıο) for delay

CALL: DELAY : Call delay subroutine

MVI A, 24H

OUT (80H) PA : Send data on port A to glow G1 and G2

MVI A, 09H

OUT (81H) PB : Send data on port B to glow R3 and R4

MVI C, 28H : Load multiplier count (40ıο) for delay

CALL DELAY : Call delay subroutine

MVI A, 12H

OUT PA : Send data on port A to glow Y1 and Y2

OUT PB : Send data on port B to glow Y3 and Y4

MVI C, 0AH : Load multiplier count (10ıο) for delay

CALL DELAY : Call delay subroutine

JMP START
Delay Subroutine:

DELAY: LXI D, Count : Load count to give 0.5 sec delay

BACK: DCX D : Decrement counter

MOV A, D

ORA E : Check whether count is 0

JNZ BACK : If not zero, repeat

DCR C : Check if multiplier zero, otherwise repeat

JNZ DELAY

RET : Return to main program
Stepper Motor Control
Statement: Interface a Stepper Motor to the 8085 microprocessor system and write an 8085
assembly language program to control the Stepper Motor.
HARDWARE FOR STEPPER MOTOR CONTROL
A stepper motor is a digital motor. It can be driven by digital signal. Fig. shows the typical
2 phase motor rated 12V /0.67 A/ph interfaced with the 8085 microprocessor system using
8255. Motor shown in the circuit has two phases, with center-tap winding. The center taps
of these windings are connected to the 12V supply. Due to this, motor can be excited by
grounding four terminals of the two windings. Motor can be rotated in steps by giving
proper excitation sequence to these windings. The lower nibble of port A of the 8255 is used
to generate excitation signals in the proper sequence. These excitation signals are buffered
using driver transistors. The transistors are selected such that they can source rated
current for the windings. Motor is rotated by 1.80 per excitation.
Fig. shows the interfacing diagram to control 12 electric bulbs. Port A is used to control
lights on N-S road and Port B is used to control lights on W-E road. Actual pin connections
are listed in Table 1 below.
SOFTWARE FOR STEPPER MOTOR CONTROL
As port A is used as an output port, control word for 8255 is 80H.
Stepper Motor Control Program:
6000H Excite code DB 03H, 06H, 09H, OCH : This is the code sequence for clockwise rotation
Subroutine to rotate a stepper motor clockwise by 360° - Set the counts:

MVI C, 32H : Set repetition count to 50ıο

START: MVI B, 04H : Counts excitation sequence

LXI H, 6000H : Initialize pointer

BACK1: MOV A, M : Get the Excite code

OUT PORTA : Send Excite code

CALL DELAY : Wait

INX H : Increment pointer

DCR B : Repeat 4 times

JNZ BACK l
Delay Subroutine:

Delay: LXI D, Count

Back: DCX D

MOV A, D

ORA E

JNZ Back

RET
INTERFACING OF DAC0-800 WITH 8085
The DAC0800 can be interfaced to 8085 system bus by using an 8-bit latch and the latch
can be enabled by using one of the chip select signal generated for I/O devices. A simple
schematic for interfacing DAC0800 with 8085 is,

In this schematic the DAC0800 is interfaced using an 8-bit latch 74LS273 to the
system bus.

The 3-to-8 decoder 74LS 138 is used to generate chip select signals for I/O devices.

The address lines A4, A5 and A6 are used as input to decoder.

The address line A7 and the control signal IO/M (low) are used as enable for
decoder.

The decoder will generate eight chip select signals and in this the signal IOCS-7 is
used as enable for latch of DAC.

The I/O address of the DAC is shown in table.

In order to convert a digital data to analog value, the processor has to load the data
to latch.

The latch will hold the previous data until next data is loaded.

The DAC will take definite time to convert the data. The software should take care
of loading successive data only after the conversion time.

The DAC 0800 produces a current output, which is converted to voltage output
using Ito V converter.
INTERFACING OF DAC0-800 WITH 8085
The DAC0800 can be interfaced to 8085 system bus by using an 8-bit latch and the latch
can be enabled by using one of the chip select signal generated for I/O devices. A simple
schematic for interfacing DAC0800 with 8085 is,

In this schematic the DAC0800 is interfaced using an 8-bit latch 74LS273 to the
system bus.

The 3-to-8 decoder 74LS 138 is used to generate chip select signals for I/O devices.

The address lines A4, A5 and A6 are used as input to decoder.

The address line A7 and the control signal IO/M (low) are used as enable for
decoder.

The decoder will generate eight chip select signals and in this the signal IOCS-7 is
used as enable for latch of DAC.

The I/O address of the DAC is shown in table.

In order to convert a digital data to analog value, the processor has to load the data
to latch.

The latch will hold the previous data until next data is loaded.

The DAC will take definite time to convert the data. The software should take care
of loading successive data only after the conversion time.

The DAC 0800 produces a current output, which is converted to voltage output
using Ito V converter.
THE INTERNAL BLOCK DIAGRAM OF ADC0809/ADC0808 :
The various functional blocks of ADC are 8-channel multiplexer, comparator, 256R
resistor ladder, switch tree, successive approximation register, output buffer, address latch
and decoder.

The 8-channel multiplexer can accept eight analog inputs in the range of 0 to 5V and
allow one by one for conversion depending on the 3-bit address input. The channel
selection logic is,

The successive approximation register (SAR) performs eight iterations to determine
the digital code for input value. The SAR is reset on the positive edge of START
pulse and start the conversion process on the falling edge of START pulse.
A conversion process will be interrupted on receipt of new START pulse.
The End-Of-Conversion (EOC) will go low between 0 and 8 clock pulses after the positive
edge of START pulse.
The ADC can be used in continuous conversion mode by tying the EOC output to START
input. In this mode an external START pulse should be applied whenever power is
switched ON.

The 256'R resistor network and the switch tree is shown in fig.

The 256R ladder network has been provided instead of conventional R/2R ladder
because of its inherent monotonic, which guarantees no missing digital codes.

Also the 256R resistor network does not cause load variations on the reference
voltage.

The comparator in ADC0809/ADC0808 is a chopper- stabilized comparator. It
converts the DC input signal into an AC signal, and amplifies the AC sign using
high gain AC amplifier. Then it converts AC signal to DC signal. This technique
limits the drift component of the amplifier, because the drift is a DC component and
it is not amplified/passed by the AC amp1ifier. This makes the ADC extremely
insensitive to temperature, long term drift and input offset errors.

In ADC conversion process the input analog value is quantized and each quantized
analog value

will have a unique binary equivalent.
The quantization step in ADC0809/ADC0808 is given by,
The various functional blocks of ADC are 8-channel multiplexer, comparator, 256R
resistor ladder, switch tree, successive approximation register, output buffer, address latch
and decoder.

The 8-channel multiplexer can accept eight analog inputs in the range of 0 to 5V and
allow one by one for conversion depending on the 3-bit address input. The channel
selection logic is,

The successive approximation register (SAR) performs eight iterations to determine
the digital code for input value. The SAR is reset on the positive edge of START
pulse and start the conversion process on the falling edge of START pulse.
A conversion process will be interrupted on receipt of new START pulse.
The End-Of-Conversion (EOC) will go low between 0 and 8 clock pulses after the positive
edge of START pulse.
The ADC can be used in continuous conversion mode by tying the EOC output to START
input. In this mode an external START pulse should be applied whenever power is
switched ON.

The 256'R resistor network and the switch tree is shown in fig.

The 256R ladder network has been provided instead of conventional R/2R ladder
because of its inherent monotonic, which guarantees no missing digital codes.

Also the 256R resistor network does not cause load variations on the reference
voltage.

The comparator in ADC0809/ADC0808 is a chopper- stabilized comparator. It
converts the DC input signal into an AC signal, and amplifies the AC sign using
high gain AC amplifier. Then it converts AC signal to DC signal. This technique
limits the drift component of the amplifier, because the drift is a DC component and
it is not amplified/passed by the AC amp1ifier. This makes the ADC extremely
insensitive to temperature, long term drift and input offset errors.

In ADC conversion process the input analog value is quantized and each quantized
analog value

will have a unique binary equivalent.
The quantization step in ADC0809/ADC0808 is given by,