System components
Timing diagrams.
Memory.
Busses and interconnect.
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Overheads for Computers as
Components
Timing diagrams
 A timing diagram shows a trace through the operation of
a system.
Generally used for asynchronous machines with timing
constraints.
enq
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Overheads for Computers as
Components
ack
Timing diagram syntax
Constant value:
1
0
Stable:
Changing:
Unknown:
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Overheads for Computers as
Components
Timing constraints
Minimum time between two events:
enq
20 ns
ack
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Overheads for Computers as
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Origin of timing
constraints
Control signals are passed on the bus:
D
20 ns
c
a
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Overheads for Computers as
Components
Q
Memory device
organization
n
r
Memory array
c
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Overheads for Computers as
Components
Memory parameters
Size.
Address width.
Aspect ratio.
Data width.
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Types of memory
ROM:
Mask-programmable.
Flash programmable.
RAM:
DRAM.
SRAM.
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SRAM vs. DRAM
SRAM:
Faster.
Easier to integrate with logic.
Higher power consumption.
DRAM:
Denser.
Must be refreshed.
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Overheads for Computers as
Components
Typical generic SRAM
CE’
R/W’
SRAM
Adrs
Data
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Overheads for Computers as
Components
Generic SRAM timing
CE’
R/W’
Adrs
Data
From SRAM
read
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Overheads for Computers as
Components
From CPU
write
time
Generic DRAM device
CE’
R/W’
RAS’
CAS’
Adrs
DRAM
Data
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Overheads for Computers as
Components
Generic DRAM timing
CE’
R/W’
RAS’
CAS’
Adrs
row
adrs
col
adrs
Data
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Kaufman
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Overheads for Computers as
Components
time
Page mode access
CE’
R/W’
RAS’
CAS’
Adrs
Data
© 2000 Morgan
Kaufman
row
adrs
col
adrs
data
Overheads for Computers as
Components
col
adrs
data
col
adrs
data
time
RAM refresh
Value decays in approx. 1 ms.
Refresh value by reading it.
Can’t access memory during refresh.
CAS-before-RAS refresh.
Hidden refresh.
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Other types of memory
Extended data out (EDO): improved page
mode access.
Synchronous DRAM: clocked access for
pipelining.
Rambus: highly pipelined DRAM.
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Components
Flash issues
Flash is programmed at system voltages.
Erasure time is long.
Must be erased in blocks.
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Overheads for Computers as
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Generic bus structure
Address:
m
n
Data:
Control:
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c
Overheads for Computers as
Components
Electrical bus design
Bus signals are usually tri-stated.
Address and data lines may be multiplexed.
Every device on the bus must be able to drive
the maximum bus load:
Bus wires.
Other bus devices.
Bus may include clock signal.
Timing is relative to clock.
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Overheads for Computers as
Components
Four-cycle handshake
3
1
enq
data
4
2
ack
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Overheads for Computers as
Components
Busses as communicating
machines
enq = 1
ack = 0
0
0
ack
enq
1
1
enq = 0
ack
ack = 1
1
enq
0
M1
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Kaufman
0
M2
Overheads for Computers as
Components
1
When should you
handshake?
When response time cannot be
guaranteed in advance:
Data-dependent delay.
Component variations.
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Overheads for Computers as
Components
Fixed-delay memory
access
read = 1
adrs = A
R/W
data
R/W
R
reg = data
adrs
mem[adrs] =
data
data = mem[adrs]
memory
CPU
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Kaufman
W
Overheads for Computers as
Components
Variable-delay memory
access
read = 1
adrs = A
R/W
done = 0
data
R/W
R
done
n
y
reg = data
adrs
data = mem[adrs]
done = 1
done
memory
CPU
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Kaufman
W mem[adrs] =
data
done = 1
Overheads for Computers as
Components
Typical bus access
clock
R/W’
Address
enable
adrs
Data
Ready’
data
write time
read
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Overheads for Computers as
Components
Bus mastership
Bus master controls operations on the
bus.
CPU is default bus master.
Other devices may request bus
mastership.
Separate set of handshaking lines.
CPU can’t use bus when it is not master.
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Direct memory access
(DMA)
DMA provides parallelism on bus by
controlling transfers without CPU.
I/O
memory
CPU
DMA
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DMA operation
CPU sets up DMA transfer:
Start address.
Length.
Transfer block length.
Style of transfer.
DMA controller performs transfer, signals when
done:
Cycle-stealing.
Priority.
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Overheads for Computers as
Components
ARM busses
Open standard.
Many external
devices.
memory
CPU
Two varieties:
AMBA HighPerformance Bus
(AHB).
AMBA Peripherals
Bus (APB).
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Overheads for Computers as
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AHB
bridge
AMBA:
I/O
APB