ECE 171
Digital Circuits
Chapter 9
Hazards
Herbert G. Mayer, PSU
Status 2/25/2016
Copied with Permission from prof. Mark Faust @ PSU ECE
Syllabus
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Glitches and Hazards
Static Logic Hazards
Static Function Hazards
Dynamic Hazards
Decoders
Multiplexers
References
Glitches and Hazards
• So far we assumed: steady state of a circuit
• Steady state is equivalent to having “waited” a long
time for signals to settle
• Long time meaning: more than a cycle for clocked, or
longer than signal propagation time for un-clocked
• In practice, the actual time for a signal to propagate
to the output gate can be long, and the signal may
depend on which path that signal has taken
• Depending on such paths, outputs may experience
an unintended pulse, AKA glitch
• Glitch means: though the steady state produces the
correct signal, an opposite signal occurs momentarily
Glitches and Hazards
• Hazard means the condition for a glitch exists
• It doesn’t mean the hazard actually occurs each time
• It doesn’t even mean the hazard occurs at all during
this execution
• It means, the hazard can occur, based on input signal
combinations, on actual signal path taken
• The circuit designer must identify are acceptable or
not
• If hazards are not acceptable, the designed must
analyze and take design steps to avoid them; e.g. via
consensus terms
Glitches and Hazards
Glitch: Wrong signal in a circuit due to unequal delay paths; this is
the manifestation of a hazard
Logic Hazard: Is a glitch when one input changes. Can be
removed by adding logic: AKA consensus terms
Function Hazard: May cause glitch when two or more inputs
change at once. Cannot generally be removed by adding logic.
Static Hazard: Occurs when output of the circuit is supposed to be
constant. There are 2 kinds: unexpected 0 or unexpected 1
Dynamic Hazard: Occurs when output of the circuit changes
unexpectedly more than once for a single input change.
Function and Logic Hazards can be Static or Dynamic.
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Glitches and Hazards
• Definition: A static-1 hazard is an unexpected 0 output,
generated by a pair of input combinations such that: a.) the
two inputs differ by just 1 variable, b.) both combinations
produce a 1 output signal, yet c.) an unwanted 0 signal
occurs during the single input transition
• Definition: A static-0 hazard is an unexpected 1 output,
generated by a pair of input combinations such that: a.) the
two inputs differ by just 1 variable, b.) both combinations
produce a 0 output signal, yet c.) an unwanted 1 signal
occurs during the single input transition
• Definition: A dynamic hazard is the possibility of an
unexpected change of the output signal more than once as a
result of a single input signal change
Static Logic Hazards
Single input changed. Resulting output should have remained
constant: 1 in case(a). 0 in case(b). However, a glitch appeared
before the output settled back to its correct level
Two-level SOP circuits may see static-1 hazards
Two-level POS circuits may see static-0 hazards
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Static-1 Hazard with SoP
Static-1 Logic Hazard
F1  A  C  B  C
Students draw minimized circuit in class, SOP form:
And- and Or-gates OK, better even Nand-gates
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Static-1 Logic Hazard
Consider inputs
ABC
111 time t1
110 time t2
F1  A  C  B  C
11
01
11
NAND/NAND Implementation
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Observe Carefully:
• If first input at time t1 is: A B C = 1 1 1, the output F1
will be 1, due to nand-gate with inputs B C
• Then at time t2 the input changes to A B C = 1 1 0
• Output F1 again is 1, due to nand-gate with inputs A
C’, but the length (and thus the length of time) for the
input path with signal C’ is longer, due to the inverter;
may be critical!
• In some instances that may be a sufficient delay to
create a brief static 1 hazard, AKA 0 glitch
• 1 hazard alluding to: signal should be 1 but isn’t
• Static alluding to: signal should be 1 before, should be
1 after, but there is a different value; must be 0
Static-1 Logic Hazard
Consider inputs
ABC
111
110
F1  A  C  B  C
11
01
11
NAND/NAND Implementation
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Detect, Eliminate Static-1 Hazard
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Countermeasure
• To avoid this type of hazard:
• With input transition 111 -> 110, output signal F1
should stay 1: was 1 initially, should remain 1
• Yet the “second 1” may arrive just a bit late: longer path
• Add 3rd signal path (consensus term) that covers areas
of 1s with further option to generate 1 signal: AB
Detect, Eliminate Static-1 Hazard
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Static-0 Hazard with SoP
Static-0 Hazard
Implement a hazard-free circuit for the 0s of the previous function
using NOR gates
SoP Form for 0s:
F1’ = . . . Students!!
Students write F1( A, B, C ) in SoP form, for 0s
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Static-0 Hazard
Implement a hazard-free circuit for the 0s of the previous function
using NOR gates
SOP Form for 0s:
F1= A×C + B×C
• Hazard occurs at boundary of 2 terms, both of which deliver
the same signal of interest, 0 here, at different times
• Consensus term needed to deliver same signal, 0 here, if the
other 2 terms may not “agree” about timing
• To avoid a logic 1 glitch
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Static-0 Hazard
•
•
•
•
•
Where is a critical boundary?
Look for: products grouped together!
Look for: logically adjacent terms in K-map
Add new term covering both, adjacent terms
Is redundant for signal-generation, but adds
needed value that otherwise might get lost, due
to glitch
Static-0 Hazard
Students, which term is to be added?
One that covers 0s, when 2 adjacent terms
should be 0, but happen to become temporarily 1
Without adding new 0 terms!
I.e. covering existing neighboring zeros!
And that is . . . Which term?
Static-0 Hazard
Implement a hazard-free circuit for the 0s of the previous function
using NOR gates
SOP Form for 0s
F1  A  C  B  C
Needed Cover Term Included
F1= A×C + B×C + A× B
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Static Function Hazards
Result of multiple input signals changing
Cannot generally be removed by adding logic
Unless we design new logic!
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Hazard Example
Hazard Example
•
•
•
•
Given the K-Map for function Haz() below:
Write function Haz() in SoP form
Identify where hazards exist
Devise a hazard-free function Haz’() equivalent to Haz()
c
c
0
0
0
0
0
0
1
1
b
a
1
1
1
1
b
a
1
1
0
0
d
d
Haz( a, b, c, d ) = ?
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Hazard Example
• Assuming Haz() = a c’ + a’ c
• The hazard arises between cells: a b c’ d and a b c d
• Add new term a b d, so: Haz’() = a c’ + b c + a b
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Dynamic Hazard
Dynamic Hazards
• Generally occur in multi-level circuits with multiple paths,
each having different delays from input to output
• Do not occur in 2-level SOP (or POS) implementations
• Requires these further levels, creating more choices, each with
differing timings
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Implementations for Complex
Functions and Their Delays
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Decoders
Decoders
n-to-2n decoder
Converts binary code on n=2 input lines to one of 2n=4 output lines
When decoder has EN enabled, is referred to as
demultiplexer (dmux). EN is often active low.
Students design circuit in class now, ignore EN
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Decoders
Converts binary code on n input lines to one of 2n output lines
But EN ignored here!
I1
I0
Y0
Y1
Y2
Y3
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Decoders
Converts binary code on n input lines to 1 of 2n output lines
EN’
I1
I0
Y0
Now with EN’ signal.
Shown with EN negated:
Y1
Y2
Y3
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Decoders
Sometimes outputs are active low too!
B1B0 F0F1F2F3
0 0 0111
0 1 1011
1 0 1101
1 1 1110
F0
F1
F2
F3
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Decoders
When using decoders with active low outputs use “bubble
matching” to use correct gate
Example: Implement XNOR with DMUX
F  X  Y  F ( X , Y )   (0,3)
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Multiplexers
Multiplexers (Data Selectors) Mux
Directs one of 2n inputs to a single output
S0 F
0 D0
1 D1
S0D1D0 F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
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Multiplexers
Sometimes include Enable input; can be high or low
Effective as universal function generator.
Students: in class create Truth table for F( EN’, S0, D0, D1 )
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Multiplexers
Here truth table shown:
EN S0
0 0
0 1
1 X
F
D0
D1
0
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Type 0 Universal Function
Implementation with a Mux
Uses the function inputs (X,Y,Z) to “select” the value of the function by
selecting the minterm corresponding to the inputs. If the minterm mi is
in the function the corresponding Di input is tied to 1 (0 otherwise)
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Type 1 Universal Function
Implementation with a Mux
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A word about “optimization”
• What are we optimizing?
–
–
–
–
–
–
–
Variables (inputs – connectors)
Terms (gates, interconnect)
Unique fan-in (IC packages – same number of gates)
Number of logic levels (speed)
NAND/NOR Implementations (speed, IC packages,…)
Complexity (Design time – time to market)
Design Time & Flexibility/Cost (FPGA vs. ASIC)
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