FPGA for
Dummies
Modern FPGA architecture
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA for Dummies
• Historical introduction, where we come from;
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional elements;
• FPGA Programming:
Design flow;
Software;
• FPGA DSP:
Digital filters examples;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA for Dummies
• Historical introduction, where we come from;
• FPGA Architecture:
 basic blocks (Logic, FFs, wires and IOs);
 additional elements;
• FPGA Programming:
Design flow;
Software;
• FPGA DSP:
Digital filters examples;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
Field Programmable Gate Arrays
(FPGAs)
FPGAs initially were Similar to CPLDs, so a function to be
implemented in FPGA is partitioned into modules (each
implemented in a logic block) and then the logic blocks are
connected with the programmable interconnection: ARRAY of
logic GATES is the G and A in FPGA.
By way of a configuration file or bit stream, an FPGA can be
configured to implement the user’s desired function: this allows
customization at the user’s electronics bench, or even in the
final end product.
This is why FPGAs are FIELD PROGRAMMABLE.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
Basic FPGA Architecture
The basic structure of an FPGA is
composed of the following elements:
 Look-up table (LUT): This element
performs logic operations
 Flip-Flop (FF): This register
element stores the result of the
LUT
 Wires: These elements connect
elements to one another, both
Logic and clock
 Input/Output (I/O) pads: These
physically available ports get
signals in and out of the FPGA.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
Contemporary FPGA architectures incorporate the
basic elements along with additional computational
and data storage blocks that increase the
computational density and efficiency of the device.
The combination of these elements provides the
FPGA with the flexibility to implement any software
algorithm running on a processor.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: memory
Using LUTs as registers does not provide enough
space or versatility, so the FPGA fabric includes
embedded memory elements that can be used
as random-access memory (RAM), read-only
memory (ROM), or shift registers. These
elements are block RAMs (BRAMs), LUTs, and
shift registers.
Using LUTs as SRAM, this is called
DISTRIBUTE RAM
Included dedicated RAM components in the FPGA fabric are called
BLOCKs RAM
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: memory
The 7 series families have the same Block RAM/FIFO
(36Kb or 18kb+18kb): this components has multiple
configuration options;
 Integrated Error Correction
 FIFO Logic
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: memory
Single-Port
Block RAM
True Dual-Port
Block RAM
Simple Dual-Port
Block RAM
Block RAM Cascading
Example: Cascade 8 block RAMs to build
256-Kb memory
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: memory
Full featured FIFO:
 Synchronous or asynchronous
read and write clocks;
 Full, empty, programmable
almost-full/empty flags;
 Optional first-word-fall-through
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: memory
Altera Cyclone II embedded
memory structure consist of
columns of M4k memory
blocks;
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FPGA Components: memory
Altera Stratix II embedded memory structure consist of TriMatrix of M512,
M4k and big M-RAM memory blocks;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
All synchronous designs need at least one external clock reference,
many designs require several clock sources!!!
Modern applications have complex clocking requirements:
 Extremely high-performance clock signals;
 Support for multiple frequency domains across a wide frequency
range;
 De-skewing of clocks relative to one another;
 Low jitter and precise duty cycle to maintain the widest possible
data valid window;
 Lowest possible system power
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
Clock regions:
 Each clock region is 50 CLBs
high and spans half the device:
 12 global clock networks
(Driven by BUFH);
 4 regional clock networks
(Driven by BUFR);
 4 I/O clock networks
(Driven by BUFIO).
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
Vertical Spines:
 Global clock networks allow
clocks to be distributed to
potentially every clocked element
on the die;
 Global clocks are driven by
BUFGCTRL located in the middle
of the die;
 Each BUFGCTRL drives a
vertical spine in the center of the
die that runs from the bottom to
the top of the die;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
Horizontal Spines:
 Each clock region has 12 horizontal spines for carrying
global clocks:
 Clock regions on left and right have 12
independent horizontal spines;
 These horizontal spines can drive all clocked resources
within the region;
 Each horizontal spine is driven by a BUFH;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
Regional Clock Networks:
 These regional networks can drive all
clocked resources within the region;
 Each horizontal spine is driven by a BUFR;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
Clocking CLB Resources:
 In every region there are 12 horizontal spines of the global clock
network and 4 regional clocks;
 All 16 clocks can clock resources within the region;
 Only 12 of the 16 can enter the double column of CLBs in the top
and bottom half of the clock region
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: clocking
There are up to 24 Clock Management Tiles (CMT) per device, each one
contains:
 One Mixed-Mode Clock Manager (MMCM), that is used to generate
multiple clocks with defined phase and frequency relationships to a
given input clock.
 one PLL, primarily intended for use with the I/O phaser for high speed
memory controllers or with high requirement analog clocks.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: High Speed
Tranceivers
To communicate between FPGAs or
to other devices, it’s more convenient
to use high speed differential
connection instead of parallel one, to
reduce noise spikes.
Many standard protocol use this
approach for the physical layer:
Fibre Channel, InfiniBand, PCI
Express, RapidIO, SkyRail ,
Gigabit Ethernet, etc…
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: High Speed
Tranceivers
 TX: From the FPGA
fabric a parallel bus is
encoded to increase the
robustness against the
noise and to reduce the
DC component and then
serialized;
 RX: the received
differential signal is used
to reconstruct the clock,
and then decoded and
re-parallelized.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: High Speed
Tranceivers
Xilinx Multi-Gigabit Transceiver have different name depending on the
maximum speed that they support:
 GTP (6,6 Gbps);
 GTX (12,5 Gbps);
 GTH (16,3 Gbps);
 GTY (32,75 Gbps).
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: High Speed
Tranceivers
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: High Speed
Tranceivers
The Arria 10 FPGA and SoC transceivers have a versatile feature set to
handle a wide range of links and provide error-free link operation
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components:
Off-chip memory controllers
FPGA devices provide memory interface support, including serial and
parallel interfaces.
 Serial memory: Hybrid Memory Cube (HMC) is the latest technology;
 Parallel Memory: latest devices offer parallel memory support up to
high rate for DDR4 and supports a wide range of other protocols like
o DDR3 / DDR3L, LPDDR3;
o DDR2;
o Mobile DRAMs;
o QDRII+ SRAM;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: multiplier
XILINX Spartan 3 (2004) include on
the side of each BRAM a multiplier
block (18x18)
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: multiplier
Altera Cyclone II has one to three columns of
embedded multipliers; each embedded
multiplier can be configured to support :
 One 18 x 18 multiplier
 Two 9 x 9 multipliers
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: XtremeDSP
Multiplier
Adder
Accumulator
A[n:0]
x
B[n:0]
+
Y[(2n - 1):0]
Starting with Virtex 4 family, Xilinx
introduced DSP48 block for highspeed DSP on FPGAs
Essentially a multiply-accumulate
core with many other features
MAC
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: XtremeDSP
Adder Out = (Z ± (X + Y + CIN))
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FPGA Components: DSP unit
Also Altera include in the Stratix III family a DSP Unit
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Architecture
These additional elements, which are discussed in the following
sections, are:
 Embedded memories for distributed data storage;
 Phase-locked loops (PLLs) for driving the FPGA fabric at different
clock rates;
 High-speed serial transceivers;
 Off-chip memory controllers;
 Multiply-accumulate blocks;
 Embedded processors.
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Xilinx Virtex-II Pro include a
PowerPC™ 405 Core
1. Processor Block
2. RocketIO Multi-Gigabit
Transceivers
3. CLB and Configurable Logic
4. SelectIO-Ultra
5. Digital Clock Managers
6. Multipliers and Block
SelectRAM
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Xilinx Zynq is an Innovative
ARM® + FPGA architecture for
differentiation, analytics &
control.
 Zynq-7000 SoC uses a Dualcore ARM® Cortex™-A9 MPCore™
with CoreSight™ up to 1GHz;
 Zynq UltraScale+ MPSoC uses
a Quad-core ARM® Cortex™A53 MPCore up to 1.5GHz with
a Real-Time Processing Unit
Dual-core ARM®
Cortex™-R5 MPCore up to
600MHz
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
FPGA Components: Embedded
Microprocessor Cores
Also Altera has ARM® +
FPGA architectures:
 Arria 10 SoCs, includes a
dual-core ARM® Cortex™A9 MPCore™ hard
processor system (HPS);
 Stratix 10 FPGA and SoC
system includes ad-core 64
bit ARM® Cortex®-A53 hard
processor system up to 1.5
GHz;
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
Questions
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna
ESS | FPGA for Dummies | 2015-12-15| Maurizio Donna