Noise and Reliability in Advanced Bipolar
Technologies
Md Mazhar Ul Hoque
Advisor: Prof. Zeynep Celik-Butler
Department of Electrical Engineering
University of Texas at Arlington
UTA Noise and Reliability Laboratory
1
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
2
Current BJT low-frequency noise models




Gummel-Poon:
2
I BN

KF  I BAF
f
EF
 f
VBIC – Flicker noise due to IBE, IBEP
MEXTRAM:

 I B2
MULT
2

iN B 
KFN 

f
MULT


MODELLA:
1 AF
KF

MULT
I RE  I LE
2
iN B 
f
2

 I B1
  KF 

 MULT


UTA Noise and Reliability Laboratory




2
  f


AF
 f
3
Importance and motivation
Limitations in existing noise models:


Only one single noise source in base current: SIB=KF.IBAF.

Noise in base current dominant only for higher base series
resistance.

Does not include any geometry, temperature or process
parameter.
Noise in collector current and internal resistances are neglected.

Noise in collector current contributes at lower base series
resistance.

Noise from internal resistance contributes at higher bias current.
Research goal:



To model all possible noise sources in advanced bipolar transistors:

Noise in base current, collector current and internal resistances.
Developing physics based scalable equations for the noise sources:

Incorporating geometry, temperature and process dependant
parameters.
Writing computer source code for device and circuit analysis CAD
tools to incorporate all possible noise sources in BJT.
UTA Noise and Reliability Laboratory
4
Advanced bipolar technologies under
investigation

Polysilicon emitter bipolar transistors:

2nd generation BiCMOS technology, Texas
Instruments Inc.



NPN and PNP transistors.
Variable size, variable IFO thickness.
SiGe heterojunction bipolar transistors:

1st generation BiCMOS technology, National
Semiconductor Corporation.



NPN transistors.
Variable size, variable design rules.
Variable doping in base and collector.
UTA Noise and Reliability Laboratory
5
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
6
Collector-base measurement setup
RL
12V
RS
4.8V
100K
100K
(a)
rb
SV R
SVB
S
RS
rc
  ib
ib
SVr
b
SIB
r
ro
c
S IC
SVr
SVB1
RB1
SVr
e
SVR
L
RL
SVC
SVB 2
re
RB 2
(b)
UTA Noise and Reliability Laboratory
7
Collector-base measurement
SVC  x  SVr  y  S I B  z  S I C
SVB  u  SVr  v  S I B  w  S I C
2
SVBC
2
SVB  SVC
SVr  SVr  SVr
e
b
for unity coherence:
If SVr
has the dominant contribution,
If S I B
has the dominant contribution,
If S I C has the dominant contribution,
SVC
SVB
SVC
SVB
SVC
SVB

x
u

y
v

z
w
UTA Noise and Reliability Laboratory
8
Dominant noise source
10
6
10
5
10
4
0.7x100 μm2 PNP, thickest IFO, RS=1MΩ
Vr
0.5
10
2
10
1
10
0
10
-8
10
-7
10
0
-6
VB
3
6
10
5
10
4
10
3
10
2
10
1
10
0
1
measured at 1 Hz
S contribution dominant
IB
VC
10
VC
S /S
VB
IB
S contribution dominant
IC
S contribution dominant
S /S
measured at 1 Hz
S contribution dominant
Coherence (at 1 Hz)
1
10
S contribution dominant
IC
S contribution dominant
Vr
10
0.5
-1
10
-7
-6
10
-5
0
I (A)
I (A)
B
B

10
Coherence (at 1 Hz)
0.7x100 μm2 NPN, thickest IFO, RS=1MΩ
Calculated SVC/SVB considering SIB contribution dominant closely
matches experimental SVC/SVB; SIB contribution dominant.
UTA Noise and Reliability Laboratory
9
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
10
Area dependence of SIB in NPN transistors
10
-20
I = 0.1mA
I = 0.3mA
I = 0.5mA
I = 0.2mA
I = 0.4mA
I = 0.6mA
B
B
B
S (A /Hz)
10
B
B
B
-21
Noise source
2
homogeneously distributed
IB
underneath the emitter.
10
-22
~ 1/A
10
-23
1
10
2
Emitter Area (m )
[ Darby Lan ]
UTA Noise and Reliability Laboratory
11
Internal emitter resistance and ideality
factor of base current
0.7x100 μm2 NPN, thickest IFO, RS=1MΩ
1.6
m  re  gmi  nb
1.5
m
mm
1.4
~ m = 27.8 gmi + 1.07
1.3
ri
SVC
kT
qI B
gmi 
1.1
1
1.0E-03
SVB
ri 
re=27.8 ohm
nb =1.07
1.2
  RL
5.0E-03
9.0E-03
1.3E-02

ri
1.7E-02
-1
gmi (ohm ) -1
gmi
(ohm )
UTA Noise and Reliability Laboratory
12
Physical origin of SIB

Base current dependence

SI B
 I Bdiff
diffusion fluctuation in emitter.
SIB
2
 IB
tunneling fluctuation in IFO.
diff

tun
tun
recombination fluctuation in emitterbase space charge region.

SI B
rec


2
 IB
rec
recombination fluctuation at spacer
oxide interface.
Emitter perimeter dependence

Noise source distributed homogeneously around the emitter.

Recombination fluctuation at the spacer oxide interface.
Emitter area dependence

Noise source distributed homogeneously underneath the emitter.

Diffusion fluctuation in emitter or tunneling fluctuation in IFO.
UTA Noise and Reliability Laboratory
13
Physical origin of SIB (cont.)
SIB  SIB
 SIB
 SIB
diff
tun
rec

Unity ideality factor of
IB
negligible
I Brec .
negligible
SIB
rec
.
SI B  SI B
 SI B
diff
tun
UTA Noise and Reliability Laboratory
14
Diffusion and tunneling
fluctuation component of SIB
0.7x100 μm2 NPN, medium IFO, RS=1MΩ
SI B  SI B  SI B
D
T
SIB/IB (A/Hz)
8.10E-16
2
 KFD  I B  KFT  I B
6.10E-16
4.10E-16
~ SIB/IB = 1.13x10-9 IB + 7.85x10-17
IB
-9
SIBT = 1.13x10
2.10E-16
SIB
 KFD  KFT  I B
-17
SIBD = 7.85x10
1.00E-17
1.E-08
2.E-07
3.E-07
5.E-07
6.E-07
8.E-07
IB(A)
UTA Noise and Reliability Laboratory
15
Area dependence of tunneling
fluctuation of SIB in PNP transistors
-7
10
Thickest oxide
Tunneling-fluctuation source
homogeneously distributed
underneath the emitter.
-8
10
T
~1/A
(0.847)
KF
E
Smaller device-dimension
severely affected by lateral
-9
10
diffusion and mask undercut;
effective emitter area
considered.
Thickest IFO
-10
10
-1
10
0
10
1
2
10
10
2
Emitter area: A (m )
E
UTA Noise and Reliability Laboratory
16
Diffusion fluctuation in SIB
 p(0)   pq  p( x2 ) 
ln

ln
Dm f  p( x1 )  D p f  p( x3 ) 
mq
D
IB

 Wm W p
1
1 




 Dm D p sox sm 


smW p
p x 2 
1
p x 3 
Dp
p0
Wm  1
1 W p 
1


p x1 
Dm  sox sm D p 
1
αm : Hooge parameter in mono-Si
αp : Hooge parameter in poly-Si
2
Assumption: αm = αp =α
carrier concentration p(x)
SIB
monosilicon
base
oxide
metal
contact
Polysilicon
p(x)
p(x)
sox
αp, Dp
αm, Dm
x1
0
sm
Wm
UTA Noise and Reliability Laboratory
x3
x2
L
Wp
17
Tunneling fluctuation in SIB

 1 Wm W p  
T

 1  sox 


2


IB

 sm Dm D p  
SIB
tmn
tunneling probability
of minority carriers
2
St mn
St mn
2
t mn
2
tmn

m*qkTL3 tan
3Vo 2 ox Af
 ox
oxide permittivity
Vo
barrier height for the
minority carriers
St mn
fluctuation in tmn
m*
effective mass of
minority carriers

modified Planck’s
constant
q
electronic charge
A
area of IFO
k
Boltzmann constant
L
IFO thickness
tan
loss tangent of the
oxide
UTA Noise and Reliability Laboratory
18
Scaling effect on SIB
AF for SIB in PNP transistors
Relative
AF
IFO thickness
0.7x100
( μm2 )
0.7x0.7
( μm2 )
thickest
1.12
1.89
medium
1.23
2.09
thinnest
1.01
S I B  KF  I BAF
SIB  SIB
 SIB
diff
tun
2
 KFD  I B  KFT  I B

Diffusion fluctuation dominant in large (0.7x100μm2) devices.

Tunneling fluctuation dominant in small (0.7x0.7μm2) devices.
UTA Noise and Reliability Laboratory
19
Scaling effect on SIB in PNP
transistors with thickest IFO
-18
10
A = 0.7x100m
AF=1.12
-19
10
2
A = 0.7x10m
AF=1.79
2
-19
10
-20
-20
10
10
S
-21
S
10
S
-22
IB
-21
10
IBT
-22
10
10
-23
10
-24
-24
10
A = 0.7x2.8m
AF=1.66
-19
10
2
A = 0.7x0.7m
AF=1.89
2
-19
10
-20
-20
10
Tunneling
fluctuation
component of SIB
I
10
2
Diffusion fluctuation dominant
I
2
-23
S (A /Hz)
10
S (A /Hz)
Total SIB
IBD
10
Tunneling fluctuation dominant
-21
-21
10
-22
10
-23
10
10
Diffusion
fluctuation
component of SIB
-22
10
-23
10
-24
-24
10
10
-8
10
-7
10
-6
10
-8
-5
10
-7
10
-6
10
-5
10
I (A)
B
UTA Noise and Reliability Laboratory
20
Emitter plug effect in smaller device
small device
Large device
dl < ds
Poly-Si emitter
oxide
dl
ds
mono-Si emitter
base


Thicker polysilicon in smaller transistors.
Lower dopant concentration; shallower junction.

higher chance for minority carriers from base to reach and tunnel
through the oxide interface; tunneling fluctuation dominant.

FLUORINE EFFECT: fluorine enhances oxide break-up.
 lower fluorine (from BF2) concentration causes less oxide
breakup in smaller PNP devices; increased tunneling:
(no fluorine in the transistors studied here)
UTA Noise and Reliability Laboratory
21
Perimeter depletion effect
d1 < d2
Poly-Si emitter
oxide
d1
d2
mono-Si emitter
base




Polysilicon surface almost perpendicular to wafer surface
at emitter window sidewall.
Reduced doping concentration in the perimeter region.
Shallower junction close to emitter window perimeter.
An overlap of the emitter-base space charge region with
poly-mono silicon interface might occur close to
perimeter.
UTA Noise and Reliability Laboratory
22
Perimeter depletion effect in smaller
transistors
Perimeter/area vs. emitter area
Perimeter/area
5.00
4.00
3.00
2.00
1.00
0
20
40
60
80
100
120
emitter area (μm2)

For smaller transistors

perimeter/area ratio increases sharply.

non ideal peripheral component of base current increases.

fluctuation in non-ideal base current might become significant.
UTA Noise and Reliability Laboratory
23
Effect of IFO on DC characteristics of
0.7x100μm2 NPN transistors
2
10
600
I (thickest IFO)
C
I (thickest IFO)
B
I (medium IFO)
0
10
-2
thickest IFO
medium IFO
thinnest IFO
I
C
C
10
500
I (medium IFO)
10
400
C
I (thinnest IFO)
B
-6
10
300
-8
10
200
-10
I
10
Current gain
Current (A)
B
I (thinnest IFO)
-4
B
100
-12
10
-14
10
0.3
0.4
0.5
0.6
0.6
0.7
0.8
0.9
1 0.3
V

BE
0.4
0.5
0.6
0.6
0.7
0.8
0.9
1
0
(V)
IFO increases the current gain significantly.
UTA Noise and Reliability Laboratory
24
Effect of IFO on DC characteristics
of 0.7x100μm2 PNP transistors
2
10
0
thickest IFO
medium IFO
thinnest IFO
I (thickest IFO)
C
I (thickest IFO)
B
Current (A)
10
I (medium IFO)
C
-2
I
I (medium IFO)
B
10
160
C
120
I (thinnest IFO)
C
-4
I (thinnest IFO)
B
10
-6
10
-8
10
-10
10
-12
80
I
0.3
0.4
0.5
0.6
0.6
40
B
0.7
0.8
0.9
1 0.3
V

Current gain
10
BE
0.4
0.5
0.6
0.6
0.7
0.8
0.9
1
0
(V)
No significant improvement in current gain with increasing
IFO thickness.
UTA Noise and Reliability Laboratory
25
Effect of interfacial oxide on SIB
in NPN and PNP transistors
0.7x100 μm2 NPN
10
-19
10
0.7x100 μm2 PNP
-19
thickest IFO
medium IFO
10
-20
10
-21
10
-22
10
-20
10
-21
10
-22
10
-23
10
-23
-24
10
-24
10
thinnest IFO
2
S (A /Hz)
thinnest IFO
10
IB
IB
2
S (A /Hz)
thickest IFO
medium IFO
-8
10
-7
10
-6
10
-5
10
-8
10
I (A)
B

-7
10
-6
10
-5
I (A)
B
IFO increases SIB both in NPN and PNP transistors.
UTA Noise and Reliability Laboratory
26
Difference in the effect of IFO
in NPN and PNP transistors
0.7x100μm2 transistors
Device type
AF
PNP
~1
NPN
~ 1.5


S I B  KF  I BAF
S I B  S IBdiff  S IBtun
 KFD  IB  KFT  IB 2
In PNP, diffusion fluctuation in mono and poly-silicon
emitter dominates; less effect of IFO.
In NPN, both diffusion fluctuation in mono and polysilicon emitter, and tunneling fluctuation through IFO
contribute.
UTA Noise and Reliability Laboratory
27
Physics behind difference
in NPN and PNP transistors




Hole barrier height larger than electron barrier height at
interfacial oxide:

minority carriers (holes) severely suppressed in NPN;
significant current gain improvement.

minority carriers (electrons) not suppressed significantly in
PNP; little current gain improvement.
Effect of fluorine:

fluorine accelerates oxide break-up.

fluorine from emitter dopant BF2 in PNP creates more oxide
breakup; reduced tunneling and increased diffusion through
broken oxide.
Increased oxide breakup and faster diffusion of boron makes the
emitter deeper in PNP:

increased recombination-base current, reduced current gain
improvement.

higher diffusion fluctuation in larger monosilicon emitter
region.
Different oxidation rate of the base material could create different
IFO thickness for NPN and PNP transistors on the same wafer.
UTA Noise and Reliability Laboratory
28
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
29
Effect of interfacial oxide on SIC
0.7x100 μm2 NPN
10
-15
10
-16
0.7x100 μm2 PNP
10
-15
10
-16
10
-17
10
-18
thickest IFO: AFC=1.54
medium IFO: AFC=1.74
-17
10
-18
10
-19
10
-19
10
-20
10
-20
10
-21
10
-21
IC
2
S (A /Hz)
10
IC
2
S (A /Hz)
thinnest IFO: AFC=2.01
10
-6
10
-5
10
-4
10
-3
thickest IFO: AFC=1.72
medium IFO: AFC=1.71
10
-5
I (A)
C

10
-4
10
-3
I (A)
C
IFO increases SIC both in NPN and PNP transistors.
UTA Noise and Reliability Laboratory
30
SIC modeling
Some researchers assign the same
S IC  S IC  S IC
N
D
 KFN  IC 2  KFD  IC
origin of SIB to SIC.
S IC 
SVC
RL2
is merely an amplified SIB.
Hooge type fluctuation at the
collector side of basecollector junction.
1.E-05
-1
carrier transport determined
by electric field in base
collector junction.
h(ohm )
output conductance22
0.7x100μm2 PNP, thickest IFO
S I C  IC( 2 K 1)
h22  ICK
K 1
1.E-06
~ IC
(0.98)
K=0.98
1.E-07
1.E-05
1.E-04
1.E-03
IC (A)
Number fluctuation in SIC requires further investigation.
UTA Noise and Reliability Laboratory
31
Diffusion fluctuation in SIC
S IC
D
carrier concentration n(x)
IC

n(0)
  D / WB
 s
n(WB )
D / WB
qD
 n(0) 

ln
2
WB f  n(WB ) 
collector
s
monosilicon
base
saturated drift velocity
oxide
Polysilicon
metal
contact
n(x)
α, D
WB
0
UTA Noise and Reliability Laboratory
32
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
33
Effect of bias on coherence in NPN
and PNP transistors
0.7x100 μm2 NPN, thickest IFO, RS=1MΩ
0.7x100 μm2 PNP, thickest IFO, RS=1MΩ
1
1
0.8
0.8
'a' to 'e'
(increasing bias current)
0.6
0.4
Coherence
Coherence
1.2
0.6
a: I = 301 nA
B
0.4
a: I = 72 nA
B
B
c: I =1.09 
b: I =264 nA
B
B
d: I =1.48 
c: I =384 nA
0.2
b: I =493 nA
0.2
B
d: I =546 nA
B
e: I =1.99 
B
B
e: I =760 nA
B
0
0
10
10
1
10
2
10
3
10
4
10
5
0
0
10
10
1
Frequency (Hz)

10
2
10
3
10
4
10
5
Frequency (Hz)
Coherence decreases with increasing bias in NPN transistor.
UTA Noise and Reliability Laboratory
34
Effect of varying base bias resistance
(RS) on SV
0.7x100 μm2 NPN, thickest IFO, IB=384nA
10
(V /Hz)
-11
2
10
-10
-12
10
-13
10
-14
10
-15
decreasing R
S
RS=1M
RS=100K
RS=50K
RS=10K
Background noise
VB
10
-12
10
-13
-14
10
-16
10
10
-15
10
-17
S
10
S
VC
2
(V /Hz)
10
RS=1M
RS=100K
RS=50K
RS=10K
RS=1K
RS=120
-9
decreasing R
10
0
10
1
S
10
2
10
3
10
4
10
5
10
0
10
1
Frequency (Hz)


10
2
10
3
10
4
10
5
Frequency (Hz)
SVC does not decrease any more for RS smaller than 1 kΩ.
SVB becomes comparable to system background noise for RS
smaller than 10 kΩ.
UTA Noise and Reliability Laboratory
35
Collector-emitter measurement setup
SVE
SVC
4.8V
12V
RL
1K
RS
RE
100K
UTA Noise and Reliability Laboratory
36
Dominant noise source in
collector-emitter measurement
0.7x100 μm2 NPN, thickest IFO, RS=100Ω
10
5
1
VC
S /S
10
3
0.5
measured
S contribution dominant
IC
10
coherence at 1 Hz
4
VE
10
Unity coherence.
One single dominant
noise source:
2
SIC or SVr?
S contribution dominant
IB
S contribution dominant
Vr
10
1
10
0
-7
10
-6
10
-5
I (A)
B
UTA Noise and Reliability Laboratory
37
SIC in collector-emitter measurement
0.7x100 μm2 NPN, RS=100Ω
thickest IFO : AFC=3.21
10
-14
S IC  KFC  ICAFC
medium IFO : AFC=3.58
10
-15
10
-16
10
-17
IC
2
S (A /Hz)
AFC  3.05 ~ 3.58
no physical
explanation for
such high current
dependence:
SPURIOUS?
10
-18
10
-4
10
-3
10
-2
I (A)
C
UTA Noise and Reliability Laboratory
38
Effect of interfacial oxide on SVr
0.7x100 μm2 NPN, RS=100Ω
10
-11
10
-12
medium IFO
SVr  SVr  SVr
e
b
Vr
2
S (V /Hz)
thickest IFO
~I
10
E
-13
10
-14
10
-15
10
2
SVr  SVr
e
2
 IE
 Sre
-4
10
-3
10
-2
I (A)
E
UTA Noise and Reliability Laboratory
39
Effect of internal resistance in
collector-emitter measurement
0.7x100 μm2 NPN, thickest IFO
Collector-base measurement, RS=1MΩ
Collector-emitter measurement, RS=100Ω
1.E-03
1.E-03
exponential fitted line
( η=1.12 )
1.E-04
1.E-05
1.E-05
Base current (A)
Base current (A)
exponential fitted line
( η=1.1 )
1.E-04
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-07
1.E-08
noise
m easurem ent
region
1.E-09
1.E-10
noise
m easurem ent
region
1.E-11
1.E-06
1.E-11
1.E-12
1.E-12
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.5
0.6
VBE (V)
UTA Noise and Reliability Laboratory
0.7
0.8
0.9
1
VBE (V)
40
Tunneling fluctuation
through interfacial oxide
fluctuation in
minority carrier
tunneling
SIB
T
base
monosilicon
oxide
Polysilicon
metal
contact
fluctuation in
majority carrier
tunneling
Sre
re2

St mj
2
t mj

Sre
tunneling probability of the
majority carriers through IFO
m*qkTL3 tan
tmj
3Vo 2 ox Af
S t mj fluctuation in t
mj
UTA Noise and Reliability Laboratory
41
Interfacial oxide thickness
Relative
Emitter area
IFO thickness
(μm2)
interfacial oxide thickness (Å) from
minority carrier
majority carrier
fluctuation (SIBT)
fluctuation (SVre)
PNP
thickest
medium
thinnest
Vh
tan
0.7x100
14.50
0.7x10
16.90
0.7x2.8
14.50
0.7x0.7
11.00
0.7x100
4.13
0.7x0.7
8.78
NPN
NPN
4.08
11.30
0.7x100
2.70
0.7x0.7
2.81
2.26
Inconsistency:
uncertainty in loss
tangent, mass and
potential barrier of
the carriers at oxide
interface.
Vh  0.363V
Ve  0.097V
m*h  0.81mo
me*  1.08mo
tan
obtained from
Kleinpenning et. al,
IEEE Trans. on Elec.
Dev., vol. 42, 1995.
as high as 1.8V and Ve as high 1 V found in literature.
unique for each sample.
UTA Noise and Reliability Laboratory
42
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
43
Experimental and Simulated data
Simulation results vs. Measured
Simulated Noise vs Lab
1000.0
Noise (V/sqrt(Hz) AU)
100.0
10.0
1.0
0.1
1.E+01
Simulated with
modified model
Experimental
data
Noise data measured at TI
Simulated with
existing
model 1.E+03
1.E+02
1.E+04
1.E+05
1.E+06
1.E+07
Freq (Hz)
Production Models
THS4271 Lab
Spot Models
UTA Noise and Reliability Laboratory
44
Computer source code

Existing BERKELEY SPICE source code has been
modified.
 Source code written at Texas Instruments Inc. by
Douglas Weiser.
S I C and SVr have been added to the existing noise

model in addition to S I B .
 An area scaling factor has been added to the
equations to make the noise models scalable.
The modified BERKELEY SPICE source code is available
to the SRC (Semiconductor Research Corporation)
member companies (TI, Intel, IBM, Motorola, National
Semiconductor Corporation, AMD, etc.)
UTA Noise and Reliability Laboratory
45
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
46
Device structure under investigation
dielectric isolation
p+ SiGe
epi
p+ SiGe poly
p SiGe epi
shallow trench
DTI
(deep
trench
isolation)
Selectively
implanted
collector
z
SiGe epi-SiGe poly interface
n+ poly Si emitter
y
p+ SiGe
epi
n+ Si emitter
x
x = emitter-poly overlap
p+ SiGe poly
shallow trench
DTI
(deep
Trench
trench
isolation)
y = composite enclosure of poly
z = DTI enclosure of composite
Transistors described as x-y-z; e.g. SIC:25-10-25.
UTA Noise and Reliability Laboratory
47
Dominant noise source
5
6
10
10
SIC:20-20-40
SIC:20-20-40
1
4
Resistance (
0.8
VC
S /S
VB
3
10
2
experimental
S contribution dominant
IB
S contribution dominant
IC
S contribution dominant
10
1
10
10
base series resistance
input resistance
coherence at 10 Hz
0.4
4
10
0.2
3
-6
10
-5
10
-4
10
10
0
-6
-5
10
10
I (A)
-4
10
I (A)
B

0.6
Vr
0
10
5
Coherence at 10 Hz
10
B
Calculated SVC/SVB with SIB contribution dominant closely
matches experimental SVC/SVB ; SIB contribution dominant.

IB increases
rπ decreases
coherence increases.
UTA Noise and Reliability Laboratory
48
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
49
Selectively implanted collector (SIC)
Higher
collector
doping
Selectively
implanted
collector
Higher collectorbase capacitance
Lower f max
Retarded Kirkeffect
Higher fT
Higher fT
and reduced
degradation
of f max
UTA Noise and Reliability Laboratory
Reduced
base-width by
compensation
of boron tail
50
Effect of selectively implanted collector
-2
10
SIC:25-10-25
25-10-25
I
10
150
B
B
C
I , I (A)
-8
200

-10
10
100
noise
measurement
region
-14
0
V
BE
~I
-20
10
1
-21
10
-7
10
(V)

SIC retards Kirk-effect

No degradation in noise.
2
B
50
10
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
-19
10
2
C
IB
I
-6
10
-12
SIC:25-10-25
25-10-25
250
S .f (A ) at 10 Hz
10
10
10
current gain: 
-4
-18
300
-6
10
-5
10
I (A)
B
higher β for wider range of bias.
UTA Noise and Reliability Laboratory
51
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
52
Higher extrinsic base implant (HEBI)
High dose
implantation
in extrinsic
base
Higher f max
Smaller base
resistance
Lower RF
noise figure
UTA Noise and Reliability Laboratory
53
Effect of higher extrinsic base implant
-2
SIC:25-10-25
HEBI,SIC:25-10-25
400
C
B
300
-8
10
B
C
I , I (A)
I
200

-10
10
~I
2
B
-20
10
100
-12
10
SIC:25-10-25
HEBI,SIC:25-10-25
-21
-14
10
-19
10
2
I
-6
10
IB
10
noise
measurement
region
S .f (A ) at 10 Hz
-4
-18
10
500
current gain: 
10
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
BE


1
0
10
-7
10
(V)
-6
10
-5
10
I (A)
B
Higher gain for higher extrinsic base implant is
possibly due to relative changes in Ge profile.
No degradation in noise.
UTA Noise and Reliability Laboratory
54
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
55
SiGe epi-SiGe poly interface
Non-selective
epitaxial
growth of
SiGe base
smaller distance
between SiGe
epi-SiGe poly
interface &
intrinsic base
SiGe epi
on top of
exposed Si
SiGe poly
on top of
shallow
trench
Smaller basecollector
capacitance
UTA Noise and Reliability Laboratory
Interface of
epitaxial and
polycrystalline
SiGe
Higher f max
Higher fT
56
Effect of SiGe epi-SiGe poly interface
-2
10
-4
10
I
C
10
-12
10
100

-10
noise measurement
region
-14
10
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
BE


1
~I
2
B
2
B
-19
10
-20
10
IB
B
10
S .f (A ) at 10 Hz
I
-8
10
current gain: 
150
SIC:20-20-40
SIC:20-10-25
-18
200
-6
C
10
SIC:20-10-25
SIC:20-20-40
10
I , I (A)
-17
250
-21
50
10
0
10
-22
-7
10
-6
-5
10
(V)
10
-4
10
I (A)
B
No significant impact on DC characteristics.
No degradation in noise; boron implantation in extrinsic
base passivates the interface-defects.
UTA Noise and Reliability Laboratory
57
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
58
Effect of emitter-poly overlap
SIC:20-10-25
-10
10
SIC:10-10-25
10
~ 1/f
-11
-11
2
2
(V /Hz)
10
(V /Hz)
~ 1/f
-10
-12
-12
10
S
S
VC
VC
10
10
-13
10
I = 0.5uA
-13
10
I = 0.5 A
B
I = 1uA
B
B
I = 1 A
-14
10
I = 4uA
-14
10
B
I = 4 A
B
I = 10uA
B
B
-15
10
-15
0
10
1
10
2
10
Frequency (Hz)


3
10
10
0
10
1
10
2
10
3
10
Frequency (Hz)
Significant g-r noise for smaller emitter-poly overlap.
g-r noise diminished at higher currents in comparison to
increased 1/f noise.
UTA Noise and Reliability Laboratory
59
Effect of emitter-poly overlap (cont.)
-4
-17
10
10
SIC:25-10-25
SIC:20-10-25
SIC:10-10-25
-18
10
2
S .f at 10 Hz (A )
-6
10
B
I (A)
-8
10
-10
10
 = 3.08
-12
SIC:25-10-25
SIC:20-10-25
SIC:10-10-25
10
-14
-22
10
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
V
BE

-20
10
-21
10

2
B
IB
r
~I
-19
10
1
10
-7
10
(V)
-6
-5
10
10
-4
10
I (A)
B
Higher non-ideal base current for smaller emitter-poly overlap.
SIB deviates from ~IB2 dependence for smaller emitter-poly
overlap.
UTA Noise and Reliability Laboratory
60
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
UTA Noise and Reliability Laboratory
61
Physical origin of SIB
-17
2
10
20-20-40
SIC:20-20-40
10-20-40
SIC:10-20-40
25-10-25
2
smaller emitter-poly
overlap (x = 0.1 m)
1.8
-19
1.6
10
~I
2
AF
S .f at 10 Hz (A )
-18
10
B
-20
1.4
10
IB
SIC:25-10-25
SIC:20-10-25
-21
1.2
SIC:10-10-25
HEBI:25-10-25
HEBI,SIC:25-10-25
10
-22
10
1
-7
10
-6
-5
10
10
-4
10
1
1.5
B
All except smaller emitter-poly overlap

Smaller emitter-poly overlap
2.5

I (A)

2
3
3.5
4
r
ηr≤1.6, AF≈2.
ηr>3, AF≈1.
UTA Noise and Reliability Laboratory
62
SIB model
i
2
KF1   I B
i
1  ( 2f i ) 2
N1
2
S I B  KF1  I B
AF  2
N 1 : Total number of
 i : Characteristics time
constant of ith trap.
traps in emitterbase junction.
SRH g-r centers
in E-B depletion
region
Capture and
emission of
carriers
Continuous
distribution of
time constants
Superposition
of Lorentzians
UTA Noise and Reliability Laboratory
Perturbation
in free carrier
density
1/f noise
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Noise from Surface recombination current
Smaller emitterpoly overlap
Extrinsic base
moves closer to
emitter perimeter
Two parallel
BJTs
n+ poly Si emitter
dielectric isolation
n+ Si emitter
p SiGe epi
(intrinsic base)
n+ emitter - p+
extrinsic base
diode
n+ emitter,
p SiGe
intrinsic
base,
collector
n+ emitter,
p+ SiGe
extrinsic
base,
collector
p+ SiGe epi
(extrinsic base)
Thin depletion
region & high
electric field
UTA Noise and Reliability Laboratory
Recombination
through trap
assisted tunneling
64
SIB model for smaller emitter-poly overlap
From surface of
E-B junction
From intrinsic
E-B junction
AF  1
S I B  KF  I BAF
S I B  KF1  I 2  KF2  I 2
Bv
Bs
KF2 
N 2 : Oxide slow state
volume density.
A : Area of surface
region.
q 4 N 2
2 f
KTAC sc
 : Attenuation
tunneling distance.
C sc : Surface capacitance
per unit area.
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65
Separation of SIB components
1.E-03
S I B  KF1  I 2  KF2  I 2
Bv
Bs
1.E-04
1.E-05
1.E-06
IBv = IB - IBs
IB(A)
1.E-07
SIB
1.E-08
I2
1.E-09
Bs
1.E-10
IBs
ηr = 1.47
1.E-11
 KF1
I2
Bv
 KF2
2
I
Bs
1.E-12
1.E-13
ηi = 1.09
1.E-14
1.E-15
0
0.2
0.4
0.6
VBE(V)
0.8
qV
I B s  I B so  exp( BE )
 r KT
1
N 2 = 9.65x1015 ~ 3.08x1016 /eV/cm3.
Published values = 1017 ~ 1018 /ev/cm3.
Uncertainties in  and C sc .
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66
Outline




Introduction:

Limitations in existing noise models.

Importance and motivation of research.
Noise in polysilicon emitter bipolar transistors:

Experimental setup.

SIB modeling:
 noise mechanisms, effect of bias, geometry and IFO.

SIC modeling:
 noise mechanisms, effect of bias and IFO.

SVr modeling:
 Collector-emitter measurement setup, effect of bias and IFO.

Computer codes.
Noise in SiGe heterojunction bipolar transistors:

Dominant noise source.

Effect of selective collector implant.

Effect of higher extrinsic base implant.

Effect of SiGe epi-SiGe poly interface.

Effect of emitter-poly overlap.

Physical origin and modeling of SIB.
Conclusion
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67
Conclusion
Polysilicon emitter bipolar transistors:




The base current fluctuations dominate at
relatively high external base resistance values.
Collector current fluctuations contribute when the
external base resistance becomes comparable to
or less than the input resistance.
Fluctuations caused by the internal emitter
resistance take over for high currents with small
base resistance.
From the dependence of noise magnitude on the
geometry and temperature, fluctuations in the
non-ideal base current was neglected.
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68
Conclusion (cont.)




SIB originates from diffusion fluctuations of minority
carriers in poly and monosilicon emitter, and
tunneling fluctuations of minority carriers at IFO; SIC
from diffusion and number fluctuations of minority
carriers in base, and SVre from tunneling fluctuations
of majority carrier at IFO.
Diffusion fluctuations dominate over the tunneling
fluctuations for larger devices; tunneling
fluctuations dominate over diffusion fluctuations for
the smaller ones.
IFO increases the current gain significantly in NPN;
both tunneling and diffusion fluctuations contribute.
No significant improvement with increasing IFO
thickness in PNP; diffusion fluctuations dominant.
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Conclusion (cont.)
SiGe heterojunction bipolar transistors:
 Selectively implanted collector causes higher current
gain for wider range of bias; no noise degradation.
 No significant effect of SiGe epi-SiGe poly interface
and higher extrinsic base implant.
 Severe impact of smaller emitter-poly overlap:
 increases non-ideality of the base current; trap
assisted tunneling current due to parasitic BJT.
 g-r noise at lower bias currents.
 At higher bias currents, fluctuations from trap
assisted tunneling current contribute.
 For all transistors except smaller emitter poly
overlap, noise originates from intrinsic E-B junction.
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70
Acknowledgements



Supervising Professor:
Zeynep Celik-Butler
Semiconductor Research Corporation:
Texas Instruments Inc.
National Semiconductor Corporation
Texas Higher Education Board, Advanced Technology Prog.
UTA Noise & Microsensor Group:
 Bigang Min, Siva P. Devireddy, Shadi Dayeh, Enhai Zhao
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