ECE 340 Lecture 35
MOS Field-Effect Transistor (MOSFET)
• The MOSFET is an MOS capacitor with Source/Drain terminals
GATE LENGTH, Lg
• How does it work?
 Gate voltage (VGS) controls
mobile charge sheet under
_______________
OXIDE THICKNESS, Tox
Gate
Source
Drain
Substrate
JUNCTION DEPTH, Xj
 Source-drain voltage (VDS) sweeps
the mobile charge away, creating ____________ (ID)
• Desired characteristics (remember water faucet analogy):
 “On” current __________________
 “Off” current___________________
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
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• First MOSFET patents: Julius Lilienfeld (early 1930s)
• This invalidated most of Bardeen,
Brattain and Shockley’s transistor
patent claims in the late 1940s!
• But the MOSFET did not work in
practice until the 1960s. Why?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
2
• A modern “n-type” MOSFET (N-MOSFET):
• How does it work?
 If VG = 0, any current between source-drain (ID)?
 If VG > 0 what happens (assume source grounded, VS = 0)
 If VGS >> 0 and VDS > 0 what happens?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
3
• Typical 2-D cross-section view of the N-MOSFET:
• Note direction of carrier flow,
and of current flow
• Gate voltage (VGS) controls
Source-to-Drain current (ID)
• “Source” terminal refers to source of _____________
NMOS
PMOS
ID
P+ poly-Si
N+ poly-Si
N+
P+
N+
P-type Si
© 2012 Eric Pop, UIUC
ID
VGS
P+
n-type Si
ECE 340: Semiconductor Electronics
VGS
4
• Theory of the MOSFET (*here N-MOSFET):
 When VGS < VT the channel
is _________________
depletion layer
 When VGS > VT the channel
is _________________
 If small drain voltage (VDS > 0)
is applied __________
• Will charge sheet move by drift or diffusion?
Current ≈ width X charge sheet X velocity
• What is the inversion charge: |Qinv| ≈
• What is the drift velocity: v ≈
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
5
• At low VDS, the inversion layer essentially acts like a resistor!
I DS  ZQinv v  ZCi VGS  VT  eff 
 VDS 
 ZCi VGS  VT  eff 

L


• What about higher drain voltages VDS?
• Must take into account variation of potential along channel, 0 < Vx
< VDS. So inversion layer charge at any point is
|Qinv(x)| = Ci(VGS – VT – Vx)
• And the current is:
IDS,lin =
VDS
Z

 eff Ci  VGS  VT 
L
2


 VDS

• Still linear in VGS voltage! This is the linear region.
• When VDS = VGS – VT the channel becomes _____________
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
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• When VDS > VGS - VT the un-inverted (drain depletion) region
increases, as does the ____________________
• Any increase in VDS:
 Reduces the amount of inversion charge, but…
 Increases the lateral field (charge velocity)
• The two effects cancel each other out, so at high VDS the drain
current is no longer a function of VDS! The current saturates to a
value only dependent on VGS (i.e. charge).
• Putting in VDS = VGS – VT (the pinch-off, i.e. saturation condition)
in the previous equation:
I DS , sat
© 2012 Eric Pop, UIUC
1Z

eff Ci (VGS  VT ) 2
2L
ECE 340: Semiconductor Electronics
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• Plot and label an example N-MOSFET:
Z
dox
VT
• What about IDS vs. VGS?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
8
• Back to the physical picture,
why does ID vs. VDS saturate?
• Why is this desirable?
 Voltage gain, dVDS/dID because
small changes in ID cause large
swings in VDS
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
9
• What is the “effective mobility” μeff in the MOSFET channel?
• Can we look it up in the bulk-silicon charts?
(Vgs + V t + 0.2)/6Toxe (MV/cm)
(NFET)
• Scattering mechanisms
affecting mobility in channel:
 Charged impurity (Coulomb) scattering
 Lattice vibration (phonon) scattering
 Surface roughness scattering
© 2012 Eric Pop, UIUC
(PFET)
–(Vgs + 1.5V t – 0.25)/6Tox e (MV/cm)
ECE 340: Semiconductor Electronics
10
ECE 340 Lecture 36
MOSFET Analog Amplifier and Digital Inverter
• Analog applications: Small-Signal MOSFET model
• Of all elements in the model… CGS ~ Ci and gm
(transconductance dID/dVGS) are essential, the rest are parasitics
which must be reduced
• Note that a lot of elements are voltage-dependent, e.g. depletion
capacitances vary with depletion widths and voltage
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
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At low frequency
At high frequency
• Drain current: id  g d vd  g m vg
• Conductance parameters:
gd 
gm 
I D
VD
I D
VG
  I Dsat 0
output conductance
VG  const

VD  const
Z
eff Ci (VGS  VT )
L
transconductance
• See ECE 342, ECE 441
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
12
• Cutoff frequency fmax = frequency where MOSFET no
longer amplifies input (gate) signal
• Obtained by considering high-freq. small-signal model
with output shorted, finding freq. where |iout/iin| = 1
f max 
eff
gm
1

(
V

V
)

GS
T
2 Ci 2 L2
L2
• Something we already knew qualitatively  higher
MOSFET operating frequency
achieved by decreasing channel
length L, increasing mobility μeff
• Smaller = faster for devices
(though parasitics play a big role
in realistic circuits)
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
13
• Logic applications: CMOS inverter
• Key property: signal regeneration – returns logic outputs
(0 or 1=V+=VDD) even in presence of noise
• Complementary MOS (CMOS) inverter
N Well
VDD
CIRCUIT SYMBOLS
N-channel
MOSFET
VDD
P-channel
MOSFET
PMOS
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
• Qualitative operation:
 When Vin = 0  Vout =
NFET is ________ PFET is __________
 When Vin = VDD  Vout =
NFET is ________ PFET is __________
• Other key property of CMOS inverter: no power consumption
while idling in either logic state (only while switching)
• Consider PFET as “load” to NFET:
• Note “rail-to-rail” logic levels 0 and VDD
• Want transition voltage VDD/2, but usually
Lp = Ln which means choose Zp/Zn ≈ 2
because μn ≈ 2μp (for Si)*
*what about other materials?
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
15
• A quick look at CMOS power dissipation
• Energy consumed while charging capacitive load: EP = _______
• CL is discharged through NFET  EN = _________
• Total energy dissipated per clock cycle: E = CLVDD2
• Frequency f cycles per second  active power P = fCLVDD2
• This is very important: fundamental trade-off between speed (f) and
power dissipation. Reducing voltage and parasitic C’s is a must to keep
power low at higher speeds.
© 2012 Eric Pop, UIUC
ECE 340: Semiconductor Electronics
16
• In reality, there is also passive power (leakage) dissipated by the
FETs supposed to be “off”: Poff = IleakVDD
• Ioff ~ Ion/1000 in modern technology per transistor
• But this can become a headache when you have 100s of millions of
“sleeping” transistors (i.e. “passive power” vs. “active power”)!
1000
Power (W/cm2)
1E+03
Tox (C )
100
10
classic scaling
1
Vdd (V)
0.1
Gate Length, Lgate (um )
© 2012 Eric Pop, UIUC
1E+01
1E+00
1E-01
1E-02
1E-03
Passive Power Density
1E-04
1E-05
0.01
Vt (V)
0.1
0.01
Active Power Density
1E+02
0.1
1
Gate Length (μm)
1
Ex: see IBM journal of Research & Dev.
http://www.research.ibm.com/journal/rd/504/tocpdf.html
ECE 340: Semiconductor Electronics
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