記
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3675
編
號
狀
NC089FJU00428009
態
助
教
查
核
索
書
號
學
校
輔仁大學
名
稱
系
所
電子工程學系
名
稱
舊
系
所
名
稱
學
488506103
號
研
究
生 陳世倫
(
中
)
研
究
Shih-Lun Chen
生
(
英
)
論
文
名
稱 深次微米高速連接線的設計與分析
(
中
)
論
文
名
稱 Design and Analysis of High-Speed Interconnection in Deep Sub-Micron Process
(
英
)
其
他
題
名
指
導
教
授 黃弘一
(
中
)
指
導
教
授 Hong-yi Huang
(
英
)
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學
位
碩士
類
別
畢
業
學 89
年
度
出
版
年
語
文 英文
別
關
鍵
字 深次微米 連接線 感測放大器 加速器 介面電路 高速積體電路 單一系統晶片
(
中
)
關
鍵
字 Deep Sub-Micron interconnection sense amplifier accelerator interface circuit High-speed
( VLSI system-on-a-chip
英
)
摘
要
(
中
)
隨著VLSI製程上的進步，以及SOC (System-on-Chip)之單一系統晶片整合的趨勢，邏
輯閘延遲 (Gate Delay)因元件 (Device)尺寸的縮小 (Scale down)而減小；而IC內部的連
接線 (Interconnection)卻隨著IC變大而變長，且隨著製程的進步，連接線之線寬變窄
，反而造成更大的連接線延遲 (Interconnect Delay)，使得整個晶片的延遲 (Delay
Time)將被連接線延遲所主宰。改善連接線延遲的方法可分為製程上的改進，跟利用
電路技巧來改善。在製程上，利用銅製程和低介電常數 (Low Dielectric)的製程來改
善連接線實際電阻、電容值。在電路技巧上，則使用特殊的電路來當接收器，使連
接線延遲減小。 在本論文裡，我們提出的新型電路於下： 1.三個新型的輸入隔絕感
測放大器 (Input Isolated Sense Amplifiers)。 2.兩種新型減低連接線擺幅的驅動器
(Drivers)。 3.一種新型的接收器-電容耦合接收器 (Capacitor Coupling Trigger)。 4.一
種新型的加速器-電容耦合加速器 (Capacitor Coupling Accelerator)。 5.一種改良型的
輸入隔絕感測放大器。 我們利用輸入隔絕感測放大器來當連接線的接收器(Receiver)
來改善連接線延遲。並且提出減小連線擺幅的Driver。除此之外，輸入隔絕感測放大
器還可應用在記憶體(Memory)和高速差動邏輯電路(High-Speed Differential Logic
Circuit)的應用上。電容耦合加速器是直接接在連接線上，來增加連接線上訊號的變
化。另外，其最大特點是可以應用在雙向(Bidirection)傳輸的訊號線上。 在本論文裡
，除了用HSPICE來模擬驗證論文裡所提出的電路，並利用輸入隔絕感測放大器和電
容耦合加速器分別設計成除頻器(Frequency Divider)和震盪器(Ring Oscillator)，以
TSMC 0.35μm 1P4M的製程，實現兩顆實際的晶片來做電路驗證。
摘
要
(
英
)
In the deep sub-micron era, the interconnect delay takes the major part of the large
dimension ICs. On one hand, the dimension of the Metal Oxide Silicon Field Effect
Transistor (MOSFET) is scaled down as the VLSI process has been made great progress.
On the other hand, the interconnection width is so narrow that the resistance and the
capacitance of the interconnection become larger. Besides, a single IC possibly contains an
entire system (system-on- chip (SOC)). The transistors on a single chip are increasing
rapidly and the global interconnections become extremely long at the present day.
Therefore, the interconnect delay dominants the global chip delay in very deep sub-micron
era. Various methods of reducing the interconnect delay have been investigated. One of
them is to replace the material of the interconnection from aluminum to copper to reduce
the resistivity. Another is to use a lower dielectric constant material as the interlevel
dielectric insulator between layers of interconnections. The others are to insert the
repeaters, accelerators or to use special receivers for the reduction of long interconnection
RC delay. In this thesis, we propose several new circuits. 1.Three types of input isolated
sense amplifiers (IISAs). 2.Two types of reduced swing driver (RSD). 3.One type of
capacitor coupling trigger (CCT). 4.One type of capacitor coupling accelerator (CCA).
5.One type of modified input isolated sense amplifier (MIISA). The IISA is a differential
circuit that has better noise immunity compared to single-ended receiver. The input
terminal of IISA and the input terminal of the core differential amplifier are initially
connected and then separated which results in smaller input capacitance at the input
terminal of the core differential amplifier during the operation. The IISA not only has a
positive feedback at the output nodes, but the input signals. Thus the voltage gain can be
increased. The IISA can also be applied to the memory design and the receiving of large
capacitive load signals. The CCT can be used as a receiver to speed up the detection of
signal transition. The CCA can be operated without extra control signal. The CCA can also
be applied to bi-directional signal transmission. In addition to the simulation of the
proposed circuits, two test chips with experimental circuits are designed and measured to
verify the speed performance of the long interconnection design.
論
文
目
次
致謝 摘要 Abstract List of Contents List of Figures List of Tables List of Nomenclatures
Chapter 1 Introduction
1.1Motivation…………………………………………………………………………1
1.2Analysis of Interconnection………………………………………………………..2 1.2.1
Different Driver Size………………………………………………………...2 1.2.2
Different Interconnection Length……………………………………………5 1.2.3 CrossTalk……………………………………………………………………8 1.3Thesis
Organization………………………………………………………………12 Chapter 2
Review of Interface Circuits 2.1 Low-Swing Interface
Circuits……………………………………………………13 2.1.1 Conventional Level
Converter...………………………………………….13 2.1.2 Symmetric Level
Converter...…………………………………………….14 2.1.3 Pulse-Controlled Driver
with Sense Amplifier...…………………………15 2.1.4 Reduced Swing Driver with
Voltage Sense Translator……………………16 2.1.5 Symmetric Source Follower
Driver………………………………………17 2.1.6 Asymmetric Source Follower
Driver……………………………………..18 2.1.7 Dynamic Over-Driving and Adaptive
Sensing Level Converter…………20 2.1.8 NMOS-Only Push-Pull Driver and Level
Converter with Low-Vt
Devices………………………………………………………………….20 2.1.9 CapacitiveCoupled Level Converter……………………………………..20 2.1.10 Level-Converting
Register………………………………………………21 2.2 Transient Sense
Accelerator……………………………………………………...22 2.2.1 Transient Sense
Trigger…………………………………………………...22 2.2.2 Transient Sense
Accelerator…………………...………………………….23
2.3Comparisons……………………………………………………………………...24
Chapter 3 Input Isolated Sense Amplifiers 3.1 Introduction to Sense
Amplifiers……………………………………………..….26 3.2 Precharged Input Isolated
Sense Amplifier………………………………………30 3.3 Non-precharged Input Isolated
Sense Amplifier…………………………………34 3.4 Capacitor Input Isolated Sense
Amplifier………………………………………..35 3.5 Modified Input Isolated Sense
Amplifier………………………………………..37 3.6 Driver
Design…………………………………………………………………….38 3.7 Control
Signal Design……………………………………………………………44 3.8 Simulations
and Comparisons……………………………………………………46 3.9 Test
Chip………………………………………………………………………….50 Chapter 4
Capacitor Coupling Accelerator and Capacitor coupling Trigger 4.1 Capacitor Coupling
Technique and Its Implementation ……………….………...52 4.2 Capacitor Coupling
Trigger………………………………………………………53 4.2.1 High-Threshold
Capacitor Coupling Trigger……………………………..53 4.2.2 Low-Threshold Capacitor
Coupling Trigger……………………………...56 4.3 Capacitor Coupling
Accelerator………………………………………………….58 4.4 Simulations and
Comparisons……………………………………………………62 4.5 Test
Chip…………………………………………………………………………65 Chapter 5
Conclusions and Future Work 5.1
Conclusions………………………………………………………………………67 5.2
Future Work………………………………………………………………………68
Reference……………………………………………………………………………..69 List
of Publications
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參
Delay of VLSI Circuits,” IEEE Journal of Solid-State Circuits, vol. SSC-17, pp. 275-280,
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Advanced Semiconductor Manufacturing Conference and Workshop, pp. 337—346, 1998.
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Redeker, V. Rana, B. Tang, and D. Yost, “Process Integration of Double Level CopperLow k (k=2.8) interconnect”, IEEE International Conference on Interconnect Technology,
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IEEE International Conference on Solid-State and Integrated Circuit, pp. 43-46, 1998.
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Hu, O. Sam Nakagawa, and Soo-Young Oh, “Interconnect Scaling: Signal Integrity and
Performance in Future High-Speed CMOS Designs,” IEEE International Symposium on
VLSI, pp. 42-43, 1998. [8]Yehea I. Ismail and Eby G. Friedman, “Optimum Repeater
Insertion Based on a CMOS Delay Model for On-Chip RLC Interconnect,” IEEE
International ASIC Conference, pp. 369-373, 1998. [9]Yanbin Jiang, Sachin S. Sapatnekar,
Cyrus Bamji, and Juho Kim, “Interleaving Buffer Insertion and Transistor Sizing into a
Single Optimization,” IEEE Transactions on VLSI Systems, vol. 6, no. 4, pp. 625-633, Dec.
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Gerorge and J. M. Rabaey, “Low-Swing On-Chip Signaling Techniques: Effectiveness and
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Colshan and B. Jaroun, “A Novel Reduced Swing CMOS BUS Interface Circuit For High
Speed Low Power VLSI Systems”, Proc. IEEE International Symposium on Circuits and
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Current Sensing Scheme for CMOS SRAM,” IEEE International Workshop on Memory
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Capable of High Speed Operation”, U.S. Patent 5079745, Jan. 7, 1992. [19]C. G. Douglas,
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[20]G. V. Kristovski and Y. L. Pogrebney, “New Sense Amplifier for Small-Swing CMOS
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Seki and Tatsuji Matsuura, “Sense Amplifier, SRAM, and Microprocessor,” U.S. Patent
5534800, July 9, 1996. [22]Michael Anthony Ang, “Charge transfer sense amplifier,” U.S.
Patent 5668765, Sep. 16, 1997. [23]M. Matsui et al., “200 MHz Video Compression
Macrocells Using Low-Swing Differential Logic,” IEEE International Solid-State Circuits
Conference, pp. 76-77, Feb. 1994. [24]Alina Deutsch, Geraed V. Kopcsay, Phillip J. Restle,
Howard H. Smith, G. Katopis, Wiren D. Becker, Paul W. Coteus, Christopher W. Sorovic,
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IEEE International Symposium on Circuits and Systems, pp. 634-637, 2001. [26]Masataka
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Watanable and Akihiko Chiba, “A 200 MHz 13mm2 2-D DCT Macrocell Using SenseAmplifying Pipeline Flip-Flop Scheme”, IEEE Journal of Solid-State Circuits, pp.14741481, Dec. 1994. [27]Borivoje Nikolic, Vladimir Stojanovic, Vojin G. Oklobdzija, Wenyan
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