Multi-Disciplinary Senior Design Conference
Kate Gleason College of Engineering
Rochester Institute of Technology
Rochester, New York 14623
Project Number: P09141
THERMAL HEATER CONTROLLER
Anthony Berwin/Mechanical Engineer
John
Scipione/Electrical
Engineer
Scott Rioux/Industrial Engineer
Greg Pawlowski/Electrical
Engineer
ABSTRACT
The satellite thermal heater controller is a single
master multiple slave system that is arrayed in a
distributed fashion with centralized control. The
design is used in satellite applications to control the
temperature of critical optical subsystems. Currently
dedicated data and power lines are run between the
master controller and the many slave controllers. The
purpose of this project is to eliminate the data lines by
instead communicating directly over the power bus.
The fundamental challenge with this design is
producing effective and reliable communication over
the power bus. However, the benefits include higher
performance,
decreased
power
consumption,
decreased overall weight, and improved thermal
performance when compared to the current system.
This design reduces the power consumption and
weight used adding considerable value and extending
the products life cycle.
The controllers are
implemented using multiple DSPs connected via
power lines. A GUI is developed to allow the end user
to monitor telemetry and also update the settings on
the DSP units.
NOMENCLATURE
GUI: Graphical User Interface, used to link the human
element to the machine element to allow control.
ASCII: Communication method that is used to send
data from the GUI to the DSP’s and back.
SCI: The communication protocol that is used to
communicate from the GUI to the DSP and back.
Sarmad
Abedin/Electrical
Engineer
FSK: Frequency shift keying, type of communications
being used.
PWM: Pulse width modulation, used to modulate the
FSK signal.
ADC: Analog to digital converter, used to demodulate
the FSK signal.
DSP: Digital Signal Processor. A microcontroller.
Goertzel: An algorithm used to emulate the Fast
Fourier Transform using a microcontroller. Useful for
frequency detection.
INTRODUCTION (OR BACKGROUND)
Satellite systems take decades to create and
implement. Following this long development process
there is only one shot at getting the system to work in
space. Sending a satellite into space is the last time
anyone will touch it which means that all the
components have to be tested and work perfectly
before they are sent on the satellites first and final
mission. The cost associated with sending a satellite
into space is immense and is directly proportional to
the weight of the system. Therefore, any weight
reduction is greatly desired. Another key problem with
space devices is power. Satellites get all of their power
from battery arrays which are charged via solar panels.
Since solar energy is not the most direct and efficient
way of creating power, power is a luxury on board a
satellite. Therefore the heater controller system has to
be as efficient as possible and must deal with the
fluctuating power supply with spikes and irregularities
on the power bus.
Copyright © 2009 Rochester Institute of Technology
Once the two fundamental problems of power and
weight of a system were considered, the design
concepts for the heater controller were developed. A
traditional design approach is to run dedicated lines
from the master controller to each slave controller. To
minimize weight and power, the communications
between the master and slave controllers is done over
the main power bus. Separate communication wires
are not be needed. This presented the main and most
difficult design challenge of the project. One controller
must produce an AC signal and pass it over the power
line. The receiving controller must decode and
interpret what the other controller is sending. The
DSP’s themselves are going to have to be controlled
from an end user, which means the development of
some sort of GUI. This function needs to be able to
control all aspects of the DSP’s and be able to
monitor them.
PROCESS (OR METHODOLOGY)
The first phase of the design process involved doing
concept development. By engaging with the customer
a set of requirements and relevant data was collected
and then translated into the customer needs and
specifications. Gathering needs data from the customer
was an ongoing process, but, most of the needs were
established soon after the start of the project.
Customer needs were organized into three priorities,
must haves, should haves, and niceties. The list was
refined and reorganized until an essential list was
produced. A full treatment of the process of gathering
and refining the customer needs can be found in the
references. (1)
Once the customer's needs were laid down, concrete
measurements were gathered into specifications. As
with the needs requirements, the specifications were
updated over time but the most important
specifications were established early on. Eventually a
final list of specifications was nailed down. A full
treatment of the process of gathering and refining the
specifications can be found in the references. (2)
A high level system overview was developed using the
customer needs and specifications. This was distilled
into a block diagram of the project. Once the high
level overview of the design was complete, each of the
individual blocks were split up so that they could be
developed separately. A communication protocol was
established. A modulation and demodulation
technique was developed. Interface electronics to
condition the AC and DC portions of the signal were
designed.
An enclosure was specified. A GUI
interface was designed.
Once the major subsystems of the project were
established, the designs were evaluated by the
customer and by faculty in order to ensure that the
designs was feasible. Each of the major subsystem
went through several iterations of evaluation and
redesign before a final design was selected.
Once the major subsystems were established, the
culmination of each of the subsystems was combined
into a detailed design package. This final package was
again reviewed and refined until the entire design was
declared finished.
With the final design established a large amount of
programming had to be done to realize the design.
Many of the subsystems involved programming the
DSP to emit and detect the needed signals. For
instance, the PWM on the DSP had to be programmed
to produce a sine wave at the appropriate frequencies.
The DSP, using the ADC, also had to be programmed
to detect those same frequencies implementing the
Goertzel algorithm. The GUI also had to be
programmed to emit the correct protocol. A separate
protocol had to be programmed in order to enable the
DSPs to communicate. At first, each piece was
programmed and tested separately. Once the various
pieces of the design were completed they had to be
integrated together and tested to make sure that they
worked together. This involves sending a signal from
the GUI and have it go through the master DSP to the
slave DSP and back again.
The final product was built and tested. The final build
was then compared against the needs and
specifications to see how it matched up.
RESULTS AND DISCUSSION
The Texas Instruments TMS320F2808 DSP is used to
communicate between the master and slave DSPs over
the 22 AWG wire. Because only one communication
wire is available FSK signal generation is necessary to
communicate between the two DSPs. The transmitted
FSK signal is generated using the pulse width
modulator (PWM) of the TMS320F2808 of the
EZDSP. The transmitted signal will pass through a
passive low-pass filter to smooth the signal and
generates a sine wave.
The PWM signal outputs on a TMS320F2808 device
are variable duty cycle square waves with 3.3 volt
amplitude. These signals can each be decomposed into
a DC component plus a new square wave of identical
duty-cycle but with a time-average amplitude zero.
The idea behind realizing digital-to-analog (DA)
output from a PWM signal is to apply an analog lowpass filter the PWM output to remove most of the high
frequency components leaving only the DC
component. The bandwidth of the low-pass filter will
essentially determine the bandwidth of the digital-toanalog converter.
Two main sources of error negatively affect the DA
output. Firstly, the PWM duty cycle can only be
specified with a finite resolution. The resolution is
directly related to the PWM carrier frequency used.
For example, suppose 100 kHz PWM is desired with
the PWM module driven by a 100 MHz
SYSCLKOUT. The time-base of the PWM will
provide 1000 clock counts per cycle of PWM at which
to specify the timer compare value. This directly
affects the duty cycle. If the standard PWM is used,
the resulting resolution is just less than 10-bits. The
desired DC output is specified in steps of 3.3 mV
(3.3V/1000). However, using the enhanced PWM
module (ePWM) provides approximately 6 additional
bits of resolution beyond the standard time-base
resolution. This equates to just under 16 bits of
resolution.
The second source of error is the peak-to-peak ripple
produced by unfiltered harmonics. The two error
sources sum together to yield the total uncertainty:
total uncertainty = harmonic ripple + duty cycle
resolution
The duty cycle resolution can be improved by
decreasing the carrier frequency of the PWM.
Reducing the carrier frequency from 100 kHz to 50
kHz will cut the step size in half to 1.65 mV (~11 bits
resolution for the standard resolution PWM or ~17 bits
resolution for the high resolution PWM). The lower
carrier frequency also decreases the base frequency of
the unwanted harmonics. The first harmonic will now
appear at 50 kHz rather than 100 kHz, and more of it
will pass through the analog low-pass filter increasing
the harmonic ripple.
For a given analog low-pass filter a trade-off exists
between the harmonic ripple and PWM duty cycle
resolution when selecting the PWM carrier frequency.
The optimal carrier frequency is the one where the
total uncertainty is smallest.
The performance of the filtered PWM as a digital-toanalog converter depends heavily on the choice of the
analog low-pass filter chosen. Active filters (built
using op-amps) are often used rather than passive
filters (built solely using resistors, inductors, and
capacitors). Although active filters avoid the
impedance loading issues suffered by passive filters,
passive filters can offer lower cost and reduce
complexity. The gain bandwidth of the op-amps must
be considered when using active filters. The gain
bandwidth represents the upper frequency that the opamp can effectively handle when used in a closed-loop
circuit configuration with small signal input. However,
passive filters do not suffer as much from a gain
bandwidth problem, although they do have their own
high-frequency design issues (especially in designs
that utilize inductors).
The two most important filter properties when
selecting a low-pass filter are the bandwidth and the
stop-band roll off rate. The filter bandwidth is the
frequency at which the filter's frequency response
magnitude equals 0.707 (-3 dB). The filter bandwidth
directly relates to the maximum signal frequency that
the PWM/DAC will handle effectively and the stopband roll-off rate is the slope of the frequency
response magnitude at high frequency. Combined with
the bandwidth, the roll-off rate determines the amount
of harmonic ripple that will be seen in the output of
the filter. In general, low-pass analog filters roll-off at
a rate of -20 dB/decade per filter order (-20 dB/decade
for a 1st order filter, -40 dB/decade for a 2nd order
filter, etc.).
For this design, a 2nd-order low-pass passive filter
was chosen. The 2nd-order low-pass filter offers 40
dB/decade of stop-band roll-off -- a two-fold
improvement over the 1st order filter. The step
response of the filter is an important measure of
performance for the practical situation of changing the
DAC output from one voltage level to another. It is
important to get as low a damping ratio as possible in
order to have fast rise times. However, low damping
ratios produce large step response overshoots and long
settling times. The smallest damping ratio with no
overshoot in the step response is ζ=1 (critically
damped). It is also desirable to avoid having a resonant
peak in the frequency response magnitude of the filter.
The smallest damping ratio with no resonant peak is
ζ=0.707 (-3dB). The choice of damping ratio will
depend on the particular requirements of your system.
A reasonable trade-off is often to choose the filter
damping ratio between 0.707 and 1.0.
A passive 2nd order passive RC filter is constructed by
cascading two 1st order RC filters in series.
The following component values were chosen:
R1 = R2 = 1k
C1 = C2 = 0.01uF
This resulted in a cutoff frequency of
ωn = 100kHz
and a dampening ratio of
ζ = 1.5
A cutoff frequency ~100kHz is desirable for this
particular application as it will cutoff most of the
higher harmonic frequencies . The frequencies desired
for this design are between 50Khz and 100Khz.
Higher order filters offer progressively better stopband roll-off rates, and hence remove more of the
unwanted ripple. However, design complexities
associated with thermal drift and component value
variation increase with filter order. Cost and board
space also increases. At some point an actual DAC
chip becomes a better solution than emulating one
with a PWM/DAC.
Using the above designed filter, the next step is to
produce the desired PWM function from the DSP.
The PWM frequency is derived from SYSCLKOUT =
100 MHz. The eZdsp 2808 is clocked from a 20 MHz
oscillator. The CPU clock is initialized with
SysCtrlRegs.PLLCR = 10. So that the CPU clock is
running at CLKIN= 100 MHz. This clock feeds other
module as SYSCLKOUT.
In order to generate the desired frequencies the
SYSCLKOUT is divided down to a more reasonable
frequency used by the HRPWM. The SYSCLKOUT is
divided by 400 to give a PWM clock of 250Khz. The
PWM clock is then divided down a second time to
yield the desired frequency for a binary 0 or 1. For
example
250kHz/4.1667 = 60kHz which represents a binary 0.
250kHz/2.7778 = 90kHz which represents a binary 1.
This PWM clock is fed into a table of sine values to
vary the duty cycle of the output of the PWM. After
the PWM signal is fed through the DAC a sine wave
of the appropriate frequency results. In this way the
PWM/DAC produces the correct frequency for a 0 or a
1. A division factor of 1 can be used to produce no
output since 250Khz is above the cutoff frequency and
thus will be filtered out by the low pass filter.
The ADC is used extensively in this application. The
ADC is used to receive the communications signal
and, to monitor the functionality of the Hybrid Heater
Controller (HHC). Each HHC is made up of 2
controllers and the DC power input circuitry. Each of
the controllers have 3 points that the ADC has to
monitor for a total of 6 monitoring points, the power
input circuitry is monitored at 2 separate points. The
two thermistors on the controller have to be monitored
to calculate the temperature near the optics. The
voltage after the comparator is monitored to make sure
it is turning on and off at the correct times and the
heater power return is also monitored to make sure the
heater is turning on at the specified time, and to make
sure it is functioning. There are two separate points on
the DC power input circuitry that are being monitored,
these are the power input, to make sure the circuit is
receiving the DC input from the power bus and the
input voltage to the controller circuitry to make sure
the controller is receiving the correct DC voltage from
the input circuitry. The monitoring of the HHC
requires 8 separate ADC channels.
After the
monitoring another channel is required to receive the
communications signal from the DC power bus. The
total number of ADC channels required for this
application is 9, but a tenth channel has been set up for
use in future applications.
The ADC's main function is to sample the received
communications signal and demodulate it into its
binary equivalent message. Binary FSK modulation
techniques were used for the communications between
the master and slave. The two frequencies used to
represent a zero and a one are 62.5 kHz and 83.33
kHz. These frequencies were chosen because there is
“chopping” noise on the DC power bus between 20
and 50 kHz so frequencies above this range were
chosen for faster transmitting times out of the range of
the noise. These frequencies were also chosen based
on the calculations used for the Goertzel filter. A
sampling rate of 208.33 kHz was used because it at
least meets the Nyquist criteria and gives the
microcontroller enough time in the ADC interrupt to
do the Goertzel calculations.
The ADC was
configured for this frequency based on the divisions of
the high speed peripheral clock which is 100 MHz.
This sampling frequency was calculated by dividing
the high speed peripheral clock by a factor of 2 times
twelve which is set in an ADC register, then the
sample and hold time was set to 2 clock cycles which
divided the frequency down by a factor of 2 and
finally divided down by another factor of 10, which is
from the number of ADC channels being sampled.
This is how and why the communications and
sampling frequencies were selected.
The most important part of the project is the Goertzel
algorithm.
This algorithm is how the DSP's
demodulate the transmitted BFSK signal.
The
Goertzel algorithm is like a fast Fourier transform in
that it determines the energy of a signal, but unlike the
fast Fourier transform it only determines this for select
target frequencies instead of a range of frequencies.
By looking at the target frequencies (ft), sampling
frequency (fs) and number of samples (N) a coefficient
is determined.
Coefficient = 2*cos(2п*k)
where,
k = integer (N*ft/fs)
After the coefficients for each target frequency are
determined each sample goes through a intermediary
calculation that saves the current calculation and the
previous calculation. After N times there is a final
calculation using the previous calculations and the
coefficients to determine the magnitude squared
(energy) of the signal. By setting a threshold the
frequency is determined if the magnitude squared is
greater than the threshold.
This is how the
demodulation of the signal functions. Synchronization
of the signal was accomplished by setting another
threshold and taking the difference of the current and
previous ADC input. This threshold is set above the
noise threshold so, if a signal is present the difference
is greater than the noise threshold and the Goerztel
algorithm starts to demodulate the message.
In order to properly communicate between the user
interface (LabView) and ‘master’ DSP, an SCI
protocol was adopted. An SCI protocol allows the
streaming of 8 bits in every transmission and
communicates in ASCII format. In order to meet the
objectives of the project, a proper protocol would
allow the user to interact with a slave of its choice and
read/set the temperature of the Hybrid Heater
Controller (HHC). Keeping this in mind, three
transmissions of 8 bits each were developed consisting
of slave ID bits, control bits, and Temperature bits.
In the master DSP, an interrupt routine was developed
to adequately read in the data. A circular buffer was
used with an input and output pointer in order to
ensure that data would not be lost. A structure was
setup for one complete message, consisting of
SlaveID, ControlBits, and TempBits, that would read
and clear the circular buffer in order to allow for it to
read more data.
In order to effectively relay the message to the ‘slave’
DSP over the power bus, the LabView message had to
be properly modified. The 24 bit LabView message
was enhanced with two start bits, a transmit/receive
bit, 5 telemetry bits, an error bit,6 checksum bits, and a
stop bit. The final message that would be sent to the
slaves would now be 40 bits. The start bit would
trigger to the ‘slave’ that a message was being relayed
and the end bit would separate the different messages.
The CheckSum bits are essential to make sure no error
has occurred in the transmission over the power line.
This would count the number of ‘1’s in the message
and output that number in binary format. This value in
binary format would be added to the protocol and
checked by the ‘slave’ that the number of ‘1’s read by
the slave is the same as the number of ‘1’s sent out by
the master. The telemetry bits would allow the slave
to report back to the master the on/off state of 5 key
elements. This is mostly used to pinpoint any faults
that might occur in the HHC. If there occured an error
in the transmission of the message, the error bit was
added in order to request the master to ‘resend’ the
message.
Bits
Description
B0-B1
Start indicator
B2
B3-B10
Tx/Rx bit
Slave ID number
B11
B12
B13
B14
B15
Error bit
Zone/type of error
Read/Set
Temp/Heater State
Read what?
B16
Vdd state (telemetry(tlm) pin)
B17
B18
B19
B20
Bus voltage(tlm pin)
Heater state (tlm pin)
Thermistor (tlm pin)
Transistor gate (tlm pin)
B21-B32 Temp Value
B33-B38 Checksum
B39
Stop bit
The final 40 bit message was relayed to the PWM and
sent out bit by bit over the UART protocol.
CONCLUSIONS AND RECOMMENDATIONS
This section should include a critical evaluation of
project successes and failures, and what you would do
differently if you could repeat the project. It’s also
important to provide recommendations for future
work.
REFERENCES
Using PWM Output as a Digital-to-Analog Converter
on a TMS320F280x
http://focus.ti.com.cn/cn/apps/docs/techdocsabstract.ts
p?appId=270&abstractName=spraa88a
Spread-Frequency Shift Keying Power Line Modem
Software Architecture –
http://focus.ti.com/apps/docs/techdocsabstract.tsp?app
Id=198&abstractName=spraa94
Within the text, references should be cited in
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In the case of two citations, the numbers should be
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Rearward-Facing Step," Technical Report No. HTL26, CFD-4, Iowa State Univ., Ames, IA.
ACKNOWLEDGMENTS
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Example References:
[1] Ning, X., and Lovell, M. R., 2002, "On the Sliding
Friction Characteristics of Unidirectional Continuous
FRP Composites," ASME J. Tribol., 124(1), pp. 5-13.
[2] Barnes, M., 2001, "Stresses in Solenoids," J. Appl.
Phys., 48(5), pp. 2000–2008.
[3] Jones, J., 2000, Contact Mechanics, Cambridge
University Press, Cambridge, UK, Chap. 6.
[4] Lee, Y., Korpela, S. A., and Horne, R. N., 1982,
"Structure of Multi-Cellular Natural Convection in a
Tall Vertical Annulus," Proc. 7th International Heat
Transfer Conference, U. Grigul et al., eds.,
Hemisphere, Washington, DC, 2, pp. 221–226.
[5] Hashish, M., 2000, "600 MPa Waterjet Technology
Development," High Pressure Technology, PVP-Vol.
406, pp. 135-140.
[5] Watson, D. W., 1997, "Thermodynamic Analysis,"
ASME Paper No. 97-GT-288.
[6] Tung, C. Y., 1982, "Evaporative Heat Transfer in
the Contact Line of a Mixture," Ph.D. thesis,
Rensselaer Polytechnic Institute, Troy, NY.
[7] Kwon, O. K., and Pletcher, R. H., 1981,
"Prediction of the Incompressible Flow Over A
Be sure to acknowledge your sponsor and customer as
well as other individuals who have significantly
helped your team throughout the project.
Acknowledgments may be made to individuals or
institution