DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
DESIGN A SIGNAL GENERATOR
USING FPGA
STUDENT
: W0706833
SUPERVISOR
: MAK LIN SENG
PROJECT CODE
: JUL09/BEHE/22
A project report submitted to SIM University
in partial fulfilment of the requirements for the degree of
Bachelor of Engineering
May 2010
DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
ABSTRACT
Signal generator produces alternating current (AC) of the desired frequencies and
amplitudes with the necessary modulation for testing or measuring circuits. Users are
able to know what state the circuit is in when the signals are distorted, attenuated or
missing entirely. Therefore, it is important that the amplitude generated by the signal
generator is accurate.
The objective of this project is to design a signal generator using Field-Programmable
Gate Array (FPGA) to generate a few basics waveform such as square waves,
triangular waves and sine waves. These waveforms will be output to a oscilloscope
since with just the LCD on the FPGA development board is not able to display the
waveforms.
The project will be divided into 3 main areas. The first is the development of different
waveform signals which can be selected, second will be the development of selecting
different frequencies for the waveform output and thirdly is to transfer these signals to
Digital-to-Analog Converter (DAC) which then output to the Oscilloscope.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
ACKNOWLEDGEMENT
I would like to express my gratitude to my supervisor Mr. Mak Lin Seng for his
guidance, constructive suggestion and encouragement has given me a great helped in
providing me a good basis in this project.
I am also grateful to Mr. Min Thu Naung for his patience and precious time in
providing the utmost support for my project.
Special thanks to Xilinx’s field engineer Mr. Felix Keng in favour of providing a
workshop for ISE and FPGA Starter Kit training.
I wish to extend my gratitude to my family and wife, Ms. Shannon Teo for their
understanding and patience throughout this period.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
TABLE OF CONTENTS
ABSTRACT .................................................................................................................. 1
ACKNOWLEDGEMENT ........................................................................................... 2
TABLE OF CONTENTS ............................................................................................ 3
LIST OF FIGURES ..................................................................................................... 6
LIST OF TABLES ....................................................................................................... 8
CHAPTER ONE .......................................................................................................... 9
INTRODUCTION ...................................................................................................... 9
1.1
BACKGROUND .................................................................................................. 9
1.2
OBJECTIVE ..................................................................................................... 10
1.3
SCOPE............................................................................................................. 10
CHAPTER TWO ....................................................................................................... 11
REVIEW OF THEORY AND PREVIOUS WORK DONE..................................... 11
2.1
OVERVIEW OF SIGNAL GENERATOR ................................................................ 11
2.2
SIGNAL GENERATOR BLOCK DIAGRAM .......................................................... 12
2.2.1
Memory Allocation ................................................................................ 13
2.2.2
Waveform Generator Engine ................................................................. 13
2.2.3
Digital Gain ............................................................................................ 13
2.2.4
Digital Filter (Interpolation) .................................................................. 14
2.2.5
Digital-to-Analog Converter .................................................................. 14
2.3
OVERVIEW OF HARDWARE DESCRIPTION LANGUAGE (HDL) ........................ 15
2.3.1
2.4
Review on VHDL and Verilog .............................................................. 15
OVERVIEW OF FPGA DEVELOPMENT BOARD ................................................ 16
2.4.1
FPGA Programming Process ................................................................. 17
2.4.2
Review of Different FPGA Development Board ................................... 18
CHAPTER THREE ................................................................................................... 21
PROJECT MANAGEMENT ................................................................................... 21
3.1
PROJECT PLAN AND SCHEDULE ...................................................................... 21
3.2
GANTT CHART ............................................................................................... 24
CHAPTER FOUR ...................................................................................................... 25
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
HARDWARE AND SOFTWARE IMPLEMENTATION ...................................... 25
4.1
CLOCK SOURCE .............................................................................................. 25
4.2
DIGITAL-TO-ANALOG CONVERTER ................................................................ 26
4.2.1
SPI Communication ............................................................................... 27
4.2.2
Interface Signals..................................................................................... 30
4.2.3
SPI Communication Details ................................................................... 31
4.2.4
Communication Protocol ....................................................................... 32
4.3
SLIDING SWITCH TO SELECT DIFFERENT OUTPUT WAVEFORM ...................... 34
4.4
ROTARY PUSH-BUTTON SWITCH TO SELECT DIFFERENT OUTPUT
FREQUENCIES ............................................................................................................ 35
4.4.1
Rotary Encoder Design .......................................................................... 35
4.4.2
Rotary Signals Design............................................................................ 36
4.4.3
Discrete LEDs Design............................................................................ 40
4.5
SIGNAL GENERATOR WORK FLOW ................................................................. 41
4.5.1
VHDL Implementation of a Signal Generator ....................................... 41
4.5.2
VHDL Implementation of the Waveform .............................................. 43
4.5.2
VHDL Implementation of the Rotary and Left Right LEDs ................. 45
CHAPTER FIVE ....................................................................................................... 46
TIMING SIMULATION .......................................................................................... 46
5.1
TIMING SIMULATION ON THE SIGNAL GENERATOR ........................................ 46
5.2
TIMING SIMULATION ON THE OUTPUT WAVEFORM - SQUARE WAVE............. 46
5.3
TIMING ANALYSIS OF ROTARY AND LEFT RIGHT LEDS ................................. 47
CHAPTER SIX .......................................................................................................... 48
TESTING AND VERIFICATION ........................................................................... 48
6.1
OUTPUT WAVEFORM - SINE WAVE ............................................................... 48
6.2
OUTPUT WAVEFORM - SQUARE WAVE .......................................................... 51
6.3
OUTPUT WAVEFORM - TRIANGULAR WAVE .................................................. 54
CHAPTER SEVEN .................................................................................................... 58
CONCLUSION AND RECOMMENDATION ....................................................... 58
7.1
CONCLUSION .................................................................................................. 58
7.2
RECOMMENDATION FOR FUTURE WORK ........................................................ 58
CHAPTER EIGHT .................................................................................................... 61
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
REFLECTION ......................................................................................................... 61
8.1
HARDWARE SKILL .......................................................................................... 61
8.2
SOFTWARE SKILL ........................................................................................... 61
8.3
PROJECT MANAGEMENT................................................................................. 62
8.4
PROBLEMS ENCOUNTERED ............................................................................. 62
REFERENCES ........................................................................................................... 64
APPENDICES ............................................................................................................ 66
APPENDIX A: FPGA STARTER KIT COMPARISON ...................................... 66
APPENDIX B: VHDL SOURCE CODE – TOP LEVEL ...................................... 67
APPENDIX C: VHDL SOURCE CODE – SINE WAVE ..................................... 71
APPENDIX D: VHDL SOURCE CODE – SQUARE WAVE .............................. 74
APPENDIX E: VHDL SOURCE CODE – TRIANGULAR WAVE .................... 77
APPENDIX F: VHDL SOURCE CODE – LEFT RIGHT LEDS .......................... 80
GLOSSARY................................................................................................................ 83
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
LIST OF FIGURES
Figure 2.1
Frequency, Period and Amplitude of a Sine Waveform ........................ 11
Figure 2.2
Amplitude Modulation (AM) and Frequency Modulation (FM) ........... 12
Figure 2.3
Block Diagram of a Signal Generator .................................................... 12
Figure 2.4
Signal Generator Memory Allocations .................................................. 13
Figure 2.5
DAC Input and Output Signal................................................................ 14
Figure 2.6
Output Signal with Clocking ................................................................. 15
Figure 2.7
HDL Modelling Capability .................................................................... 16
Figure 2.8
Xilinx’s Spartan-3A FPGA Development Kit Board ............................ 17
Figure 2.9
FPGA Programming Process ................................................................. 18
Figure 4.1
Block Diagram of a Signal Generator .................................................... 25
Figure 4.2
CLK_50MHz ......................................................................................... 26
Figure 4.3
SMA-style Connector ............................................................................ 26
Figure 4.4
CLK_AUX ............................................................................................. 26
Figure 4.5
DAC Onboard ........................................................................................ 27
Figure 4.6
Block Diagram of LTC2624 Quad DAC ............................................... 27
Figure 4.7
Single SPI Slave Communications ........................................................ 28
Figure 4.8
Multiple SPI Slave Communications ..................................................... 29
Figure 4.9
Digital to Analog Connections Schematic ............................................. 29
Figure 4.10
Simple Transfers of Data.................................................................... 30
Figure 4.11
SPI Communication Waveforms ........................................................ 31
Figure 4.12
32 Bits Communications Protocol ..................................................... 32
Figure 4.13
24 Bits Communications Protocol ..................................................... 33
Figure 4.14
Slide Switches .................................................................................... 34
Figure 4.15
Rotary Push-Button Switch ................................................................ 35
Figure 4.16
Push-Button Switch ............................................................................ 35
Figure 4.17
Rotary Shaft Encoder Circuitry .......................................................... 36
Figure 4.18
Signals from Rotary Encoder ............................................................. 37
Figure 4.19
Chatter signal...................................................................................... 37
Figure 4.20
Misinterpreted Chatter Signals ........................................................... 37
Figure 4.21
Signals of Designed Filter .................................................................. 39
Figure 4.22
Events and Direction Signals ............................................................. 39
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
Figure 4.23
Discrete LEDs .................................................................................... 40
Figure 4.24
LED Design ........................................................................................ 40
Figure 4.25
Signal Generator Flow Chart.............................................................. 42
Figure 4.26
Output Waveform Flow Chart............................................................ 44
Figure 4.27
Flip-flops design ................................................................................. 45
Figure 5.1
Simulation Result on the Signal Generator ............................................ 46
Figure 5.2
Simulation Result on the Output Waveform – Square Wave ................ 47
Figure 5.3
Simulation Result on the Rotary and Left Right LEDs ......................... 47
Figure 6.1
1 Hz Sine Wave with X, 200 ms/div and Y, 2 V/div ............................. 48
Figure 6.2
10 Hz Sine Wave with X, 50 ms/div and Y, 2 V/div ............................. 49
Figure 6.3
100 Hz Sine Wave with X, 5 ms/div and Y, 2 V/div ............................. 49
Figure 6.4
1 kHz Sine Wave with X, 500 us/div and Y, 2 V/div ............................ 50
Figure 6.5
10 kHz Sine Wave with X, 50 us/div and Y, 2 V/div ............................ 50
Figure 6.6
100 kHz Sine Wave with X, 5 us/div and Y, 2 V/div ............................ 51
Figure 6.7
1 Hz Square Wave with X, 200 ms/div and Y, 2 V/div ......................... 52
Figure 6.8
10 Hz Square Wave with X, 50 ms/div and Y, 2 V/div ......................... 52
Figure 6.9
100 Hz Square Wave with X, 5 ms/div and Y, 2 V/div ......................... 53
Figure 6.10
1 kHz Square Wave with X, 500 us/div and Y, 2 V/div .................... 53
Figure 6.11
10 kHz Square Wave with X, 50 us/div and Y, 2 V/div .................... 54
Figure 6.12
1 Hz Triangular Wave with X, 200 ms/div and Y, 2 V/div ............... 55
Figue 6.13
10 Hz Triangular Wave with X, 50 ms/div and Y, 2 V/div ................... 55
Figue 6.14
100 Hz Triangular Wave with X, 50 ms/div and Y, 2 V/div ................. 56
Figue 6.15
1 kHz Triangular Wave with X, 500 us/div and Y, 2 V/div .................. 56
Figure 6.16
10 kHz Triangular Wave with inputX, 50 us/div and Y, 2 V/div ...... 57
Figue 6.17
10 kHz Triangular Wave with X, 50 us/div and Y, 2 V/div .................. 57
Figure 7.1
Un-interpolated Signal ........................................................................... 59
Figure 7.2
Interpolated Signal ................................................................................. 59
Figure 7.3
Character LCD Interface ........................................................................ 60
Figure 7.4
LCD Screen ............................................................................................ 60
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
LIST OF TABLES
Table 2.1
FPGA Starter Kit.................................................................................... 19
Table 3.1
Project Plan ............................................................................................ 23
Table 3.2
Gantt Chart ............................................................................................. 24
Table 4.1
DAC Interface Signals ........................................................................... 30
Table 4.2
Command and Address Assignment ...................................................... 34
Table 4.3
XNOR Truth Table ................................................................................ 38
Table 4.4
XOR Truth Table ................................................................................... 38
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
CHAPTER ONE
INTRODUCTION
1.1
Background
Signal Generator is a tool that can produce various patterns of waveforms at a variety
of frequencies and amplitudes. Basically, a signal generator is used to generate signal
with precise controlled frequency and amplitude characteristics to mimic the input
signal of the circuit being tested. It is generally used in designing, testing and
troubleshooting electronic devices. Signal generators generally fall into one of the two
categories: function generators and arbitrary waveform generators.
Function generators are the simpler of the two types. They produce simple repetitive
signals in waveforms such a square waves, sine waves and triangular waves.
Arbitrary waveform generators are more complicated. Other than the ability to
generate the standard waveforms, it also can produce waveforms such as sin(x)/x [4],
exponential, cardiac, etc. A combination of signals is also possible and it operates at
clock rate of a few GHz which is much higher than the function generators.
Field-Programmable Gate Array (FPGA) provides an attractive platform for these
signal generators in-terms of performance, power consumption and flexibility in
configuration.
FPGA is a semiconductor device that can be configured by the customer or designer
after manufacturing. FPGAs are programmed using a logic circuit diagram or a source
code in a Hardware Description Language (HDL) to specify how the chip will work.
The most common HDL used to program FPGA is Very high speed integrated circuit
Hardware Description Language (VHDL) and Verilog.
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DESIGN A SIGNAL GENERATOR USING FPGA
1.2
WONG PENG YEW
(W0706833)
Objective
The main objective is to design a signal generator using Field-Programmable Gate
Array (FPGA) to generate a few types of waveforms - square waves, triangular waves
and sine waves are the main objective of this project.
As technologies are fast changing, a modifiable tool is essential and comparing to
those high-priced signal generation instruments, an FPGA-based signal generator fits
the bill. By modifying the soft coded VHDL or Verilog, we can develop a signal
generator catering to our needs.
Through research, design, programming and analysis, the goal of this project could be
attainable.
1.3
Scope
The design of signal generator requires the following approach to obtain the objective
of this project

Research and study on signal generator and how signals are generated

Research and study on the FPGA

Research on the different types of FPGA development board which is available
in the market

Study and choose one of the two types of application language suitable for
FPGA: VHDL(chosen) and Verilog

Implement algorithms and functions on the FPGA development board with
VHDL coding

Stimulation and evaluation on the output
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
CHAPTER TWO
REVIEW OF THEORY AND PREVIOUS WORK DONE
2.1
Overview of Signal generator
Signal generators deliver a sinusoidal output of accurately calibrated frequency. The
output signals are usually frequency or amplitude modulated. Signal generators are
typically used to measure the output in simple electronic repair and design, therefore
output accuracy is critical. Accuracy is the way in which the output level of a signal
generator is controlled. When generating the signal, an attenuator is used to maintain
this output. The stability and intensity of the signal is maintained and made stronger
by the inbuilt amplifier [2].
The signal generator may use Digital Signal Processing (DSP) to synthesize
waveforms, followed by a Digital to Analog Converter to produce analog output [3].
The signal generator will operate in the audio frequency range, ranging from 20 Hz to
20 KHz or quantity of cycles per second. The frequency and the amplitude are
adjustable and must be able to maintain constancy over the tuning range.
Figure 2.1
Frequency, Period and Amplitude of a Sine Waveform
If the generator needs to operate above the audio frequency range, it will often include
modulation function such as Amplitude Modulation (AM) and Frequency Modulation
(FM). AM is the variation of the signal’s amplitude where its frequency remains
constant and FM is the variation of the signal’s frequency where its amplitude remain
constant. Figure 2.2 shows an example of AM and FM signals. Other than these
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
common modulations, today’s signal generators include Phase Modulation (PM) and
Quadrature Amplitude Modulation (QAM).
Figure 2.2
2.2
Amplitude Modulation (AM) and Frequency Modulation (FM)
Signal Generator Block Diagram
Figure 2.3 shows the block diagram of a signal generator. The Waveforms Generator
Engine will output waveform from the waveforms sequence stored in Onboard
Memory. This output waveform will go through Digital Gain for amplification or
attenuation before heading for the Digital Filter to be interpolated. The interpolated
waveform will go through Digital-to-Analog Converter (DAC) to output analog
waveform triggered by the Clock. This analog waveform will lastly go through the
Analog Filter to have most or all of its unwanted signals removed before generating
the ideal output.
Onboard
Memory
Waveform
Generation Engine
Digital
Gain
Analog
Filter
Output
Figure 2.3
Digital Filter
(Interpolation)
DAC
Block Diagram of a Signal Generator
12
Clock
DESIGN A SIGNAL GENERATOR USING FPGA
2.2.1
WONG PENG YEW
(W0706833)
Memory Allocation
Figure 2.4 illustrates on the memory allocation for waveforms and sequence
instructions stored on the Onboard Memory device of a signal generator [5]. The
signal generator requires limited memory to store a single period of the waveforms
since its outputs are repetitive and with a standard library it is able to generate
periodic waveforms. Loading of multiple waveforms and sequence instructions are
possible but more complicated ones may occupy a significant block of memory.
Figure 2.4
Signal Generator Memory Allocations
2.2.2 Waveform Generator Engine
Waveform Generator Engine is a program to link and loop waveform segments.
Linking and looping can be divided into sequence generation mode and script
generation mode. Comparing sequence and script generation mode, the latter is more
advance but not all signal generators possesses. Other than outputting a predetermined
series of waveforms with the sequence instructions stored in the onboard memory,
script generation mode can have a waveform sequences that depends on an external or
internal trigger to generate an output signal.
2.2.3 Digital Gain
The Amplifier and Attenuator are to maximize the digital signal’s amplitude accuracy.
When amplified signals are output as analog signal after DAC, users are able to adjust
the amplitude of the signal without the need to reload a different waveform. DAC is to
convert digital waveforms in the memory to analog waveforms.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
2.2.4 Digital Filter (Interpolation)
Both the digital and analog Filter is used to provide the best approximation of an ideal
analog signal. During digital to analog conversion, digital filter are used to interpolate
the signals to increase the effective sampling rate. But the digital filter might not be
able to remove unwanted signals completely. The analog filter is able to attenuate
these DAC signals and remove the unwanted signals through applying a low pass
filter, high pass filter or a band pass filter. Figure 2.5 shows the input (raw signal) and
output signal (filtered signal that had gone through interpolation, conversion and
filtering).
Figure 2.5
DAC Input and Output Signal
2.2.5 Digital-to-Analog Converter
Clocking of DAC is critical as it will affect the frequency accuracy and its effect is
measurable. Referring to Figure 2.6, whenever the clock clocks on the rising edge, the
DAC will generate the output signal with the sampled points of the single period
waveforms sequence stored in the memory.
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DESIGN A SIGNAL GENERATOR USING FPGA
Figure 2.6
2.3
WONG PENG YEW
(W0706833)
Output Signal with Clocking
Overview of Hardware Description Language (HDL)
There are now two standard industrial HDL, Very high speed integrated circuit
Hardware Description Language (VHDL) and Verilog. With the complexity of FPGA
design, many specialist design consultant has his or her own specific tools and
libraries written in VHDL or Verilog. As a result, designers of FPGA had vendors of
VHDL, Verilog and Electronic Design Automation (EDA) provide tool that provides
an environment suitable for both HDL to be used in unison.
The choice of which to use is not therefore based solely on technical capability but on:

personal preferences

EDA tool availability

commercial, business and marketing issues
2.3.1
Review on VHDL and Verilog
VHDL has two advantages, firstly it allows system’s behaviour to be modelled and
simulated before logic synthesis tools were used. Secondly, it allows switching
between different modelling of the system.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
Verilog allows switch-level modelling which are useful for exploring new circuits.
And it ensures that all signals are initialized to “unknown” so that designers will
produce necessary logic to initialize their design.
Figure 2.7
HDL Modelling Capability
Figure 2.7 show the modelling capabilities of VHDL and Verilog cover a slightly
different spectrum across the level of behaviour abstraction. VHDL contains more
features that allow it to model up to the highest level in design but not to the lowest
level whereas Verilog can model down to the lowest level but not the highest. The
main difference between the two is that Verilog is based on C and VHDL is based on
ADA.
2.4
Overview of FPGA Development Board
A Field-Programmable Gate Array (FPGA) is a semiconductor device that can be
configured by the customer or designer after manufacturing – hence the name “FieldProgrammable” [7]. The first FPGA industry sprouted from Programmable Read Only
Memory (PROM) and Programmable Logic Devices (PLDs). Both PROM and PLDs
are field programmable, however programmable logic are hard-wired between logic
gates. Due to the advancement of technology, FPGA now has programmable gates
and programmable interconnect between gates.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
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Over the years, there is a trend to form a complete “system on a programmable chip”
by combining the logic blocks and interconnects of traditional FPGA with embedded
microprocessors and related peripherals. Xilinx’s Spartan-3A is one of these hybrid
technologies, which is shown in Figure 2.8. It features some of the I/O ports, switches
and components integrated on it.
Figure 2.8
2.4.1
Xilinx’s Spartan-3A FPGA Development Kit Board
FPGA Programming Process
Figure 2.9 illustrates the process of FPGA programming. When the system compiled a
HDL code written at the design entry level, it output a Register Transfer Level (RTL)
netlist. When the input HDL is successfully synthesize at the synthesizer, it produces
a HDL of this gate-level code that can be mapped into the FPGA hardware.
Compiling and simulation of this gate-level HDL can be done at the actual level to
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DESIGN A SIGNAL GENERATOR USING FPGA
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avoid any code written at RTL disappeared at the final gate level implementation.
Thus, debugging of error can be done at actual level.
Figure 2.9
2.4.2
FPGA Programming Process
Review of Different FPGA Development Board
Xilinx and Altera are the current FPGA market leaders but the more prominent one
would be Xilinx since it is controlling over 50% of the market according to some
reports.
Xilinx has two FPGA development boards which met the minimum requirement for
the design of a signal generator, Spartan-3A and Spartan-3AN. In terms of
specification, there is no difference between the two (Appendix A). But Spartan-3N
has one specific feature which Spartan-3A did not. It is the ‘Non-volatile
configuration from internal SPI Flash’ [1] meaning to say that the Flash memory is
able to stored information even when not powered.
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WONG PENG YEW
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DESIGN A SIGNAL GENERATOR USING FPGA
Then comparing Xilinx’s Spartan-3A and 3AN with its competitive development
board, Altera’s Cyclon II and III, Alteras’ is not as comprehensive as Xilinxs’
(Appendix A) in terms of specification. Cyclon II need an external clock input and
Cyclon III has no analog interface which is critical in my design and Xilinx’s Spartan3A and 3AN has both integrated onboard.
Xilinx’s Spartan-
Xilinx’s Spartan-
Altera’s
Altera’s
3A
3AN
Cyclon II
Cyclon III
700K
700K
-
-
Slices
5888
5888
-
-
Logic Cells
13248
13248
18752 Logic
18752 Logic
Elements
Elements
11776
11776
-
-
50MHz Crystal
50MHz Crystal
Oscillator
Oscillator
(Open slot for user-
(Open slot for user-
installed clock)
installed clock)
4Mbit Platform Flash
4Mbit Platform Flash
PROM
PROM
8Mbyte
SDRAM
32Mx16 DDR2
32Mx16 DDR2
SDRAM
1Mbyte
SDRAM
SDRAM
512Kbyte
synchronous
32Mbit pareallel Flash
32Mbit pareallel Flash
SRAM
SRAM
2-16Mbit SPI Flash
2-16Mbit SPI Flash
4Mbyte Flash
16Mbytes
Devices
Devices
4-channel D/A
4-channel D/A
converter
converter
24-bit
2-channel A/D
2-channel A/D
coder/decoder(
converter
converter
CODEC)
Signal Amplifier
Signal Amplifier
Start Kit
System
Gates
CLB FlipFlops
Clock
Memory
Analog
Interface
Table 2.1
external clock
input(SAM
connector)
50MHz onboard oscillator
256Mbit DDR
Flash
-
FPGA Starter Kit
Comparing the specification of Altera’s and Xilinx’s Development Kit, the latter
shows that it more compatible. And comparing Xilinx’s Spartan 3N and Spartan 3A
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DESIGN A SIGNAL GENERATOR USING FPGA
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development kit, Spartan 3A was able to meet the design’s minimum requirement and
it is more affordable compared to the other.
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DESIGN A SIGNAL GENERATOR USING FPGA
WONG PENG YEW
(W0706833)
CHAPTER THREE
PROJECT MANAGEMENT
The project was not acted according to the planned schedule. The actual dates were
behind schedule due to multiple assignments and exams from my other modules,
work commitments, and personal issues. But the main contributing factor was during
the design of the signal generator as I have no knowledge in FPGA and HDL. From
my busy schedule, I had spared two days to attend a workshop recommended by my
project supervisor which was provided by Xilinx. The workshop provides
fundamental knowledge on VHDL programming, basic operation of the FPGA
development kit and basic analytical skills in FPGA design. VHDL programming
book needs to be read, signal generator related program and research papers needs to
be read up for reference whether or not problem arises during the design of signal
generator. Project plan and schedule will be presented and delays in the schedules will
be discussed.
3.1
Project Plan and Schedule
Task 1 – Project Proposal Writing and Submission was able to complete on time.
Task 2 – Research for a Suitable FPGA Development Board for Designing a Signal
Generator was able to meet schedule. Xilinx’s Spartan 3A was selected after
studies were done on a few similar FPGA Development Boards. At the same
time, research was done on simple FPGA based signal generators.
Improvement on the board was not needed as the board itself is already
sufficient.
Task 3 – Research and writes a suitable HDL took longer than expected, this is due to
the lack of basic knowledge on HDL. Although simple program were used
during the attended workshop, it was still difficult to digest. Finally after a
long research, VHDL (advantage discussed in chapter 2.3.2) was selected as
the preferred HDL. First, the square wave was developed and followed by
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WONG PENG YEW
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DESIGN A SIGNAL GENERATOR USING FPGA
other waveforms. Then different output frequencies are implemented using
LEDs as indication.
Task 4 – Evaluation of Design and Model Testing was delay due to the prolonged
schedule of Task 3.2. This had also made the tasks that follow overlaps and
many tasks have to be run concurrently. Finalize program and testing and
simulation has to be performed concurrently. Documentation on test results
and simulation results has to run concurrently with task 5.
Task 5 – Preparations for final report took up a lot of time since junks of materials
need to be organized and documented. And lastly, final poster and oral
presentations took more than 2 weeks to be prepared.
Date
S/No.
Date Start
Finish
Days
Project Proposal Writing and Submission
5-Aug-09
30-Aug-09
26
1.1
Meet up with supervisor
5-Aug-09
5-Aug-09
1
1.2
Project research, proposal write up and review
6-Aug-09
22-Aug-09
17
1.3
Supervisor review proposal
23-Aug-09
23-Aug-09
1
1.4
Finalize project proposal (submission on 31st Aug)
24-Aug-09
30-Aug-09
7
31-Aug-09
5-Oct-09
36
31-Aug-09
6-Sep-09
7
7-Sep-09
7-Sep-09
1
8-Sep-09
28-Sep-09
21
design
29-Sep-09
5-Oct-09
7
Research and Writes a Suitable HDL
6-Oct-09
8-Feb-10
126
1
Task
Research for a Suitable FPGA Development Board
2
for Designing Signal Generator
Compare different readymade FPGA development
2.1
board
2.2
Select a suitable FPGA development board
Detail study on the selected FPGA development board
2.3
(components and functionality) and its limitation.
Possibility for any improvement on the board to suit
2.4
3
Research on VHDL and Verilog - study and write
3.1
simple code to simulate each HDL
6-Oct-09
2-Nov-09
28
3.2
Write program for signal generator with preferred HDL
3-Nov-09
25-Jan-10
84
3.3
Finalize program for simulation
26-Jan-10
8-Feb-10
14
Evaluation of Design and Model Testing
25-Jan-10
14-Mar-10
49
4.1
Finalize prototype (model and specification)
25-Jan-10
7-Feb-10
14
4.2
Testing and simulation
8-Feb-10
28-Feb-10
21
4.3
Documentations on test and simulation results
1-Mar-10
14-Mar-10
14
4
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Report Writing and Submission
8-Mar-10
4-Jun-10
89
5.1
Consolidate document and data
8-Mar-10
14-Mar-10
7
5.2
Report writing and Poster Preparations
15-Mar-10
9-May-10
56
10-May-10
16-May-10
7
17-May-10
4-Jun-10
18
5
Final check on report and poster (submission on 17th
5.3
May)
Final Poster and Presentation Preparation (Presentation
5.4
on 5th Jun)
Table 3.1
Project Plan
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3.2
Gantt Chart
Table 3.2
Gantt Chart
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CHAPTER FOUR
HARDWARE AND SOFTWARE IMPLEMENTATION
Figure 4.1 shows the block diagram of the signal generator. With input from the clock
and switches (frequencies selection and waveform selection), FPGA will process the
data and transfer to Digital-to-Analog Converter every micro second. This data will be
output to an Oscilloscope.
50MHz
OSCILLATOR
FREQUENCIES
SWITCHES
FPGA
WAVEFORM
SWITCHES
D/A
CONVERTER
OSCILLOSCOPE
Figure 4.1
4.1
Block Diagram of a Signal Generator
Clock Source
The FPGA Starter Kit supports three primary clock input sources. First, the kit
includes an on-board 50 MHz clock oscillator. Second, clock signals and other highspeed signals can be generated from the FPGA through a SMA-style connector or
clocks can be supplied off-board via the SMA-style connector. Third, a 133MHz
clock oscillator is installed in the CLK_AUX socket with an option to substitute a
separate eight-pin DIP-style clock oscillator in the socket provided. All the mention
three inputs are shown in figure 4.2, 4.3 and 4.4 respectively.
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DESIGN A SIGNAL GENERATOR USING FPGA
Figure 4.2
Figure 4.3
WONG PENG YEW
(W0706833)
CLK_50MHz
SMA-style Connector
Figure 4.4
CLK_AUX
As the 50 MHz clock oscillator is sufficient, CLK_SMA and CLK_AUX will not be
considered. The 50 MHz oscillator is equivalent to a 20ns period with a 40% to 60%
output duty cycle [1]. The oscillator is accurate to +/-2500 Hz or +/-50 ppm [1].
4.2
Digital-to-Analog Converter
The Spartan 3A FPGA Starter Kit Board includes an SPI-compatible, four-channel,
serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology
LTC2624 quad DAC with 12-bit unsigned resolution [1]. As shown in figure 4.5, the
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DESIGN A SIGNAL GENERATOR USING FPGA
four outputs from the DAC appear on the J21 header which uses the Digilent six-pin
Peripheral Module format.
Four DAC Output:
Linear Tech
LTC2624 Quad DAC
DAC_OUTA
DAC_OUTB
DAC_OUTC
DAC_OUTD
SPI_MOSI: (AB14)
SPI_SCK: (AA20)
DAC_CS: (W7)
DAC_CLR: (AB13)
DAC_OUT: (V7)
6-pin DAC Header (J21)
Figure 4.5
DAC Onboard
GND
1
VCC
REF LO
REF D
DAC D
DAC
REGISTER
INPUT
REGISTER
VOUT D
14
13
DAC C
DAC
REGISTER
INPUT
REGISTER
REF B
6
__
CS/LD
INPUT
REGISTER
DAC
REGISTER
DAC B
5
15
VOUT C
VOUT A
4
VOUT B
INPUT
REGISTER
3
DAC
REGISTER
REF A
DAC A
2
16
REF C
12
____
CLR
11
CONTROL
DECODE
LOGIC
7
SDO
10
SDI
SCK
32-BIT SHIFT REGISTER
8
9
Figure 4.6
Block Diagram of LTC2624 Quad DAC
4.2.1 SPI Communication
Serial Peripheral Interface (SPI) is a simple interface that allows one chip to
communicate with one or more other chip. FPGA uses SPI to communicate digital
values to each of the four DAC channels. The SPI bus is a full duplex, synchronous,
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character-oriented channel employing a simple four-wire interface [1] and most
importantly, there is only one master and can have one or more slaves.
The master is always the one who initiates communication. When in communication,
a clock is generated by the master and two bits of data (one bit in each direction since
SPI is synchronous and full duplex) are transmitted each time the clock toggles. For
data to fit on a single wire, data are to be serialized before being transmitted. And
there are two wires for transmitting the data, one for each direction. The master and
the slave know beforehand the details of the communication such as bit order, length
of data words exchanged, etc.
Referring to figure 4.7, the connections are called SCK, MOSI, MISO and SSEL. The
SPI master (FPGA in this case) drives the bus clock signal (SPI_SCK) and transmit
serial data (SPI_MOSI) to the selected SPI slave (DAC in this case) [1]. At the same
time, the SPI slave feedback serial data (SPI_MISO) to the SPI master. Slave select
(SSEL) is an output from the SPI master to SPI slave to indicate that communication
is starting (SSEL pulled to active low). In the case of multiple SPI slave, only one
SSEL line is activated at a time and slaves that are not selected must not drive the
SPI_MISO line.
SPI
Master
Figure 4.7
SCI
MOSI
MISO
SSEL
SPI
Slave
Single SPI Slave Communications
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SPI
Slave
SPI
Master
SCI
MOSI
MISO
SSEL
SPI
Slave
SPI
Slave
Figure 4.8
Figure 4.9
Multiple SPI Slave Communications
Digital to Analog Connections Schematic
Figure 4.10 shows a simple transfer of data between the master and a slave. Looking
at the figure, assuming that 8-bits of data are to be transmitted starting with the Most
Significant Bit (MSB). The master pulls the SSEL to Low to indicate that
communication is starting. The master toggles the clock eight times and send sends
eight data bits through MOSI and all data bits are received by MISO at the same time.
The master then pulls SSEL High to indicate that the transfer is over. [11]
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Figure 4.10
Simple Transfers of Data
4.2.2 Interface Signals
The table 4.1 below lists the interface between the FPGA and the DAC. The
SPI_MOSI, DAC_OUT, and SPI_SCK signals are shared with other devices on the
SPI bus. The DAC_CS signal is the active-Low slave select input to the DAC. The
DAC_CLR signal is the active-Low, asynchronous reset input to the DAC.
Signal
FPGA Pin
Direction
SPI_MOSI
AB14
FPGA to DAC
Description
Serial data: Master Output, Slave
Input
DAC_CS
W7
FPGA to DAC
Active-Low chip select. Digital-toanalog conversion starts when this
signal returns High.
SPI_SCK
AA20
FPGA to DAC
Clock
DAC_CLR
AB13
FPGA to DAC
Asynchronous, active-Low reset
input
DAC_OUT
V7
DAC to FPGA
Table 4.1
Serial Data from the DAC
DAC Interface Signals
The serial data output from the DAC is primarily used to cascade multiple DACs.
This signal can be ignored in most application although it does not demonstrate fullduplex communication over the SPI bus.
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4.2.3 SPI Communication Details
A detailed example of the SPI bus timing is shown in Figure 4.11. Each bit is
transmitted or received relative to the SPI_SCK clock signal. The bus is fully static
and supports clock rates up to the maximum of 50 MHz [1].
The FPGA transmit data on the SPI_MOSI signal starting with the MSB when
DAC_CS slave select is pull Low. During the rising edge of the SPI_SCK, data on
SPI_MOSI are captured by the LTC2624 DAC. The data must be valid for at least 4
ns relative to the rising clock edge.
During the falling edge of SPI_SCK, data captured by LTC2624 DAC are transmitted
through DAC_OUT signal. During the next rising edge of SPI_SCK, FPGA will
capture this data. To make sure bit 31 will not be missed, during the first rising edge
of SPI_SCK after DAC_CS goes Low, first DAC_OUT value must be captured by
FPGA.
When all the data bits are transmitted, DAC_CS will be pulled to High to indicate the
completed transaction between FPGA and SPI. Then only will the actual digital-toanalog conversion process takes place within the DAC.
Figure 4.11
SPI Communication Waveforms
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4.2.4 Communication Protocol
The DAC supports both 32-bit and 24-bit protocol. The 32-bit communication
protocol required to interface with the LTC2624 DAC is shown in figure 4.12
whereas the 24-bit communication is shown in figure 4.13.
Referring to figure 4.12, SPI interface is formed by a 32-bit shift register inside the
DAC. Each 32-bit command word would consist of a COMMAND followed by an
ADDRESS and then DATA. When a new command word enters the DAC, the
previous 32 bit command word is sent back to the master. This returned command
from the DAC can be ignored even though it can also be used to verify the accuracy
of the command which was sent earlier.
Figure 4.12
32 Bits Communications Protocol
The FPGA will send from the Most Significant Bit (MSB) to the Least Significant Bit
(LSB). The FPGA will first send out eight Don’t Care (dummy) bits followed by a 4bit COMMAND. The most commonly used command with the board is
COMMAND[3:0] = 0011 binary. This command will immediately updates the
selected DAC output with the specified data value. After sending the 4-bit
COMMAND, the FPGA will send a 4-bit ADDRESS to selects one or all of the DAC
output channels. The FPGA will then continue to send a 12-bit unsigned data value
which the DAC will convert to an analog value on the selected output(s). Lastly,
another four Don’t Care (dummy) bits will be sent forming the 32-bit command word.
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Figure 4.13
WONG PENG YEW
(W0706833)
24 Bits Communications Protocol
The difference between the 32-bit communication protocol and the 24-bit
communication protocol is the latter does not sent out eight Don’t Care (dummy) bits
at the beginning. After that, the sequence is the same. The 4-bit COMMAND is
loaded first followed by the 4-bit ADDRESS and lastly the 16-bit DATA including
the 4 dummy bits.
The COMMAND (C3-C0) and ADDRESS (A3-A0) assignments are shown in Table
4.2. The first four commands in the table consists of write and update operations.
Command ‘0000’ load the data word from the shift registers into the input register of
the selected DAC, n. Command ‘0001’ copies data word from the input register to the
DAC register. These data words which are copied into the DAC register becomes the
active 16, 14 or 12 bits input code which in turn is converted to an analog voltage at
the DAC output. The update operation also powers up the selected DAC if it had been
in power down mode. ADDRESS is the assignment of input register of the DAC.
COMMANDS
C3
C2
C1
C0
0
0
0
0
Write to Input Register n
0
0
0
1
Update (Power Up) DAC Register n
0
0
1
0
Write to Input Register n, Update (Power Up) All n
0
0
1
1
Write to and Update (Power Up) n
0
1
0
0
Power Down n
1
1
1
1
No Operation
ADDRESS
A3
A2
A1
A0
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0
0
0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
1
1
1
1
All DACs
Table 4.2
4.3
WONG PENG YEW
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Command and Address Assignment
Sliding Switch to Select Different Output Waveform
Slide switches on the development board are used to select desired output waveform
pattern being Square waves, Triangular Waves and Sine Waves. There are four slide
switches on Spartan 3A development board as show in figure 4.14. For this project,
only three of the switches are used being SW0, SW1, and SW2.
Figure 4.14
Slide Switches
When the switch is in High, ‘1’ or ON position (pushed up), it will connect the FPGA
pin to 3.3V, logic High. Similarly, when the switch is in OFF position (pushed down),
it connects the FPGA pin to ground, logic low. These switches typically exhibit about
2 ms of mechanical bounce as there is no de-bounced circuitry [1].
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4.4
WONG PENG YEW
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Rotary Push-Button Switch to Select Different Output Frequencies
The Rotary Push-Button Switch integrates two different functions. First, the switch
shaft rotates and output values whenever the shaft turns. Secondly, it acts as a pushbutton switch when the shaft is pressed. The Rotary Push-Button Switch in this
project is used to select different output frequencies ranging from 0.1 Hz to 100 KHz
when it rotates and is used to reset the signal when is pressed.
Figure 4.15
4.4.1
Rotary Push-Button Switch
Rotary Encoder Design
In figure 4.16, when the knob of the rotary push-button switch is pressed, it connects
the associated FPGA pin to 3.3V, thus logic high is generated. It uses an internal pulldown resistor within the FPGA pin to generate a logic low at all other times and in
this project, it is used to reset the output signal when the knob is pressed.
Figure 4.16
Push-Button Switch
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The Rotary push-button switch is also used to select different output frequencies of
0.1 Hz, 1 Hz, 10 Hz, 100 Hz, 1 KHz, 10 KHz and 100 KHz when the knob is turn
accordingly. Referring to Figure 4.17, the basic principles of the rotary encoder is like
a cam connected to a shaft which controls two push-buttons switches. Depending on
which way the shaft is rotated, one switch will open before the other. Similarly, as the
rotation continues, one switch will be closed before the other. Both switches will be
closed when the shaft is in a stationary position. [1]
Figure 4.17
4.4.2
Rotary Shaft Encoder Circuitry
Rotary Signals Design
To be able to provide logic signals to Spartan-3A device which can be work with, one
side of each switch is connected to ground such that the signal is always Low or ‘0’
when the switch contacts are closed. During rotation, the switch contacts will be open
therefore a PULL-UP resistor is required to raise the signal to High or ‘1’. Figure 4.18
show signals detected by Spartan-3A. Due to human input, irregularity of the pulses is
expected [13]. The red and green brackets indicate that the logic levels are consistent
with the switch positions displayed in the diagram.
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Figure 4.18
WONG PENG YEW
(W0706833)
Signals from Rotary Encoder
Another thing to be expected is ‘chatter’ signals as mechanical parts are prone to
bounce, especially switch contacts [13]. Figure 4.19 shows a signal where chatter was
observed. A High signal of approximately 2.5 ms was seen when the switch opened.
The signal then closed for 1 ms, opened for 1 ms then it closes momentarily before
finally settling and providing a steady High signal.
Figure 4.19
Chatter signal
The direction of rotation is determined by the actual High and Low signals of ‘A’ and
‘B’ without ‘chatter’ signals. The Right rotation is read when ‘A’ goes High and ‘B’
goes Low. Left rotation is read when ‘A’ goes Low and ‘B’ goes High. [1]
Figure 4.20 shows that when a single step is rotated, the ’chatter’ signal could be
interpreted as additional rotation in either direction.
Figure 4.20
Misinterpreted Chatter Signals
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In order to minimise the effect of a chatter signal, a design to filter the signal is
necessary. The design will only detect the first change of the signal and ignoring all
subsequent same signals until the other switch also changes state. Flip-flops are used
to provide the ‘memory’ for the above mention function. The signals of the designed
filter, rotary_q1 and rotary_q2 are show in figure 4.21.
rotary_q1 is set (High) when A is High and B is High, reset (Low) when A is Low and
B is Low. rotary_q1 behaves like a XNOR gate.
Input
Output
A
B
A XNOR B
0
0
1
0
1
0
1
0
0
1
1
1
Table 4.3
XNOR Truth Table
rotary_q2 is set (High) when A is Low and B is High, reset (Low) when A is High and
B is Low. rotary_q2 behaves like a XOR gate.
Input
Output
A
B
A XOR B
0
0
0
0
1
1
1
0
1
1
1
0
Table 4.4
XOR Truth Table
Both rotary_q1 and q2 will remember current state in all other cases. The bold lines
indicate signals that are being forced and the normal lines are indicating that the flip-
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flop memory is retaining the current state. The signals look clean and the direction is
still determinable although it has a slight difference in signal behaviour now.
Figure 4.21
Signals of Designed Filter
By comparing the output of the rotary filter with the original outputs, the direction can
be determined. Referring to figure 4.22, when rotary_q1 changes from Low to High,
rotary_q2 indicates the direction with state ‘0’ as turning right and ‘1’ as left.
Remember “The Right rotation is read when ‘A’ goes High and ‘B’ goes Low. Left
rotation is read when ‘A’ goes Low and ‘B’ goes High.” which was stated with figure
4.18. Therefore, rotary_q1 can be used to determined each event and rotary_q2 to
determine the direction. [13]
Figure 4.22
Events and Direction Signals
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4.4.3
WONG PENG YEW
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Discrete LEDs Design
Spartan-3A Starter Kit board has eight individual surface-mount LEDs labelled LED7
through LED0 located above the slide switches as shown in figure 4.23.
Figure 4.23
Discrete LEDs
Figure 4.24 shows an example of a simple 8-bit shift register which is control by the
rotary events. Each shift register bit is then optionally inverted (by pushing the rotary
press switch) on the way to the output pin which drives the corresponding LED. The
LED has a side connected to a pin on the device through a 390 Ohm resistor which
limits the current to approximately 3.5 mA.
Figure 4.24
LED Design
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Each click of the shaft will moves only one position of the illuminated LED. Even
when the rotary knob is turning really slowly or click ‘one position’ in an instant, it
will only moves the LED by one position and not several position with the single
clock cycle pulses.
In this project, the LED’s 8-bit shift register “00000001”, “00000010”, “00000100”,
“00001000”, “00010000”, “00100000” and “01000000” indicate the selection of the
output frequency of 0.1 Hz, 1 Hz, 10 Hz, 100 Hz,1 KHz, 10 KHz and 100 KHz
respectively. The maximum output frequency this signal generator can output is only
100 KHz, anything more would output distorted waveform. The last 8-bit shift
register “10000000” is assigned with 100 KHz too.
4.5
Signal Generator Work Flow
Putting Chapter 4.1 – Clock Source; 4.2 – Digital to Analog Converter; 4.3 –
Selecting Different Output Waveform; 4.4 – Selecting Different Output Frequencies
together, a Signal Generator’s Flow Chart and its subroutine flow chart can be formed.
Subroutine includes output waveform of Square Wave, Sine Wave, Triangular Wave
and a Rotary – Left Right LEDs Flow Chart.
4.5.1 VHDL Implementation of a Signal Generator
Referring to the Signal Generator’s Flow Chart in figure 4.25, ‘start’ cycle consists of
the selection of Sine Wave, Square Wave or Triangular Wave and the initialising of
the DAC SPI. ‘sendBit’ cycle is the transmission of the data when SPI_SCK is Low.
In ‘clockHigh’ cycle, FPGA captures the ‘sendBit’ data when SPI_SCK is High.
When ‘csHigh’ cycle is active, the actual digital-to-analog conversion process will
start within the DAC.
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start
SW (0) = 1
Y
DAC = Sine
N
SW (1) = 1
Y
DAC = Square
N
SW (2) = 1
Y
DAC = Triangular
N
DAC_CS = 0
SPI_SCK = 0
dacCounter = 23
N
Sine_output or Square_output
or Triangualr_output = 1
Y
sendBit
SPI_SCK = 0
SPI_MOSI = dacData(23)
dacData = dacData << 1;
clockHigh
SPI_SCK = 1
dacCounter = 0
Y
N
dacCounter = dacCounter -1
csHigh
DAC_CS = 1
Figure 4.25
Signal Generator Flow Chart
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4.5.2 VHDL Implementation of the Waveform
The generation of the Square Waveform, Sine Waveform and Triangular Waveform is
basically applying one mythology. The difference between the three is the value of the
‘ramData’ which is needed to form the shapes of the waveform. Therefore, only the
generation of one type of waveform would be discussed.
Referring to the flow chart in figure 4.26, the first cycle ‘Load Address1’ sets the
address for getting the first word from memory. The second and third cycle,
‘Address1 Wait1’ and ‘Address1 Wait2’ are wait cycles until word is loaded. Forth
cycle ‘Load Address2’ get the first word from memory and set the address for getting
the second word from memory. Fifth and sixth cycles are wait cycles too. Seventh
cycle ‘setOutput’ sets the output data. ‘delay’ cycle consists of 42 cycles of delay and
1 new output cycle.
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Load Address1
SineOutput = ‘0’
ramAddr = counter (47 to 44)
state = address1Wait1
Address1 Wait1
State = address1Wait2
Address1 Wait2
State = loadAddress2
Load Address2
Data1 = ramData & “00000”
ramAddr = counter (47 to 44) + 1
state = address2Wait1
Address2 Wait1
State = address2Wait2
Address2 Wait2
State = setOutput
setOutput
Sineoutput = data1
counter = counter + 1
delayCounter = 42
delay
delayCounter = delayCounter - 1
N
delayCounter = 0
Y
SinenewOutput = 1
Figure 4.26
Output Waveform Flow Chart
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4.5.2 VHDL Implementation of the Rotary and Left Right LEDs
As mention in Chapter 4.4 - Rotary Push-Button Switch to Select Different Output
Frequencies, the rotary signals to determine the rotation direction and events was
designed as flip-flops shown in figure 4.27 as it can provide the ’memory’ for this
function. The Low to High transition of ‘rotary-q1’ is used to form a synchronous
pulse and remember the rotated direction and this ‘flip-flops’ will be able to maintain
this synchronous design. ‘rotary_event’ which is stated in the code enables the shift
register to operate and ‘rotary_left’ is used to determined the direction.
Figure 4.27
Flip-flops design
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CHAPTER FIVE
TIMING SIMULATION
5.1
Timing Simulation on The Signal Generator
Comparing figure 5.1 (Timing Simulation of the Signal Generator) with figure 4.23
(Signal Generator flow chart) shows that both the flow coincides. Looking at DAC
start, FPGA will transmit the data when dac_cs is ‘Low’. LTC2624 DAC will
transmit data on the SPI_MOSI when SPI_SCK is ‘Low’. FPGA will capture these
data when SPI_SCK is ‘High’. DAC end happen when 24 bits of data are capture by
FPGA (rising edge of SPI_SCK) and causing dac_cs turns ‘High’
Figure 5.1
5.2
Simulation Result on the Signal Generator
Timing Simulation on the Output Waveform - Square Wave
Referring to figure 5.2, sw[1] is ‘High’ meaning to say that square wave output was
selected. 8’hE0 is the ‘High’ part of the square wave and the time taken was around 5
us. Combining the ‘High’ and ‘Low’ part of the waveform the period is 10 us and by
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calculation, the frequency is 100 kHz which is the output frequency selected for this
simulation.
Figure 5.2
5.3
Simulation Result on the Output Waveform – Square Wave
Timing Analysis of Rotary and Left Right LEDs
Figure 5.3 shows the timing analysis of rotary signals and left right LEDs. It shows
that the LEDs is working with the input signals.
Figure 5.3
Simulation Result on the Rotary and Left Right LEDs
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CHAPTER SIX
TESTING AND VERIFICATION
For all the three types of output waveforms, their frequencies are ranging from 0.1 Hz
to 100 kHz with Voltage in the vertical axis and Time Base in the horizontal axis.
6.1
Output Waveform - Sine Wave
Point A to B indicates a complete cycle of a 1 Hz Sine Waveform in figure 6.1. With
a 200 ms/div on the x axis, one cycle of a triangular waveform is seen to have a period
of 1 sec. Base on calculation with the formulae, Period = 1/Frequency, the results are
true. A few other different frequencies of Sine Waveform are shown below.
A
Figure 6.1
B
1 Hz Sine Wave with X, 200 ms/div and Y, 2 V/div
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A
Figure 6.2
B
10 Hz Sine Wave with X, 50 ms/div and Y, 2 V/div
A
Figure 6.3
WONG PENG YEW
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B
100 Hz Sine Wave with X, 5 ms/div and Y, 2 V/div
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DESIGN A SIGNAL GENERATOR USING FPGA
A
Figure 6.4
B
1 kHz Sine Wave with X, 500 us/div and Y, 2 V/div
A
Figure 6.5
WONG PENG YEW
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B
10 kHz Sine Wave with X, 50 us/div and Y, 2 V/div
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A
Figure 6.6
6.2
WONG PENG YEW
(W0706833)
B
100 kHz Sine Wave with X, 5 us/div and Y, 2 V/div
Output Waveform - Square Wave
Point A to B indicates a complete cycle of a 1 Hz Square Waveform in figure 6.7.
With a 200 ms/div on the x axis, one cycle of a triangular waveform is seen to have a
period of 1 sec. Base on calculation with the formulae, Period = 1/Frequency, the
results are true. A few other different frequencies of Square Waveform are shown
below.
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DESIGN A SIGNAL GENERATOR USING FPGA
A
Figure 6.7
1 Hz Square Wave with X, 200 ms/div and Y, 2 V/div
A
Figure 6.8
B
B
10 Hz Square Wave with X, 50 ms/div and Y, 2 V/div
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DESIGN A SIGNAL GENERATOR USING FPGA
A
Figure 6.9
B
100 Hz Square Wave with X, 5 ms/div and Y, 2 V/div
A
Figure 6.10
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B
1 kHz Square Wave with X, 500 us/div and Y, 2 V/div
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A
Figure 6.11
6.3
WONG PENG YEW
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B
10 kHz Square Wave with X, 50 us/div and Y, 2 V/div
Output Waveform - Triangular Wave
Point A to B indicates a complete cycle of a 1 Hz Triangular Waveform in figure 6.12.
With a 200 ms/div on the x axis, one cycle of a triangular waveform is seen to have a
period of 1 sec. Base on calculation with the formulae, Period = 1/Frequency, the
results are true. A few other different frequencies of Triangular Waveform are shown
below.
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A
Figure 6.12
B
1 Hz Triangular Wave with X, 200 ms/div and Y, 2 V/div
A
Figue 6.13
WONG PENG YEW
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B
10 Hz Triangular Wave with X, 50 ms/div and Y, 2 V/div
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A
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B
Figue 6.14
100 Hz Triangular Wave with X, 50 ms/div and Y, 2 V/div
Figue 6.15
1 kHz Triangular Wave with X, 500 us/div and Y, 2 V/div
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A
Figure 6.16
B
10 kHz Triangular Wave with inputX, 50 us/div and Y, 2 V/div
A
Figue 6.17
WONG PENG YEW
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B
10 kHz Triangular Wave with X, 50 us/div and Y, 2 V/div
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CHAPTER SEVEN
CONCLUSION AND RECOMMENDATION
7.1
Conclusion
The objective of this project was to design a FPGA based Signal Generator which is
able to output a few types of waveform. The objective was completed as planned in
Project Plan and Schedule. This FPGA based Signal Generator is able to generate
three type of waveforms being square, sine and triangular wave.
The Signal Generator was able to output desired waveform correctly but referring to
figure 6.2 and 6.13 for Sine and Triangular Waves respectively, the output was not so
ideal. Both Sine and Triangular Waveforms are jagged, meaning to say that the waves
outline look like steps instead of a smooth line. These waveforms can be improved
graphically by switching to high output frequency onboard and decreasing Timebase
to smaller units per second which is similar to figure 6.6.
Switches are used in conjunction with selectable parameters which allows the user to
select desired output waveform type and also selects the output frequencies of 0.1 Hz,
1 Hz, 10 Hz, 100 Hz, 1k Hz, 10k Hz or 100 kHz. The signal generator is only able to
generate waveform up to 100 kHz. Any waveform generated with frequency more
than 100 kHz will look the same.
7.2
Recommendation for Future Work
The Signal Generator is now generating Sine and Triangular waveform with stepping
outline. Improvement on the program can be done so as to output higher resolution
waveform. This signal generator is now generating waveforms with 16 samples. We
can get a better waveform outline by increasing the samples size from 16 to 32
samples. More and compact stepping could be seen on the waveforms with 32
samples but it would still not be a smooth waveform.
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Interpolation is a better function to apply rather than increasing the sample size.
Interpolation will get the first and second word, and then it will interpolate between
the two with lower bits of counter then set it as output. To put it simply, it is to
estimate the value between two values which has been tabulated. Figure 7.2 shows an
example of an interpolated signal.
Figure 7.1
Figure 7.2
Un-interpolated Signal
Interpolated Signal
Right now, the selection of frequency is indicated by the LEDs and the value of the
chosen frequency is displayed on the oscilloscope when output to it. These values
could actually be displayed on the onboard Character LCD Screen. The LCD is a
practical way to display a variety of information using standard ASCII and custom
characters. The FPGA controls the LCD via the eight-bit data interface as shown in
Figure 7.3.
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Figure 7.3
Character LCD Interface
Figure 7.4
LCD Screen
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WONG PENG YEW
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CHAPTER EIGHT
REFLECTION
8.1
Hardware Skill
This is my first encounter with a FPGA development board and every component
onboard was a new experience for me. Throughout this project I have gained basic
knowledge on some onboard components and have tried to implement them. SPI DAC
was one of the components. The FPGA uses a Serial Peripheral Interface (SPI) to
communicate digital values to each of the DAC output.
I have also learnt the mechanism operation of the rotary switch onboard. This rotary
switch was able to interact with the LEDs, indicating the frequencies used to generate
waveforms. Other than the rotary switch with the eight LEDs, another four sliding
switches are used to select the output frequency.
8.2
Software Skill
Very high speed integrated circuit Hardware Description Language (VHDL) was one
hardware programming language that I have learnt to do this project. VHDL is a
strongly typed language which means that an object must have a data typed and only
the defined values and operation can be applied to the object. Applying VHDL on
FPGA, not only memory bits but also logic gates can be controlled.
Xinlix ISE (Integrated Software Environment) Project Navigator was another
software application which I had learnt to use. ISE Project Navigator controls all
aspect of the development flow and is a graphical interfaced for users to access
software tools and relevant files associated with the project. VHDL code and
Testbench was written and tested with ISE Project Navigator.
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Project Management
Project management was critical for me due to my lack of knowledge on the project
requirements. Thus, I have to be very discipline in all areas to make up for the losses
in time during the early stages when I need to learn the required skills from scratch.
Time management plays an important role as it helps to plan and ensures that all tasks
are carried out. And this has benefited me at work or in school as it has well utilised
my time and built up my multitasking ability.
8.4
Problems Encountered
Many obstacles were encountered during the development of the project but most of
them were solved be it hardware or software. As I had zero knowledge on two critical
parameters, FPGA development board and its programming language VHDL, more
time and effort has to be spent to familiarise myself to the FPGA development board
and VHDL hence causing a delay in my schedule.
At the start of the development, creating a User Constraint File (UCF) was already a
problem. Through reading the user guide and the attended workshop, I was able to
define the needed UCF.
During the development, problems were encountered in DAC communication. I had
sought help from a senior with FPGA experience. We went through my written code
and found the flow of the shifting of registers was not right. He gave me pointers and
with his help I was able to have my DAC communication working.
I had problems again during the implementation of the rotary push-button switch. I
had sought help from Xilinx’s vendor and the senior. Both recommended me to use a
reference design for the rotary encoder interface which was written in PicoBlaze
assembly language (Xilinx specific 8 bit soft core processor). Since I have already
started my project with VHDL and did not have the luxury in time to implement the
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project in another programming language, I had to study the flow of the PicoBlaze’s
design and implement it in VHDL.
One more problem I encountered is the jagged outline of the output waveform. I had
tried to use interpolation in my design to overcome this problem but it did not turn out
well. The desired output was not achieved (ideal output was discussed in
Recommendation and Future Work). The failure might have happen during capturing
of the data and calculation in the source code.
Other than these major obstacles, minor ones are encountered too but were overcome
without much delay.
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REFERENCES
[1]
Spartan-3A/3AN FPGA Starter Kit Board User Guide (Online)
http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf
[2]
How Does a Signal Generator Work? (By an eHow Contributing Writer,
Online)
http://www.ehow.com/how-does_4970115_signal-generator-work.html
[3]
Signal Generator (Online Encyclopedia)
http://en.wikipedia.org/wiki/Signal_generator
[4]
Christopher Ziomek, Differences between Signal Generators, Function
Generators and Arbitrary Waveform Generators, Jun 22 2009 (Online)
http://blog.ztecinstruments.com/bid/22907/Differences-Between-SignalGenerators-Function-Generators-and-Arbitrary-Waveform-Generators
[5]
Signal Generator Architecture - Analog Output to Advanced Features
(National Instruments, Online)
http://zone.ni.com/devzone/cda/tut/p/id/5535
[6]
Douglas J. Smith, VHDL & Verilog Compared & Contrasted Plus Modeled
Example Written in VHDL, Verilog and C (Online)
http://www.angelfire.com/in/rajesh52/verilogvhdl.html
[7]
Field-programmable gate array (Online Encyclopedia)
http://en.wikipedia.org/wiki/Field-programmable_gate_array#cite_notehistory-2
[8]
Ed Klingman, FPGA programming step by step, April 2004 (Online)
http://www.embedded.com/columns/technicalinsights/18201956;jsessionid=Z
LEX2N1YKFEXBQE1GHOSKH4ATMY32JVN?pgno=2
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[9]
WONG PENG YEW
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Quadrature amplitude modulation (Online Encyclopedia)
http://en.wikipedia.org/wiki/Quadrature_amplitude_modulation
[10]
What is SPI? (Online)
http://www.fpga4fun.com/SPI1.html
[11]
DAC Data Sheet (Online)
http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005
,C1156,P2048,D2170
[12]
Spartan-3E FPGA Starter Kit Board User Guide (Online)
http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf
[13]
Rotary Encoder Interface for Spartan-3E Starter Kit (Online)
http://www.xilinx.com/products/boards/s3estarter/files/s3esk_rotary_encoder_
interface.pdf
[14]
Hardware Description Language (Online Encyclopedia)
http://en.wikipedia.org/wiki/Hardware_description_language (Online
Encyclopedia)
[15]
Verilog (Online Encyclopedia)
http://en.wikipedia.org/wiki/Verilog
[16]
VHDL (Online Encyclopedia)
http://en.wikipedia.org/wiki/VHDL
[17]
Generic DDS Generator
http://www.frank-buss.de/SignalGenerator/dds-example/index.html
[18]
Pong P. Chu, “FPGA prototyping by VHDL examples”, Wiley,2008
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APPENDICES
APPENDIX A:
FPGA STARTER KIT COMPARISON
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APPENDIX B:
WONG PENG YEW
(W0706833)
VHDL SOURCE CODE – TOP LEVEL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.ALL;
entity spartan3e_test is
port(
CLK_50MHZ
led
SPI_SCK
SPI_MOSI
DAC_CLR
DAC_CS
btn_north
btn_south
btn_west
btn_east
SW
ROT_A
ROT_B
ROT_CENTER
);
end entity spartan3e_test;
: in std_logic;
: out std_logic_vector(7 downto 0);
: out std_logic;
: out std_logic;
: out std_logic;
: out std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic_vector(3 downto 0);
: in std_logic;
: in std_logic;
: in std_logic
architecture rtl of spartan3e_test is
--state machie for the program control and DAC
type dacStateType is (
start,
sendBit,
clockHigh,
csHigh
);
signal dacState : dacStateType := start;
signal dacCounter : integer range 0 to 23;
signal dacData : std_logic_vector(23 downto 0);
--three types of wave
constant ddsAddressSize : natural := 4;
constant ddsWordSize : natural := 3;
constant ddsCounterSize : natural := 48;
constant outputSize : natural := 8;
signal Sineoutput,Squareoutput,Triangularoutput : unsigned(outputSize - 1 downto 0);
signal SinenewOutput,SquarenewOutput,TriangularnewOutput : std_logic := '0';
signal step
: unsigned(ddsCounterSize - 1 downto 0);
signal freq_selection : std_logic_vector(7 downto 0);
begin
SineWave: entity work.sine
generic map (
ddsAddressSize => ddsAddressSize,
ddsWordSize => ddsWordSize,
ddsCounterSize => ddsCounterSize,
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outputSize
)
=> outputSize
port map (
clock
reset
step
Sineoutput
SinenewOutput
);
=> CLK_50MHZ,
=> ROT_CENTER,
=> step,
=> Sineoutput,
=> SinenewOutput
Squarewave: entity work.square
generic map (
ddsAddressSize => ddsAddressSize,
ddsWordSize => ddsWordSize,
ddsCounterSize => ddsCounterSize,
outputSize => outputSize
)
port map (
clock
=> CLK_50MHZ,
reset
=> ROT_CENTER,
step
=> step,
Squareoutput
=> Squareoutput,
SquarenewOutput => SquarenewOutput
);
Triangularwave: entity work.Triangular
generic map
(
ddsAddressSize
=> ddsAddressSize,
ddsWordSize
=> ddsWordSize,
ddsCounterSize
=> ddsCounterSize,
outputSize
=> outputSize
)
port map
(
clock
=> CLK_50MHZ,
reset
=> ROT_CENTER,
step
=> step,
Triangularoutput
=> Triangularoutput,
TriangularnewOutput
=> TriangularnewOutput
);
rotary: entity work.left_right_leds
port map
(
clk
led
freq_selection
rotary_a
rotary_b
rotary_press
);
process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if ROT_CENTER='1' then
case freq_selection is
when "00000001"
0.1Hz
68
=> CLK_50MHZ,
=> led,
=> freq_selection,
=> ROT_A,
=> ROT_B,
=> ROT_CENTER
=> step <= x"000001AD7F2A"; --
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when "00000010"
=> step <= x"000010C6F7A0"; --
when "00000100"
=> step <= x"0000A7C5AC47"; --
when "00001000"
=> step <= x"00068DB8BAC7"; --
when "00010000"
=> step <= x"004189374BC6"; --
when "00100000"
=> step <= x"028F5C28F5C2"; --
when "01000000"
=> step <= x"199999999999"; --
when "10000000"
=> step <= x"199999999999"; --
when others
=> step <= x"000010C6F7A0"; --
1Hz
10Hz
100Hz
1000Hz
10KHz
100KHz
100KHz
1Hz
end case;
end if;
end if;
end process;
process(CLK_50MHZ, btn_south)
variable dacDataToSend : unsigned(11 downto 0);
begin
if rising_edge(CLK_50MHZ) then
if btn_south = '1' then
dacState <= start;
else
-- transfer data to DAC every us
case dacState is
when start =>
if
sw(0) = '1' then
dacDataToSend :=
unsigned(Sineoutput) & "0000";
elsif sw(1) = '1' then
dacDataToSend :=
unsigned(Squareoutput) & "0000";
elsif sw(2) = '1' then
dacDataToSend :=
unsigned(Triangularoutput) & "0000";
else
dacDataToSend := x"000";
end if;
-- initialize DAC SPI
dacData <= "0010" & "1111" &
std_logic_vector(dacDataToSend) & "0000";
if
SquarenewOutput OR TriangularnewOutput) = '1' then
DAC_CS <= '0';
SPI_SCK <= '0';
dacCounter <= 23;
(SinenewOutput OR
else
dacState <= sendBit;
dacState <= start;
end if;
when sendBit =>
SPI_SCK <= '0';
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SPI_MOSI <= dacData(23);
dacData <= dacData(22 downto 0) &
"0";
dacState <= clockHigh;
when clockHigh =>
SPI_SCK <= '1';
if dacCounter = 0 then
dacState <= csHigh;
else
dacCounter <=
dacCounter - 1;
dacState <= sendBit;
end if;
when csHigh =>
DAC_CS <= '1';
dacState <= start;
end case;
end if;
end if;
end process;
DAC_CLR <= '1';
end architecture rtl;
-- for output frequency f use this formula:
-- (2^(ddsCounterSize-ddsAddressSize) * f / 1MHz) * 16samples
-- e.g. for 1kHz ouput frequency:
-- (2^(48-4) * 1kHz / 1MHz) * 16samples = 281474976710 = 0x004189374BC7
-- some other values for testing:
-- 0.1Hz: 0x000001AD7F2A
-- 1Hz:
0x000010C6F7A0
-- 10Hz:
0x0000A7C5AC47
-- 100Hz:
-- 1kHz:
-- 10kHz:
-- 100kHz:
0x199999999999
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APPENDIX C:
WONG PENG YEW
(W0706833)
VHDL SOURCE CODE – SINE WAVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity sine is
generic (
ddsAddressSize : natural;
ddsWordSize : natural;
ddsCounterSize : natural;
outputSize : natural
);
port (
clock
: in std_logic;
reset
: in std_logic;
step
: in unsigned(ddsCounterSize - 1 downto 0);
Sineoutput
: out unsigned(outputSize - 1 downto 0);
SinenewOutput : out std_logic
);
end sine;
architecture rtl of sine is
signal counter : unsigned(ddsCounterSize downto 0);
type stateType is (
loadAddress1,
address1Wait1,
address1Wait2,
loadAddress2,
address2Wait1,
address2Wait2,
setOutput,
delay
);
signal state
: stateType := loadAddress1;
signal data1
: signed(outputSize downto 0);
signal delayCounter : natural range 0 to 43;
signal ramAddr
: unsigned(3 downto 0);
signal ramData
: unsigned(2 downto 0);
begin
process (clock,reset)
begin
if rising_edge(clock) then
-- simple sine wave simulator
case ramAddr is
when "0000" => ramData <= "100";
when "0001" => ramData <= "101";
when "0010" => ramData <= "110";
when "0011" => ramData <= "111";
when "0100" => ramData <= "111";
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when "0101" => ramData <= "111";
when "0110" => ramData <= "110";
when "0111" => ramData <= "101";
when "1000" => ramData <= "100";
when "1001" => ramData <= "010";
when "1010" => ramData <= "001";
when "1011" => ramData <= "000";
when "1100" => ramData <= "000";
when "1101" => ramData <= "000";
when "1110" => ramData <= "001";
when "1111" => ramData <= "010";
when others => ramData <= "000";
end case;
end if;
end process;
process(clock, reset)
variable delta : signed(outputSize downto 0);
variable signedFraction : signed(ddsCounterSize - ddsAddressSize downto 0);
variable interpolatedProduct : signed(ddsCounterSize - ddsAddressSize +
outputSize + 1 downto 0);
variable interpolated : signed(outputSize downto 0);
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
case state is
-- set address for getting the first word from memory
when loadAddress1 =>
SinenewOutput <= '0';
ramAddr <= counter(ddsCounterSize - 1
downto ddsCounterSize - ddsAddressSize);
state <= address1Wait1;
-- some wait cycles, until word is loaded
when address1Wait1 =>
state <= address1Wait2;
when address1Wait2 =>
state <= loadAddress2;
-- get first word from memory and set address for
getting next word
when loadAddress2 =>
data1 <= signed('0' & ramData) & to_signed(0,
outputSize - ddsWordSize);
ramAddr <= counter(ddsCounterSize - 1
downto ddsCounterSize - ddsAddressSize) + 1;
state <= address2Wait1;
-- some wait cycles, until word is loaded
when address2Wait1 =>
state <= address2Wait2;
when address2Wait2 =>
state <= setOutput;
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when setOutput =>
Sineoutput <= unsigned(data1(outputSize - 1
downto 0));
counter <= counter + step;
delayCounter <= 42;
state <= delay;
-- add some wait cycles for 1us
when delay =>
if delayCounter = 0 then
SinenewOutput <= '1';
state <= loadAddress1;
else
delayCounter <=
delayCounter - 1;
end if;
end case;
end if;
end process;
end architecture rtl;
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APPENDIX D:
WONG PENG YEW
(W0706833)
VHDL SOURCE CODE – SQUARE WAVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity square is
generic (
ddsAddressSize : natural;
ddsWordSize : natural;
ddsCounterSize : natural;
outputSize : natural
);
port (
clock
: in std_logic;
reset
: in std_logic;
step
: in unsigned(ddsCounterSize - 1
downto 0);
Squareoutput
: out unsigned(outputSize - 1 downto 0);
SquarenewOutput : out std_logic
);
end square;
architecture rtl of square is
signal counter : unsigned(ddsCounterSize downto 0);
type stateType is (
loadAddress1,
address1Wait1,
address1Wait2,
loadAddress2,
address2Wait1,
address2Wait2,
setOutput,
delay
);
signal state : stateType := loadAddress1;
signal data1 : signed(outputSize downto 0);
signal delayCounter : natural range 0 to 43;
signal ramAddr
: unsigned(3 downto 0);
signal ramData : unsigned(2 downto 0);
begin
process (clock,reset)
begin
if rising_edge(clock) then
-- simple square wave simulator
case ramAddr is
when "0000" => ramData <= "000";
when "0001" => ramData <= "000";
when "0010" => ramData <= "000";
when "0011" => ramData <= "000";
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when "0100" => ramData <= "000";
when "0101" => ramData <= "000";
when "0110" => ramData <= "000";
when "0111" => ramData <= "000";
when "1000" => ramData <= "111";
when "1001" => ramData <= "111";
when "1010" => ramData <= "111";
when "1011" => ramData <= "111";
when "1100" => ramData <= "111";
when "1101" => ramData <= "111";
when "1110" => ramData <= "111";
when "1111" => ramData <= "111";
when others => ramData <= "000";
end case;
end if;
end process;
process(clock, reset)
variable delta : signed(outputSize downto 0);
variable signedFraction : signed(ddsCounterSize - ddsAddressSize downto 0);
variable interpolatedProduct : signed(ddsCounterSize - ddsAddressSize +
outputSize + 1 downto 0);
variable interpolated : signed(outputSize downto 0);
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
case state is
-- set address for getting the first word from memory
when loadAddress1 =>
SquarenewOutput <= '0';
ramAddr <= counter(ddsCounterSize - 1
downto ddsCounterSize - ddsAddressSize);
state <= address1Wait1;
-- some wait cycles, until word is loaded
when address1Wait1 =>
state <= address1Wait2;
when address1Wait2 =>
state <= loadAddress2;
-- get first word from memory and set address for
getting next word
when loadAddress2 =>
data1 <= signed('0' & ramData) & to_signed(0,
outputSize - ddsWordSize);
ramAddr <= counter(ddsCounterSize - 1
downto ddsCounterSize - ddsAddressSize) + 1;
state <= address2Wait1;
-- some wait cycles, until word is loaded
when address2Wait1 =>
state <= address2Wait2;
when address2Wait2 =>
state <= setOutput;
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when setOutput =>
Squareoutput <= unsigned(data1(outputSize 1 downto 0));
counter <= counter + step;
delayCounter <= 42;
state <= delay;
-- add some wait cycles for 1us
when delay =>
if delayCounter = 0 then
SquarenewOutput <= '1';
state <= loadAddress1;
else
delayCounter <=
delayCounter - 1;
end if;
end case;
end if;
end process;
end architecture rtl;
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DESIGN A SIGNAL GENERATOR USING FPGA
APPENDIX E:
WONG PENG YEW
(W0706833)
VHDL SOURCE CODE – TRIANGULAR WAVE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity Triangular is
generic (
ddsAddressSize : natural;
ddsWordSize : natural;
ddsCounterSize : natural;
outputSize : natural
);
port(
clock
: in std_logic;
reset
: in std_logic;
step
: in unsigned(ddsCounterSize - 1 downto 0);
--interpolate
: in std_logic;
Triangularoutput
: out unsigned(outputSize - 1 downto 0);
TriangularnewOutput : out std_logic
);
end Triangular;
architecture rtl of Triangular is
signal counter : unsigned(ddsCounterSize downto 0);
type stateType is (
loadAddress1,
address1Wait1,
address1Wait2,
loadAddress2,
address2Wait1,
address2Wait2,
setOutput,
delay
);
signal state : stateType := loadAddress1;
signal data1 : signed(outputSize downto 0);
signal delayCounter : natural range 0 to 43;
signal ramAddr
: unsigned(3 downto 0);
signal ramData : unsigned(2 downto 0);
begin
process (clock,reset)
begin
if rising_edge(clock) then
-- simple Triangular wave simulator
case ramAddr is
when "0000" => ramData <= "000"; --1
when "0001" => ramData <= "001"; --2
when "0010" => ramData <= "010"; --3
when "0011" => ramData <= "011"; --4
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when "0100" => ramData <= "100"; --5
when "0101" => ramData <= "101"; --6
when "0110" => ramData <= "110"; --7
when "0111" => ramData <= "111";
when "1000" => ramData <= "110";
when "1001" => ramData <= "101";
when "1010" => ramData <= "100";
when "1011" => ramData <= "011";
when "1100" => ramData <= "010";
when "1101" => ramData <= "001";
when "1110" => ramData <= "000";
when "1111" => ramData <= "000";
when others => ramData <= "000";
end case;
end if;
end process;
process(clock, reset)
variable delta : signed(outputSize downto 0);
variable signedFraction : signed(ddsCounterSize - ddsAddressSize downto 0);
variable interpolatedProduct : signed(ddsCounterSize - ddsAddressSize + outputSize + 1
downto 0);
variable interpolated : signed(outputSize downto 0);
begin
if reset = '1' then
counter <= (others => '0');
elsif rising_edge(clock) then
case state is
-- set address for getting the first word from memory
when loadAddress1 =>
TriangularnewOutput <= '0';
ramAddr <= counter(ddsCounterSize - 1 downto
ddsCounterSize - ddsAddressSize);
state <= address1Wait1;
-- some wait cycles, until word is loaded
when address1Wait1 =>
state <= address1Wait2;
when address1Wait2 =>
state <= loadAddress2;
-- get first word from memory and set address for getting next word
when loadAddress2 =>
data1 <= signed('0' & ramData) & to_signed(0,
outputSize - ddsWordSize);
ramAddr <= counter(ddsCounterSize - 1 downto
ddsCounterSize - ddsAddressSize) + 1;
state <= address2Wait1;
-- some wait cycles, until word is loaded
when address2Wait1 =>
state <= address2Wait2;
when address2Wait2 =>
state <= setOutput;
when setOutput =>
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Triangularoutput <= unsigned(data1(outputSize - 1
downto 0));
counter <= counter + step;
delayCounter <= 42;
state <= delay;
-- add some wait cycles for 1us
when delay =>
if delayCounter = 0 then
TriangularnewOutput <= '1';
state <= loadAddress1;
else
delayCounter <= delayCounter - 1;
end if;
end case;
end if;
end process;
end architecture rtl;
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DESIGN A SIGNAL GENERATOR USING FPGA
APPENDIX F:
WONG PENG YEW
(W0706833)
VHDL SOURCE CODE – LEFT RIGHT LEDs
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-----------------------------------------------------------------------------------entity left_right_leds is
Port (
led,freq_selection : out std_logic_vector(7 downto 0);
rotary_a : in std_logic;
rotary_b : in std_logic;
rotary_press : in std_logic;
clk : in std_logic
);
end left_right_leds;
architecture Behavioral of left_right_leds is
-- Signals used to interface to rotary encoder
signal rotary_a_in : std_logic;
signal rotary_b_in : std_logic;
signal rotary_press_in : std_logic;
signal
rotary_in : std_logic_vector(1 downto 0);
signal
rotary_q1 : std_logic;
signal
rotary_q2 : std_logic;
signal delay_rotary_q1 : std_logic;
signal rotary_event : std_logic;
signal rotary_left : std_logic;
-- Signals used to drive LEDs
signal led_pattern : std_logic_vector(7 downto 0):= "00010000"; --initial value puts
one LED on near the middle.
signal led_drive
: std_logic_vector(7 downto 0);
begin
rotary_filter: process(clk)
begin
if clk'event and clk='1' then
-- Synchronise inputs to clock domain using flip-flops in input/output
blocks.
rotary_a_in <= rotary_a;
rotary_b_in <= rotary_b;
rotary_press_in <= rotary_press;
--concatenate rotary input signals to form vector for case construct.
rotary_in <= rotary_b_in & rotary_a_in;
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DESIGN A SIGNAL GENERATOR USING FPGA
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case rotary_in is
when "00" => rotary_q1 <= '0';
rotary_q2 <= rotary_q2;
when "01" => rotary_q1 <= rotary_q1;
rotary_q2 <= '0';
when "10" => rotary_q1 <= rotary_q1;
rotary_q2 <= '1';
when "11" => rotary_q1 <= '1';
rotary_q2 <= rotary_q2;
when others => rotary_q1 <= rotary_q1;
rotary_q2 <= rotary_q2;
end case;
end if;
end process rotary_filter;
-- The rising edges of 'rotary_q1' indicate that a rotation has occurred and the
-- state of 'rotary_q2' at that time will indicate the direction.
direction: process(clk)
begin
if clk'event and clk='1' then
delay_rotary_q1 <= rotary_q1;
if rotary_q1='1' and delay_rotary_q1='0' then
rotary_event <= '1';
rotary_left <= rotary_q2;
else
rotary_event <= '0';
rotary_left <= rotary_left;
end if;
end if;
end process direction;
-- LED control
led_display: process(clk)
begin
if clk'event and clk='1' then
if rotary_event='1' then
if rotary_left='1' then
led_pattern <= led_pattern(6 downto 0) &
led_pattern(7); --rotate LEDs to left
else
led_pattern <= led_pattern(0) & led_pattern(7
downto 1); --rotate LEDs to right
end if;
end if;
-- Pressing the rotary encoder will cause all LED drive bits to be
inverted.
if rotary_press_in='0' then
led_drive <= led_pattern;
else
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--led_drive <= led_pattern xor "11111111";
end if;
--Ouput LED drive to the pins making use of the output flip-flops in
input/output blocks.
led <= led_drive;
freq_selection <= led_drive;
end if;
end process led_display;
end Behavioral;
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GLOSSARY
AC – Alternating Current
Alternating current is the flow of electric charge periodically in reverses direction.
FPGA - Field-Programmable Gate Array
A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by the customer or designer after manufacturing
LCD – Liquid Crystal Display
Digital display that uses liquid crystal cells that change reflectivity in an applied
electric field
DAC - Digital-to-Analog Converter
HDL - Hardware Description Language
A kind of language used for the conceptual design of integrated circuits.
VHSIC - Very-High-Speed Integrated Circuit
VHDL - VHSIC hardware description language
VHDL is a hardware description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable gate arrays and
integrated circuits.
Verilog is a hardware description language used to model electronic systems.
DSP – Digital Signal Processing
DSP is concerned with the representation of signals by a sequence of numbers or
symbols and the processing of these signals.
AM – Amplitude Modulation
AM is a method of sending information by modifying (modulating) the intensity
(amplitude) of a carrier wave.
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DESIGN A SIGNAL GENERATOR USING FPGA
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FM – Frequency Modulation
FM conveys information over a carrier wave by varying its instantaneous frequency
PM – Phase Modulation
PM is a method of sending information by modifying (modulating) the difference in
phase (fraction of a wave length) between a signal and a reference.
QAM – Quadrature amplitude modulation
It conveys two analog message signals, or two digital bit streams, by changing
(modulating) the amplitudes of two carrier waves.
EDA - Electronic Design Automation
EDA is a category of software tools for designing electronic systems such as printed
circuit boards and integrated circuits.
PLDs - Programmable Logic Device
PLD is an electronic component used to build reconfigurable digital circuits.
PROM - Programmable Read Only Memory
PROM is a form of digital memory where the setting of each bit is locked by a fuse or
antifuse.
RTL - Register Transfer Level
RTL description is a way of describing the operation of a synchronous digital circuit.
LED - Light-Emitting Diode
LED is a semiconductor light source.
SPI - Serial Peripheral Interface
SPI is a simple interface that allows one chip to communicate with one or more other
chip.
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