Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
VERILOG HDL MODELING OF CMOS ANALOG
CIRCUITS
STUDENT
SUPERVISOR
PROJECT CODE
: ABDUL AZEEZ (PI NO. Q0805590)
: MR DERRICK TIEW
: JUL2010/ENG/040
A project report submitted to SIM University
In partial fulfillment of the requirements for the degree of
Bachelor of Engineering (or Bachelor of Electronics)
May 2011
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
1
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Abstract
In modern VLSI design, some parts of the circuitry still make use of analog circuit design to
maximize the system performance but this poses logic verification issue at the full-chip level when
all parts (digital & analog circuit blocks) are integrated together. In the current market, designers
face difficulties in their analog circuit designs as it is getting more and more complex then ever as
it poses an increasing complex integration tasks in the digital systems. As such designers need to
model their behavior for quick logic verification during the design phase.
There are many advanced simulation tools like ModelSim where designers acquire to generate
their behavioral simulation. Hardware description languages like VHDL and Verilog are
frequently being used by the designers to model the design’s behavior before the design goes to the
next phase.
The main aim of this project is to model a VLSI design (analog compensation circuit block)
in the behavioral aspect using Verilog HDL and subsequently providing the logic equivalency
analysis with actual analog simulations. This hardware description language would be used to
describe the logic of a VLSI design, where the design’s logic is simulated and verified with a
comprehensive test-bench in Mentor Graphics ModelSim simulator.
This project presents a study of a behavioral modeling of a VLSI design (analog compensation
circuit block) with Verilog HDL. It also presents a simulation result, which shows an identical
comparison of the designed digital simulation and with the actual analog simulation.
With the identical simulation, it shows successful modeling of VLSI design, at which the project
objectives are met. The project concludes with the expression of the conclusion, recommendation
and proposed future works which can be carried out for further improvements.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
2
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Acknowledgement
The author express his top most gratitude is to his project supervisor Mr Derrick Tiew for his
patience, perseverance and for his invaluable advise in times and providing excellent guidance and
encouragement to make this project possible with positive outcomes of this final year project.
Secondly, his greatest interest in heart goes to his family members for their continuous
encouragement, care and support during the difficult phase of the project. At this moment, he
would also like to extend his thanks to his friends Mr Jamal, Mr Ratham and Mr Alagan for their
crucial advices, which had given him great encouragement in each step of his difficult phases of
the project. Lastly, he would like to thank those who had contributed their comments for this
project. Thank you.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
3
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Table of Contents
ABSTRACT………………………………………………………………………………………………………......... 2
ACKNOWLEDGEMENT…………………………………………………………………………………………….. 3
TABLE OF CONTENTS……………………………………………………………………………………………… 4
LIST OF FIGURES………………………………………………………………………………………………........ 5
LIST OF TABLES…………………………………………………………………………………………………….. 6
1
INTRODUCTION………………………………………………………………………………………………... 7
1.1
1.2
1.3
1.4
2
PROJECT PLANNING…………………………………………………………………………………….......... 12
2.1
2.2
2.3
2.4
2.5
3
BACKGROUND AND MOTIVATION……………………………………………………………………… 7
PROJECT OBJECTIVE…………………………………………………………………………………......... 8
PROJECT OVERALL OBJECTIVE…………………………………………………………………………. 9
REPORT ORGENISATION…………………………………………………………………………….......... 10
STRENGTHS AND WEAKNESSES………………………………………………………………………… 13
PROJECT DEVELOPMENTS………………………………………………………………………….......... 14
GANTT CHART……………………………………………………………………………………………… 15
SKILLS REVIEW……………………………………………………………………………………….......... 17
CRITERIA AND TARGETS FOR PROGRESS ASSESSMENT……………………………………………. 18
INVESTIGATION OF PROJECT BACKGROUND…………………………………………………….......... 19
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
HDL BACKROUND………………………………………………………………………………………….. 19
VERILOG HDL………………………………………………………………………………………………. 21
MAIN COMPONENTS IN VERILOG HDL………………………………………………………………….23
VERILOG BEHAVIORL MODELING……………………………………………………………………… 24
3.4.1 VERILOG ASSIGNMENTS……………………………………………………………………………. 28
3.4.2 CASE STATEMENT…………………………………………………………………………………… 28
3.4.3 IF ELSE STATEMENT………………………………………………………………………………… 28
TOP MODULE…………………………………………………………………………………………...........29
ANALOG VERIFICATION…………………………………………………………………………….......... 30
TEST-BENCH………………………………………………………………………………………………… 30
CMOS TECHNOLOGY…………………………………………………………………………………........ 32
PREVIOUS WORKS…………………………………………………………………………………………. 33
3.9.1 Implementation of compensation circuit for cmos push-pulloutput buffer………………………........... 33
4
UNDERSTANDING THE HIERARCHY LEVELS IN ANALOG IC DESIGN FLOW……………………. 36
5
OVERVIEW OF MODELSIM SIMULATOR…………………………………………………………………. 39
6
POTENTIAL RISKS INVOLVED……………………………………………………………………………… 42
6.1 RTL MISMATCH……………………………………………………………………………………….......... 42
6.2 RTL DESIGN SYNTHESIS…………………………………………………………………………….......... 43
6.3 FORMAL EQUIVALENCY CHECK……………………………………………………………………....... 43
7
SIMULATION AND RESULTS………………………………………………………………………………… 44
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
4
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
8
CONCLUSION AND FUTURE WORK………………………………………………………………………... 65
9
REQUIREMENT OF RESOURCES……………………………………………………………………………. 69
REFERENCES………………………………………………………………………………………………………… 70
APPENDIXE A: SOURCE CODES…………………………………………………………………………….......... 72
List of Figures
Figure 1: A traditional verification flow…………………………………………………………………… 7
Figure 2: Basic Limitation of Verilog HDL………………………………………………………………...8
Figure 3: Basics of Digital Design using HDLs…………………………………………………………… 9
Figure 4: Digital vs. Analog design reality………………………………………………………………… 10
Figure 5: Project flowchart………………………………………………………………………………… 12
Figure 6: Gantt chart……………………………………………………………………………………...... 16
Figure 7: Typical digital design flow………………………………………………………………………. 20
Figure 8: Typical Design Flow using Verilog HDL……………………………………………………...... 22
Figure 9: Application Areas of HDLs…………………………………………………………………........ 23
Figure 10: Components of a Verilog Module………………………………………………………….......... 24
Figure 11: Initial and Always condition……………………………………………………………….......... 25
Figure 12: Procedural block execution condition………………………………………………………........ 26
Figure 13: Example for blocking & non-blocking procedural assignments………………………………… 27
Figure 14: Example of conditional statements…………………………………………………………......... 27
Figure 15: An Typical Verilog Top module……………………………………………………………........ 29
Figure 16: Test-bench and design under Verification……………………………………………………….. 30
Figure 17: An Typical Verilog testbench layout…………………………………………………………….. 31
Figure 18: Mixed-signal IC design…………………………………………………………………….......... 32
Figure 19: Initial CMOS Compensator Circuit…………………………………………………………........ 33
Figure 20: Project flowchart………………………………………………………………………………… 34
Figure 21: Final CMOS Analog Compensator circuit blocks………………………………………….......... 35
Figure 22: Design flow of Analog IC design………………………………………………………………... 38
Figure 23: CAD Tool Flow…………………………………………………………………………….......... 39
Figure 24: A creation for a project……………………………………………………………………........... 40
Figure 25: Compilation of all files…………………………………………………………………………... 40
Figure 26: Compilation with no errors………………………………………………………………………. 40
Figure 27: Selection of a test-bench……………………………………………………………………......... 41
Figure 28: Adding signal to see all waveform…………………………………………………………......... 41
Figure 29: Generation of waveforms……………………………………………………………………....... 41
Figure 30: CMOS analog compensation circuit blocks…………………………………………………....... 45
Figure 31: Delay Chain block………………………………………………………………………….......... 46
Figure 32: Delay chain block simulation screen shot………………………………………………….......... 47
Figure 33: Tri-state block……………………………………………………………………………………. 49
Figure 34: Tri-state block simulation screen shot…………………………………………………………… 50
Figure 35: Bias Generator Block………………………………………………………………………......... 52
Figure 36: Bias generator block simulation screen shot……………………………………………….......... 53
Figure 37: Slew rate control Block…………………………………………………………………….......... 55
Figure 38: Slew rate block simulation screen shot…………………………………………………….......... 57
Figure 39: Strength control block…………………………………………………………………………… 59
Figure 40: Strength control block simulation screen shot……………………………………………………60
Figure 41: Strength control top block simulation screen shot………………………………………………. 61
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
5
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 42: Top module simulation screen shot……………………………………………………………… 63
Figure 43: Flowchart for modeling a CMOS analog compensation circuit block…………………………... 64
List of Tables
Table 1: Skills review………………………………………………………………………………….......... 17
Table 2: Criteria and targets settings for progress assessments…………………………………………....... 18
Table 3: Delay chain truth table…………………………………………………………………………....... 46
Table 4: Delay chain analog vs digital comparison……………………………………………………......... 48
Table 5: Tri-state truth table………………………………………………………………………………….49
Table 6: Tri-state analog vs digital comparison…………………………………………………………....... 51
Table 7: Bias generator truth table………………………………………………………………………....... 52
Table 8: Bias generator analog vs digital comparison………………………………………………………. 54
Table 9: Slew rate truth table……………………………………………………………………………....... 55
Table 10: Slew rate analog vs digital comparison………………………………………………………....... 58
Table 11: Strength control truth table………………………………………………………………….......... 59
Table 12: Strength control analog vs digital comparison………………………………………………........ 62
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
6
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
1
INTRODUCTION
1.1
BACKGROUND AND MOTIVATION
Designers of today need to model their designs before the real construct of their designs. This step
is crucially needed to avoid logic verification issues if especially if their design has a
combinational of digital and analog circuitry.
In order to model (behavioral modeling) their design, designers turn to hardware description
languages (HDL) like VHDL or Verilog, which were used to write executable specifications of
some piece of hardware. A simulation program, designed to implement the underlying semantics
of the language statements, coupled with simulating the progress of time, provides the hardware
designer with the ability to model a piece of hardware before it is created physically.
Figure 1: A traditional verification flow (some designers try to mimic the behavioral of analog
functions via a Verilog behavioral model)
Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling
exist, and HDLs targeted for each are available [23].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
7
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
1.2
PROJECT OBJECTIVE
The main objective of this project is to study the behavior of CMOS analog circuit blocks like
CMOS compensation circuit block. The analog circuit block is then modeled efficiently in
behavioral level with Verilog Hardware Description Language.
With the design created in Mentor Graphics’s ADK Design Architect-IC, the behavioral aspects of
the circuit block are first studied before the modeling of the block takes place. Mentor Graphic’s
ModelSim simulation tool was recommended for the simulation and for the verification process.
With the limitations of using Verilog HDL, the CMOS analog circuitry is modeled digitally.
Figure 2: Basic Limitation of Verilog HDL
With the logic of the analog block is described in Verilog HDL, the model goes through a
simulation process. A simulation process allows the Verilog HDL description of the model to pass
design verification, an important step that validates the design's intended function against the code
implementation in the Verilog HDL description.
The waveforms with the validation of the test-bench, shows how actually the model response to
various inputs versus the expected outputs and that is an crucial step for a successful modelling.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
8
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 3: Basics of Digital Design using HDLs
1.3
PROJECT OVERALL OBJECTIVE
In the current design industry, analog designers are facing the ever-increasing complexity of their
analog circuit designs in the digital systems. As analog designers integrate more complex logics on
a single chip, they encounter logic verification issues at full chip level especially when all parts
(digital & analog blocks) are integrated together.
The performance of analog blocks is a key factor in the success of an integrated circuit. To create a
complete solution and achieve the target of first time right analog systems, careful methodologies,
tool flow and an appropriate set of tools must be used by the analog designers [9].
Designers of today need to partition the analog circuits into behavioral blocks by simplifying its
logics using HDLs. And that has proved to be an efficient method for quick logic verification as
designers analysis the block’s behavior before they are being integrated with large digital systems.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
9
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 4: Digital vs. Analog design reality
The aim of this project is to understand and model the behavior of CMOS analog circuit
blocks using Verilog HDL and subsequently providing the logic equivalency analysis with
actual analog simulations. The digital behavioral simulations with a complete comprehensive
test-bench would also be shown and analyzed.
The main tasks of the project includes:
-
Background study and Literature on digital design flow
-
Background study on Verilog programming language
-
Research and study of Verilog behavioral modeling
-
Research and study of Analog verifications
-
Research and study on Test-bench
-
Research and study of Analog IC Design Flow
-
Learn and study of ModelSim Simulator
-
Reasearch and study potential risks involved
-
Simulation and results
-
Writing of Final year project technical report
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
10
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
1.4
REPORT ORGANISATION
This technical report is divided into 9 chapters;
Chapter2 – Project planning
Chapter3 – Investigation on project background
Chapter4 – Understanding the hierarchy levels in analog IC design flow
Chapter5 – Overview of ModelSim simulator
Chapter6 – Potential risk involved
Chapter7 – Simulation and results
Chapter8 – Conclusion and future works
Chapter9 – Requirement of resources
References
Appendix
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
11
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
2
PROJECT PLANNING
This chapter explains methods employed to reach project objectives. The different phases and
contribution of each phase, the strength review, and skills required. The tools used for time
management on the project.
The work breakdown of the core structure of the project is shown below
Figure 5: Project flowchart
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
12
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
The project plan was divided in 7 components.
1. Project Planning, Research and Time management
2. Background study and Literature review
3. Learning of Verilog HDL and ModelSim Simulator
4. Research and learning on Behavioral modeling
5. Design Implementation
6. Simulation, Verification and Testing
7. Final Report, Poster and Presentation
2.1
STRENGTHS AND WEAKNESSES
This project development required some good knowledge of CMOS analog circuits and Verilog
hardware description language (HDL) programming. The previous modules like CMOS VLSI
design, which I have taken in UniSIM, has helped me prepared in the required knowledge in my
project development of the area of CMOS circuits. The top most priority should be picking up the
Verilog HDL programming skills as well as the understanding CMOS analog blocks.
My main weakness would be Verilog HDL programming, as this program language is totally new
to me. I am currently taking this as a challenge to learn this language. A lots of reading in the
Verilog HDL, online tutorials and further more my FYP tutor guidance will be a great help for my
understanding as well.
Having identified the strengths and weaknesses, constantly tracking and review of the project will
make sure that I always head towards the right direction. This also guides me to pursue the
objective of the project and make sure I don’t deviate from the project goals. These are essentials
to ensure that I will be able to deliver the project objectives on time.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
13
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
2.2
PROJECT DEVELOPMENTS
The project started with four main phases, careful time management was required in each phase.
My project started with initial phase, where I started to study some basic Verilog HDL codes of
Half-adder and Full-adder. This enabled me to get familiar with main logic module and test-bench.
I also spent some time in the learning of the ModelSim simulator. With that, I began with some
basic simulations and got myself familiarized with gate level programming.
After which, I spent some time studying the project done by the former project student, whereby
running analog simulations and creating truth-tables based on it. I also begin to study the different
Verilog modules on its behavioral aspects, program encoding, and simulation results.
At my second phase, I further analyzed the CMOS analog compensation circuit block which
consists of five different blocks and began building up the behavioral models with program
encodings according to analog based truth-tables, creation of simulations with comprehensive testbenches, and verification of each of the single models in the behavioral aspects.
Third phase was the most crucial and most conclusive phase. I started to integrate the modules to
the top module and wrote the top test-bench. This concludes with a final verification of the
simulated behavioral waveform with the actual analog waveform.
In the last phase, results of the work done were documented in a technical report and the
preparation of a poster with presentation slides.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
14
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
2.3
GANTT CHART
A Gantt chart provides an overview schedule of activities, which are broken down into phases to
better time management, enhance the ability to focus and monitor the progress of the Project.
The Gantt chart was created for the delivery of this project with the consideration of planning,
research and development, understanding of programming application, implementation
methodology, simulation and verifications, well documented report with poster and presentations
are essential to fulfill the project scope and requirements.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
15
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 6: Gantt Chart
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
16
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
2.4
SKILLS REVIEW
Since I started this project with limited knowledge on Verilog HDL, I spent more time in learning
the language especially in the behavioral aspect. My understanding of the CMOS transistor and
circuit which would be my strong point. But continous reading and research (internet, books, etc)
enabled me to acquire in-dept knowledge on both Verilog HDL and CMOS analog circuits.
Skills
Verilog HDL
Source/ Methods
Reference book from Library
Internet research
Simulator ModelSim Web pack
Internet tutorial guide
FYP tutors guide
Modeling of CMOS Analog Circuits with
Verilog HDL
Proficiency in Verilog HDL
Reference book for Library
Internet research
FYP tutors guide
Computer Literacy
Proficiency in Microsoft office
Report typing
For simulation and programming
Mentor Graphics circuit sanitary check
Visual checking
Reading circuit design
Assessing and evaluating of project
progress
Targets setting
Project management
Validating the model via simulation results
Implementation
Testing of models
Debugging and troubleshooting of models
Presentation
Report writing skills
Oral and presentation skills
Organize and prepare data and diagrams for
presenting.
Table 1: Skills review
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
17
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
2.5
CRITERIA AND TARGETS FOR PROGRESS ASSESSMENT
Item
Criteria / Target
Due Date
Status
1
Draft of Project proposal
21-Aug-10
Completed
2
Submission of proposal
06-Sep-10
Completed
3
Background study and Literature Review
30-Sep-10
Completed
4
Familiarizing with ModelSim simulator
30-Sep-10
Completed
4
Testing on some basic Verilog HDL
30-Sep-10
Completed
5
Submission of Interim Report
08-Nov-10
Completed
6
Research and Learning Verilog HDL
31-Mar-11
Completed
7
Research and learning behavioral modeling
31-Mar-11
Completed
8
Design Implementation
31-Mar-11
Completed
9
Simulation, verification and testing
31-Mar-11
Completed
10
Submission of Project Report
16-May-11
Completed
11
Final Report, Poster and presentation
04-June-11
Completed
Table 2: Criteria and targets settings for progress assessments
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
18
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
3
INVESTIGATION OF PROJECT BACKGROUND
3.1
HDL BACKGROUND
Years ago, as integrated circuits grew in complexity; a better method for designing them was
needed. Schematic capture tools had been developed which allowed an engineer to draw
schematics on a computer screen to represent a circuit. This worked well because graphic
representations are always useful to understand small but complex functions.
But as chip density increased, schematic capture of these circuits became unwieldy and difficult to
use for the design of large circuits. Thus hardware description languages (HDLs) came into
existence [25].
HDLs allowed the designers to model the concurrency of processes found in hardware elements.
Hardware Description Languages (HDLs) such as Verilog HDL and VHDL became popular for
logic verification.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
19
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 7: Typical digital design flow
The design flow above is typically used by designers who use HDLs. In any design, specifications
are written first. The specification described abstractly the functionality, interface and the overall
arhitecture of the digital circuit to be designed. Behavioral description is created to analyse the
design in terms of functionality and performance. The behavioral description can be written in
HDLs and it is then manually converted to an RTL description, the design process is done with the
assistance of Computer-Aided Design (CAD) tools.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
20
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Eventually the designers use Logic synthesis tools to convert the RTL description to gate-level
netlist. The gate-level netlist is input to an Automatic Place and Route tool, which creates a layout.
The layout is verified and fabricated on a chip.
3.2
VERILOG HDL
The Verilog HDL (Hardware description language) is one of the most used HDLs. It became an
IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and
effective at multiple levels of abstraction (algorithmic level, register transfer level (RTL), gate
level and switch level) in a standard textual format [6]
An overwhelming number of IC designers use Verilog HDL for a variety of design tools, including
verification simulation, timing analysis, test analysis, and synthesis. But why Verilog HDL?
-
It is simply easier to learn and use
-
It has a similar in syntax to C programming language which means designers
with C programming experience will find it easier to learn Verilog HDL
-
It allows different levels of abstraction to be used in the same design. Thus a designer
needs to learn only one language for the stimulus and hierarchical design
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
21
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 8: Typical Design Flow using Verilog HDL
-
Most of the synthesis tools support Verilog HDL and that makes the language of choice for
the designers.
In the commercial world, Verilog HDL was developed as part of a complete simulation system to
be used for describing digitally based hardware systems to allow designers to represent their
designs in the familiar method (gate and switch level descriptions) as well as abstractly or
behaviorally [11]. Semiconductor and electronic design industry use Verilog (HDL) to model
electronic systems for the design, verification, and implementation of digital logic chips at the
register transfer level (RTL) of abstraction.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
22
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 9: Application Areas of HDLs
3.3
MAIN COMPONENTS IN VERILOG HDL
A Verilog module definition always begins with the keyword module and the five main
components of a module are variable declaration, dataflow statements, instantiation of lower
modules, behavioral blocks and tasks or functions. These components can be in any order and at
any place in a module definition.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
23
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 10: Components of a Verilog Module
The endmodule statements must come last in a module definition. Verilog allows multiple
modules.
3.4
VERILOG BEHAVIORAL MODELLING
A Verilog Behavioral language constructs introduced to allow hardware to be described at a
relatively detailed level without attempting to explain how it does it. They are written with the
fewest constraints. They may or may not be synthesizable, they may or may not include
timing, and they may or may not be cycle accurate. They may be intended for use in
architectural exploration, performance modeling, or hardware/software co design.
Modeling a circuit with logic gates and continuous assignments reflects quite closely the logic
structure of the circuit being modeled. Verilog provides designers the ability to describe design
functionality in an algorithmic manner where in other words, the designer describes the behavior
of the circuit. Thus, behavioral modeling represents the circuit at a very high level of
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
24
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
abstraction. Verilog is rich in behavioral constructs that provide the designer with a great amount
of flexibility [12].
In a Verilog behavioral modeling, there are four structures used in the modeling of a circuit’s
behavior;

procedural block

procedural assignment

timing control

control statement
Procedural blocks which consist of initial and always are the basic for a behavior modeling. An
initial procedural block only execute only once whereas an always procedural block executes in a
loop.
Figure 11: Initial and Always condition
All procedural blocks are activated at zero simulation time but will not execute until the block
evaluates ‘true’ condition. When the enabling condition is met, the block will be executed
immediately.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
25
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 12: Procedural block execution condition
Procedural assignment – drives or assigns values or expressions onto registers and introduced by
always block, tasks and function. It can be modeled as blocking and nonblocking.
Block procedural assignments are represented by [=]

evaluated and assigned in a single step

execution flow within the procedure is blocked until the assignment is
completed.

evaluation of concurrent statements in the same time step are blocked until
the assignment is completed.
Nonblocking procedural assignments are represented by [<=]

evaluated and assigned in two steps:

the right-hand is evaluated immediately

the assignment to the left-hand side is postponed until other evaluations
in the current time step are completed

execution flow within the procedure continues until a timing control is
encountered (flow is not blocked)
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
26
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 13: Example for blocking & non-blocking procedural assignments
Timing control – simple delay control, event control and level-sensitive timing control
Conditional statements – If, if-else and case
Figure 14: Example of conditional statements
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
27
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
3.4.1 VERILOG ASSIGNMENTS
In Verilog there are two forms of assignment statements;

Continuous assignments

Procedural assignments
Continuous assignments are used to model combinatorial logic in a concise way. Both explicit
and implicit continuous assignments are supported. Explicit continuous assignments are introduced
by the assign keyword after the net has been separately declared. Implicit continuous assignments
combine declaration and assignment [26].
Procedural assignments are used to assign values to variables declared as regs and introduced by
always blocks, tasks and functions [26].
3.4.2 CASE STATEMENT
Case statements perform a comparison to an expression to evaluate one of a number of parallel
branches. The Case statement evaluates the branches in the order they are written. The first branch
that evaluates to true is executed. If none of the branches match, the default branch is executed
[26].
3.4.3 IF ELSE STATEMENT
If... else statements use true/false conditions to execute statements. If the expression evaluates to
true, the first statement is executed. If the expression evaluates to false (or x or z), the else
statement is executed. A block of multiple statements may be executed using begin and end
keywords. If...else statements may be nested [26].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
28
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
3.5
TOP MODULE
Top module is a main module in which zero or more low-level modules can be instantiated. Lowlevel modules can be also instantiated at lower lever level modules.
Figure 15: An Typical Verilog Top module
A top level module has the following features

Instantiation of modules to be simulated

Initial and/or always blocks that drive the input signals

Code that generates outputs and stops simulations
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
29
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
3.6
ANALOG VERIFICATION
Analog verification is a methodology for performing functional verification on analog,
mixed-signal and RF integrated circuits and systems on chip. Discussion of analog verification
began in 2005 when it started to become recognized that the analog portion of large mixed-signal
chips had gotten so complex that a significant and ever increasing number of these chips were
being designed with functional errors in the analog portion that prevented them from operating
correctly.
Analog verification built on transistor level simulation will always be too slow to provide adequate
functional verification. Instead, it is necessary to build simple and efficient models of the blocks
that make up the analog portion of the design and use those to verify the design. Those models are
typically written in HDL like Verilog, VHDL for quick verifications or analysis [8].
3.7
TEST-BENCH
The term “test-bench” usually refers to simulation code used to create a predetermined input
sequence to a design, then optionally to observe the response. The test-bench provides inputs to the
design and watches any outputs. Notice how this is a completely closed system: no inputs or
outputs go in or out. The test-bench is effectively a model of the universe as far as the design is
concerned [10].
Figure 16: Test-bench and design under Verification
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
30
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
A test bench has four components; input, procedure to do, procedure to check and output.
In a analog design, building a simple functional model is not sufficient. It is also necessary to
build a comprehensive self-checking test-bench that thoroughly checks the design and compares
its response against a previously written specification for the design. Furthermore, this testbench
should be applied in turn to both the model and the design. In this case, the design is represented
with a transistor-level schematic. If both the model and the design pass all tests, and if the
testbench is comprehensive, then this confirms that the model is consistent with the design and that
the design is consistent with the specification. [8]
Figure 17: An Typical Verilog testbench layout
Applying a comprehensive testbench to an entire analog functional unit at the transistor level is
impractical. So the verification must proceed hierarchically.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
31
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
First build simple models and test-benches for individual blocks. The block-level testbenches are
used to confirm that models match the implementation of the blocks and that the implementation
matches the block-level specification. Then test-benches are built for the entire analog functional
unit and applied to the top-level schematic of that unit with the blocks represented with their now
verified models [8].
3.8
CMOS TECHNOLOGY
Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing integrated
circuits (IC). CMOS technology is used in microprocessors, microcontrollers, static RAM, and
other digital logic circuits. CMOS technology is also used for several analog circuits such as image
sensors, data converters, and highly integrated transceivers for many types of communication.
CMOS is also an ideal technology for mixed-signal designs for dense digital logic and highperformance analog.
Figure 18: Mixed-signal IC design
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
32
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
3.9
PREVIOUS WORKS
This project is creating a behavioral modeling of a compensation circuit was created by a previous
student using a Mentor Graphics ADK Design Architect-IC toolset. Let us review this project.
3.9.1 Implementation of a compensation circuit for cmos push-pulloutput buffer
By LIM TECK HUA

Project scope and objective
The main of the project was to design and simulate an optimized compensation circuit with
drive strength, slew rate and delay adjust for CMOS push-pull output buffer using Mentor
Graphics tool or SPICE. The additional feature of the project include Bias generator that
will generates constant current over the PVT (process, voltage and temperature) variation.
It is also a control system for the slew rate control circuit.
Figure 19: Initial CMOS Compensator Circuit
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
33
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________

Proposed approach
Figure 20: Project flowchart
The approach taken by me was to first understand the use of the software ‘MENTOR GRAPHICS
& PSPICE’ and the design concept of the CMOS compensation circuit. The understanding will
allow me to create schematic diagram of any circuit simulating the design circuit, measure the
propagation delay of the design circuit and sizing the transistors.
The design of the compensation circuit consists of tri-state control logic, slew rate control predriver and CMOS circuit.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
34
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________

Results and conclusion
Figure 21: Final CMOS Analog Compensator circuit blocks
Figure 21 shows the final version of the simulated compensation circuit. Each block was initial
tested and compiled to circuit blocks.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
35
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
4.0
UNDERSTANDING THE HIERARCHY LEVELS IN ANALOG IC
DESIGN FLOW
Designers implement the concepts Hierarchy in their IC designs. The levels like, system level,
block level, circuitry level, layout hierarchy stage and fabrication and testing gives a general guide
line for their designs.
System Level
System level is the first stage of development, the required target specifications, technology
process are defined. The overall architecture of the system is designed and partitioned into a set of
high-level building blocks for the next level. During this phase, specifications for system are
mapped into intermediate-level parameters which become the specifications for the lower level
building blocks. The system-level partitioning and specification are then verified using appropriate
high-behavioral tools or system simulators such as Matlab, Verilog AMS, MMSIM, etc [9].
Block Level
[As mentioned earlier, there are few stages where analog designer would need to follow in their
analog IC design. For this project the block level is what would be focused on this project]
Block level is an effective translation of the high-level building blocks into architecture of
functional blocks required to realize the specified behavioral description. Then, all block are
described individually in an appropriate hardware description languages, like verilog and
then verified against the specification using behavioral simulations tools, such as Ultrsim,
NcSim, Hsim, Modelsim,etc [9].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
36
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Circuit Level
For each analog building block an optimization process is provided, given the inherited
specifications from the upper level and the selected technology process. The optimization is seen
as an iterative process to determine physical dimensions at device-level. This stage covers two
nuclear activities: the selection of the proper circuit topolgy and a device sizing methodogy of the
circuit parameters. A robust design should be achieved taking into account the process variations
and device tolerances in order to guarantee a high yield design. The required performance
specifications of the final circuit design are then verified using circuit simulations such as HSPICE
and Spectre [9].
Layout Hierarchy
In this stage the optimised building blocks obtained from the preceding step are mapped into a
physical representation of the circuit schematic taking the form of a multilayer layout. Layout is
set of geometric shapes obeying designs rues specified by the fabrication process. The layout area
generated munually or automatically is optimized for minimun area. After the verification phase
(verification of the design rules (DRC)) layout is followed by the extraction of layout parasitics.
Those effects are then verified with circuit simulation in order to ensure that the initial
performance does not deviate significantly from target specification even with their influence.
Crosstalk, substrate coupling analysis and mismatch are also important subjects under the umbrella
of layout techniques [9].
Fabrication and Testing
In this stage the masks are generated and the IC is finally produced. The fabrication process is
accompanied by rigorous qualitytest to avoide defective devices. The test and validation are
fundamental steps to verify the correct operation of the circuit and so a good test board and test
setup must be defined [9].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
37
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
During the top-down path, each of these hierarchical levels is combined with a top-down and
bottom-up strategy together with redesign or black-tracking iteration loops.
Figure 22: Design flow of Analog IC design
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
38
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
5
OVERVIEW OF MODELSIM SIMULATOR
Icon ModelSim
ModelSim is an entry-level simulator which offers VHDL, Verilog, or mixed-language simulation.
It is coupled with the most popular HDL debugging capabilities in the industry, ModelSim PE is
known for delivering high performance, ease of use, and outstanding product support.
ModelSim PE fully supports the VHDL and Verilog language standards. You can simulate
behavioral, RTL, and gate-level code separately or simultaneously. ModelSim PE also supports all
ASIC and FPGA libraries, ensuring accurate timing simulations.
Figure 23: CAD Tool Flow - a simple design through the Computer Aided Design (CAD) toolflow, starting from design entry all the way to programming the hardware
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
39
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Below are the few simple steps with screen shots to create a project using ModelSim simulator
Figure 24: A creation for a project
Figure 25: Compilation of all files
Figure 26: Compilation with no errors
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
40
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 27: Selection of a test-bench
Figure 28: Adding signal to see all waveform
Figure 29: Generation of waveforms
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
41
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Advantages of ModelSim simulator
-
Cost-effective HDL simulation solution
-
Intuitive GUI for efficient interactive debug
-
Integrated project management simplifies managing project data
-
Easy to use with outstanding technical support
-
Sign-off support for popular ASIC libraries
-
Award-winning technical support.
6
POTENTIAL RISKS INVOLVED
6.1
RTL MISMATCH
When designing digital integrated circuits with a hardware description language, the designs are
usually engineered at a higher level of abstraction than transistor or gate level. In HDLs the
designer declares the registers, and describes the combination logic by using constructs that are
common in programming languages such as if-then-else and arithmetic operations. This level is
called register transfer level [14].
The HDL coding styles can cause mismatches between RTL and gate-level simulations if any
coding style that gives the HDL simulator information about the design that cannot be passed on to
the synthesis tool is a bad-coding style. Additionally, any synthesis switch that provides
information to the synthesis tool that is not available to the simulator is bad.
If these guidelines are violated, the pre-synthesis RTL simulations will not match the post
synthesis gate level simulations. These mismatches can be very hard to detect if all possible logic
combinations are not fully tested. The solution is to understand what coding styles or synthesis
switches can cause RTL to gate level simulation mismatches and avoid these constructs [15].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
42
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
6.2
RTL DESIGN SYNTHESIS
In electronics, typically in register transfer level (RTL), logic synthesis is a process by which an
abstract form of desired circuit behavior is turned into a design implementation in terms of logic
gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog
[16].
A large subset of VHDL or Verilog cannot be translated into hardware. This subset is known as the
non-synthesizable and can only be used for prototyping, simulation and debugging [17].
So in this project, we did not synthesize a hardware description language to an analog circuit
but a analog circuit was modeled (behavioral) in Verilog HDL.
6.3
FORMAL EQUIVALENCY CHECK
Logic equivalence checking or Formal equivalency checking process is a part of electronic design
automation (EDA), commonly used during the development of digital integrated circuits, to
formally prove that two representations of a circuit design exhibit exactly the same behavior. In
general, there is a wide range of possible definitions of functional equivalency checks covering
comparisons between different levels of abstraction and varying granularity of timing details. The
most common approach is to consider the problem of machine equivalenct which defines two
synchronous design specifications functionally equivalent if, clock by clock, they produce exactly
the same sequence of output signals for any valid sequence of input signals [13].
A formal equivalency check can be performed between any two representations of a design: RTL
<> netlist, netlist <> netlist or RTL <> RTL, though the latter is rare compared to the first two.
Typically, a formal equivalence checking tool will also indicate with great precision at which point
there exists a difference between two representations [13].
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
43
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Conformal tool is a technology which checks the functional equivalence of versions of a design at
various critical stages to help the designer quickly identify and correct errors. Conformal
equivalence checker does not share technology with design tools, ensuring an independent
verification audit of the design flow. This complete, independent verification minimizes design respin risk. With thousands of tape-outs, conformal technology is the industry's most widely
supported equivalence checking solution [22].
7
SIMULATION AND RESULTS
How the Digital Circuit is being modeled behaviorally
Shown below is the overview of a CMOS analog compensation circuit and detailed explanations
of how each of the blocks was modeled.
The initial stage for modeling the CMOS analog circuit begins with the forming of the truth tables
based on the logic behind the actual analog simulation and for each of the blocks, the inputs and
output ports are defined together with the direction flow of logics and its default settings.
The second stage would be using Verilog HDL to code each of the blocks in behaviorally and
simulating each blocks with a comprehensive test-bench.
The final conclusive stage for a successful modeling would be based the verifications of the
behaviorally modeled digital simulation with the truth table based on the actual analog logic and
comparison with the actual analog simulation.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
44
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
What is a Compensation Circuit?
The compensation circuit is a circuit, which compensates a signal caused by digital or an analog
circuitry. The CMOS analog compensation circuit blocks shown below was created by Mentor
Graphics’s ADK Design Architect-IC was behaviorally modeled and it consists of five main parts,
delay control chain block, bias generator block, tristate control block, slew rate control block
and strength control block with each having a significant function to drive the CMOS analog
compensation circuit block. Without going into the detailed functions of each blocks (which is not
required in this project). The following blocks were modeled in the behavioral aspects. The
simulation and its logic details were discussed in this chapter.
Figure 30: CMOS analog compensation circuit blocks
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
45
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Defining the inputs and outputs, forming of the design table & waveforms
In every behavioral modeling of the blocks begins with the definition of the truth table. In this
project, there are total of five blocks being modeled. The modeling of each block and together with
the integration of the five blocks to the top level modeling would be explained in details.
Delay Chain Block
Figure 31: Delay Chain block
Data_in
HIGH Z
Don’t care
0
1
1
1
1
1
1
1
1
Del (d1,d2,d3)
Don’t care
HIGH Z
Don’t care
000
001
010
011
100
101
110
111
Date delay
HIGH Z
HIGH Z
0
500ns delay
600ns delay
700ns delay
800ns delay
750ns delay
850ns delay
950ns delay
1050ns delay
Table 3: Delay chain truth table
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
46
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
As mentioned, the modeling of the delay chain block begins with the creation of the delay chain
truth table as shown in Table 3. The delay chain block waveform was generated in accordance to
the truth-table and the simulation results are shown in Figure 31. The input ports of the delay chain
block are data_in and Del (d1, d2, d3). The output port is data_delay.
When the data_in generates logic “high”, and if the ports del has a logic change of ‘low’ to ‘high’
or ‘high’ to ‘low’, the data_delay port generates a pulse delay. With the transition carries on, the
signal data_delay increases up to 1050ns.
For the condition, where the input port data_in has a logic ‘low’ condition and regardless of the
condition of Del input ports, the data_out will have logic ‘low’.
For the condition, with at least one of the input ports has a high Z condition, the output port will
have high Z condition.
The successful modeling of the delay chain block is shown at the Figure 32.
Figure 32: Delay chain block simulation screen shot
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
47
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Table 4 shows the comparison between the analog simulation and the behaviorally modeled digital
simulation at del logic of ‘000’ and ‘111’.
Comparison at del ‘000’
Comparison at del ‘111’
Table 4: Delay chain analog vs digital comparison
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
48
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Tri-state block
Figure 33: Tri-state block
The signal from the delay chain block next connects to the tri-state block. The modeling of the tristate block was based on the truth-table as shown in Table 5. A simulation result was created with
a comprehensive test-bench.
Tri-state
HIGH Z
Don’t care
1
0
0
Data_delay
Don’t care
HIGH Z
Don’t care
0
1
Data_up
HIGH Z
HIGH Z
1
0
1
Data_dn
HIGH Z
HIGH Z
0
0
1
Table 5: Tri-state truth table
In the tri-state block modeling, the input ports are tri-state and data_delay. The output ports are
data_up and data_dn.
For the condition of at least one of the input ports has a high Z or the tri-state port has logic
‘high’, the output ports data_up and data_dn will be high Z.
For the condition of tri-state input port has logic ‘high’ and regardless of the logic of input port
data_delay, the data_up and data_dn will have logic ‘high’ and ‘low’ respectively.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
49
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
And if the tri-state port has logic ‘low’ and if data_delay has logic ‘low’, both the output signals at
data_up and data_down would be logic ‘low’. Likewise, if the tri-state port has logic ‘low’ and if
data_delay have logic ‘high’, both the output signals at data_up and data_down would be logic
‘high’.
The successful modeling of the tri-state is shown at the Figure 34.
Figure 34: Tri-state block simulation screen shot
Table 6 shows the comparison between the analog simulation and the behaviorally modeled digital
simulation when tri-state is enabled or disabled.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
50
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Tri-state disable/ logic ‘low’
With tri-state logic ‘low’ and
with data_delay is logic
‘low’, both data_up and
data_dn are logic ‘low’
Tri-state enable/ logic ‘high’
With tri-state logic ‘high’
and regardless logic of
data_delay, data_up is logic
‘high’ and data_dn is logic
‘low’
Table 6: Tri-state analog vs digital comparison
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
51
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Bias Generator block
Figure 35: Bias Generator Block
Bias Gen
HIGH Z
1
0
Vp_bias
HIGH Z
0
1
Vn_bias
HIGH Z
1
0
Table 7: Bias generator truth table
Both the signals from the tri-state block and bias generator block is connected to the slew rate
block, which means the output of the slew rate would be predicted based on the input signals from
both the tri-state and bias generator block. In modeling of the bias generator, the input port is bias
gen and the output ports are vp_bias and vn_bias.
The input port bias gen will have the following three conditions, high Z, logic ‘high’ and logic
‘low’. In order for the signal in the bias gen to be transmitted, bias gen ports must have logic
’high’ or logic ‘low’. In logic ‘high’, the vp_bias becomes logic ‘low’ and vn_bias becomes logic
‘high’ and if bias generator transmits logic ‘low’, the vp_bias and vn_bias switches to the opposite
signals.
But if in the condition, where the input ports have a high Z condition, output ports will also have
high Z condition.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
52
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
The successful modeling of the bias generator block is shown at the figure 36.
Figure 36: Bias generator block simulation screen shot
Table 8 shows the comparison between the analog simulation and the behaviorally modeled digital
simulation when bias generator is enabled or disabled.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
53
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Bias generator disable/ logic ‘low’
With tri-state logic ‘low’
and Vp is logic ‘high’ and
Vn is logic ‘low’
Bias generator enable/ logic ‘high’
With tri-state logic ‘high’
and Vp is logic ‘low’ and
Vn is logic ‘high’
Table 8: Bias generator analog vs digital comparison
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
54
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Slew rate block
Figure 37: Slew rate control Block
SR
HIGH Z
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Vp_bias
Don’t care
HIGH Z
Don’t care
Don’t care
Don’t care
1
Vn_bias
Don’t care
Don’t care
HIGH Z
Don’t care
Don’t care
0
Data_up
Don’t care
Don’t care
Don’t care
HIGH Z
Don’t care
Don’t care
Data_dn
Don’t care
Don’t care
Don’t care
Don’t care
HIGH Z
Don’t care
Pslew
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
1111
Nslew
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
0000
000
001
011
111
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0001
0011
0111
1111
0001
0011
0111
1111
000
001
011
111
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1110
1100
1000
0000
1110
1100
1000
0000
Table 9: Slew rate truth table
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
55
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
As mentioned in the previous, slew rate outputs results are based on the input signals of SR ports,
vp_bias, vn_bias, data_up, data_data down.
The modeling of the slew rate block is similar to the previous blocks, the slew rate blocks input
ports consists of three bit sr ports, vp bias, vn bias, data_up and data_dn. The output ports consist
of Pslew and Nslew. Each of them is having four ports, which consist of n1 to n4 and p1 to p4.
For the conditions at ports vp_bias and vn_bias are set initially to logic ‘high’ and logic ‘low’
respectively and regardless of SR, data_up and data_down. All the output ports of Pslew should
have logic ‘high’ and the output ports of Nslew should have logic ‘low’.
The main function begins at ports SR where the logic runs from ‘000’, ‘001’, ‘011’ and ‘111’. As
for the ports vp_bias, vn_bias, data_up, data_data down holding at logic ‘low’, ‘high’, ‘low’ and
‘low’ or logic ‘low’, ‘high’, ‘high’ and ‘high’ the Pslew and Nslew will have an output signals as
shown at the truth-table.
If in any of the condition, if at least one of the input ports has a high Z condition, output ports will
also have a high Z condition.
The successful modeling of the slew rate is shown at the Figure 38.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
56
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Figure 38: Slew rate block simulation screen shot
Table 10 shows the comparison between the analog simulation and the behaviorally modeled
digital simulation when Slew rate at SR logic ‘000’.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
57
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Slew rate at SR logic ‘000’
With vn bias logic ‘high’ and vp bias logic ‘low’,
data_up & data_dn logic both ‘low’, Pslew and
Nslew have logic ‘high’ at p1 and n1 respectively
Table 10: Slew rate analog vs digital comparison
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
58
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Strength control block
Figure 39: Strength control block
Truth table Strength control block
Enable
HIGH Z
Don’t care
Don’t care
Pslew
Don’t care
HIGH Z
Don’t care
Nslew
Don’t care
Don’t care
HIGH Z
Data_out
HIGH Z
HIGH Z
HIGH Z
0
Don’t care
Don’t care
HIGH Z
1
1
1
1
xxx0
xx00
x000
0000
xxx0
xx00
x000
0000
1
1
1
1
1
1
1
1
xxx1
xx11
x111
1111
xxx1
xx11
x111
1111
0
0
0
0
Table 11: Strength control truth table
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
59
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
The signals from the slew rate block connects to the strength control block, the input ports of the
block are enable port, Pslew ports, and Nslew ports. The output port is data_out.
In modeling of the strength control block, the enable port is the main port, which means it is an
“on”, “off” signal controller. In order for data_out to be transmitting logic ‘high’, the enable port
must have logic ‘high’ and at least one of the ports from Pslew must have logic ‘low’ and at least
one of the ports from Nslew must have logic ‘low’.
In order for data_out to be transmitted logic ‘low’, the enable port must have logic ‘high’ and at
least one of the ports from Pslew must have logic ‘high’ and at least one of the ports from Nslew
must have logic ‘high’.
But if in the condition, where one of the input ports has a high Z condition or if port enable has
logic ‘low’ condition, output ports will also have high Z condition.
The successful modeling of single block strength control is shown at the Figure 40.
Figure 40: Strength control block simulation screen shot
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
60
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Strength control top block
The strength control top block is the integration of the four individual strength control blocks
where the input enable ports controls the signal transmission to the data_out port.
The strength control top block is being modeled is such a way where if any one of the four blocks
has a logic ‘high’ the signal will transmit regardless of the logic condition of the other enable
ports.
The successful modeling of the integrated strength control top block, which consist of four strength
control blocks are shown at Figure 41.
At least one enable port must be
logic ‘high’ for output data to
transmit.
Figure 41: Strength control top block simulation screen shot
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
61
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Table 12 shows the comparison between the analog simulation and the behaviorally modeled
digital simulation of strength control when at least one of the enable ports is logic ‘high’.
Strength control at enable logic ‘high’
Here all of enable ports are logic
‘high’ and with at least one single
bit of Pslew or Nslew is logic
‘low’. The output data_out is logic
‘high’
Table 12: Strength control analog vs digital comparison
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
62
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Top module
The top module of the CMOS analog compensation circuit block is an integration of all the five
main blocks, which were they modeled individual in behavioral aspect and are verified, and are
compared with actual analog simulation. In the top module, the five main blocks were instantiated
and simulated with the top level test-bench.
The successful modeling of the CMOS analog compensation circuit block at top level simulation is
shown in Figure 42.
Figure 42: Top module simulation screen shot
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
63
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
Flowchart
The summary of modeling a CMOS analog compensation circuit block
Figure 43: Flowchart for modeling a CMOS analog compensation circuit block
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
64
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
8
CONCLUSION AND FUTURE WORK
In this project, the objective was to model a VLSI design (CMOS analog compensation circuit
block) in the behavioral aspect using Verilog HDL in Mentor graphic’s ModelSim simulator. This
chapter summarizes the conclusion, reflections and the future works on the further improvements
on this project.
8.1
CONCLUSION
The CMOS analog compensation circuit block is made up of five main blocks (delay chain, tristate, bias generator, slew rate and strength control) where each of the blocks was modeled
behaviorally and the simulation results were successfully verified. The digital simulation was
generated with Mentor Graphic’s ModelSim digital simulator whereas the analog circuit
simulation was carried out using Mentor Graphics’ Eldo simulator. With the digital simulation and
analog circuit simulations are being matched logically, the project objectives are met.
The main challenge of this project was to match the actual analog circuit simulation with the
digital simulation. With that being achieved, it is concluded that the CMOS analog compensation
circuit is successfully modeled using a digital simulator.
8.2
FUTURE WORK
In this project, there are some scopes for improvement. Though the simulation results are matched,
the analysis of the digital simulation compared to the analog simulation was only concluded based
on visual comparison.
The analog circuit simulations created by Mentor Graphics’s ADK Design Architect-IC which
gives an SPICE netlist is mainly for analog data accuracy checks. As such using the netlist for data
verification is a time consuming process especially if the verification for more complex circuits. A
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
65
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
free student version of Mentor Graphics’ ModelSim was used for this project to model the analog
circuit.
The commercial version of the software is designed to provide Verilog netlist for a rigorous
behavioral modeling of an analog circuit. This software gives a systematic analysis for digital and
analog circuit simulations. But this version could cost the school millions of dollars for the school.
If this software version is available, it would be an ideal way to further improve or to verify the
project details.
8.3
REFLECTION
By working on this project to achieve the main objectives, I have gained a lot of knowledge in
behavioral modeling using Verilog HDL and Mentor Graphic’s ModelSim simulator.
Being able to develop a behavioral model of analog complexity has enabled me to understand the
purpose of behavioral modeling and this project has given me an excellent opportunity and
invaluable experience about behavioral modeling.
Further more in doing this project, I have acquired the following:

Research of literature

Project management and planning

Verilog programming in behavioral modeling

Design and implementation

Testing and evaluation

Critical thinking and problem solving

Report writing and oral presentation.
I also wish to add that this project could be an effective guide for future students who wish to build
Verilog behavioral models for analog circuits.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
66
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
8.4
PROJECT MANAGEMENT
This project is well balanced in terms of time management and work. Other school assignments
were sufficiently planned from the very start. Verilog HDL was a totally new language to me. A
lot of time management was needed to learn this language. Furthermore, getting the learning
guidelines provided by the tutor was also very essential to me in narrowing my focus point in this
project.
8.5
VERILOG HDL PROGRAMMING
Verilog HDL programming compared to VHDL was much lesser complex. The understanding of
the coding was very much similar to C. Building up behavioral models using Verilog was
interesting concept as there are few ways in getting the results.
In the process of writing the codes and development test-bench were often found mismatches.
However by going through various Verilog books on the concepts of modeling, tutorial found on
web and key coding interpretation on the Verilog forum help me greatly resolving this problem.
Though learning Verilog could be a daunting task for beginners, it was a fruitful experience to
learn the language from the scratch. Getting the required results however though there are a lot of
Verilog HDL books and website are available but however, learning a complex programming
language like Verilog without a proper learning platform would be a difficult task. Student using
Verilog for modeling must build up a strong foundation to adopt the behavioral language in an
efficient way.
As a non-programmer in my current work and previous projects, the only way in getting started
was to study a few Verilog examples and using the similar approach in this project.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
67
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
8.6
WORK AND STUDY
Balancing the work and study is one of the major accomplishments in this project. Target setting
and meeting the time line successful was never an easy task. Constant effects were requirement for
the improvement and the development of this project. In the final stage of the project, I have
encountered enormous pressure and mental stress to juggle between project, study and work
commitment. However with a strong determination, advice from friends and tutor’s
encouragement, I have managed to clear the hurdles to achieve successful conclusion to this
project.
8.7
KEY LEARNING
In doing this project, I have learned and developed various skills, but most importantly the
challenge of learning Verilog programming had spurred my interest in going further on Verilog
programming. I have explored the development and implementations on how behavioral models
are created, their purpose and how its importance that makes a difference to analog and digital
designers.
In conclusion, this project provides me a fruitful practical experience to equip myself with better
understanding and knowledge of the subject matter. The most important part would be carrying
these developed skills in the professional career path of the real design world.
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
68
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
9
REQUIREMENT OF RESOURCES
The process of carrying out this project required the following:
1.
2.
Gathering of information

Internet resources like e-books

Books from National Library

Books from SIM Library
Usage of equipment

3.
A computer / laptop served as program writing and simulation
Software

MS Office 2007

ModelSim (Students Edition)

Mentor Graphics Design Architect
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
69
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
References:
1) http:// Analog Circuits and Systems ... - Goggle Books
2) http://en.wikipedia.org/wiki/Digital_electronics
3) http://www.mentor.com/products/fv/modelsim/
4) (ebook) Electronics - Verilog Digital Design Synthesis
by Samir Palnitkar
5) http://www.freepatentsonline.com
6) IEEE_Standard_verilog_std_1364_2001
7) http://www.verilog.net/docs.html
8) http://en.wikipedia.org/wiki/Analog_verification
9) Analog Circuits and Systems Optimization Based on Evolutionary Computation
http://books.google.com.sg/books?id=r_VfPhGq8wsC&printsec=frontcover&dq=Analog+Circuits+and+Syste
ms+Optimization+Based+on+Evolutionary+Computation&source=bl&ots=g21RzuLKCs&sig=C2zHEpDYFK
HtCCqDpexRkbNyVFk&hl=en&ei=TO0lTdulBMHxrQeI5PylDA&sa=X&oi=book_result&ct=result&resnum=9
&ved=0CFIQ6AEwCA#v=onepage&q&f=false
10) http://www.ee.iitb.ac.in/vlsi/resources/resource/simulator/Verilog-AMS%20Simulation.pdf
11) http://class.ee.iastate.edu/ee465/ee465s02/notes/billfuchs.pdf
12) Verilog HDL: a guide to digital design and synthesis, Volume 1
By Samir Palnitkar
13) http://en.wikipedia.org/wiki/Formal_equivalence_checking
14) http://en.wikipedia.org/wiki/Register_transfer_level
15) RTL Coding Styles That Yield Simulation and Synthesis Mismatches
By Don Mills & Clifford E. Cummings
16) http://en.wikipedia.org/wiki/Logic_synthesis
17) http://en.wikipedia.org/wiki/VHDL
18) http://en.wikipedia.org/wiki/Procedural_programming
19) http://en.wikipedia.org/wiki/Imperative_programming
20) http://en.wikipedia.org/wiki/Hardware_description_language
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
70
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
21) (ebook) RTL hardware design using VHDL: coding for efficiency, portability, and scalability
22) http://www.embeddedstar.com/press/content/2004/11/embedded17242.html
23) http://en.wikipedia.org/wiki/Hardware_description_language
24) http://chipdesignmag.com/display.php?articleId=117&issueId=11
25) ZEIDMAN consulting: Introduction to Verilog
26) http://www.xilinx.com/itp/xilinx4/data/docs/xst/verilog3.html
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
71
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
APPENDIX A: SOURCE CODES
//top module
`timescale 1ps/1ps
module top(del[2:0], data_in, tri_state, bias_gen, sr[2:0],
enable1, enable2, enable3, enable4, data_out);
input data_in;
input [2:0]del;
input tri_state;
input bias_gen;
input [2:0]sr;
input enable1;
input enable2;
input enable3;
input enable4;
output reg data_out;
delay del_block(del[2:0], data_in, data_delay);
tri_state_logic ha(tri_state, data_delay, data_up, data_dn);
slew_rate slew_rate1(sr[2:0], vn_bias, vp_bias, data_up, data_dn, p1, p2, p3, p4, n1, n2, n3, n4);
bias_gen_logic bias_gen1(bias_gen, vp_bias, vn_bias);
strength_control str_control1(enable1, p1, p2, p3, p4, n1, n2, n3, n4, data_out1);
strength_control str_control2(enable2, p1, p2, p3, p4, n1, n2, n3, n4, data_out2);
strength_control str_control3(enable3, p1, p2, p3, p4, n1, n2, n3, n4, data_out3);
strength_control str_control4(enable4, p1, p2, p3, p4, n1, n2, n3, n4, data_out4);
always @(data_out1, data_out2, data_out3, data_out4)
begin
if (data_out1 == 1'bx && data_out2 == 1'bx && data_out3 == 1'bx && data_out4 == 1'bx)
begin
data_out = 1'bx;
end
else if (data_out1 == 1'b1 || data_out2 == 1'b1 || data_out3 == 1'b1 || data_out4 == 1'b1)
begin
data_out = 1'b1;
end
else if (data_out1 == 1'b0 || data_out2 == 1'b0 || data_out3 == 1'b0 || data_out4 == 1'b0)
begin
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
72
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
data_out = 1'b0;
end
end
endmodule
//top testbench
`timescale 1ps/1ps
module top_tb;
reg data_in;
reg [2:0]del;
reg tri_state;
reg bias_gen;
reg [2:0]sr;
reg enable1;
reg enable2;
reg enable3;
reg enable4;
wire data_out;
top top1(del[2:0], data_in, tri_state, bias_gen, sr[2:0], enable1, enable2, enable3, enable4, data_out);
initial begin
data_in = 1'bx;
// delay input
#500
data_in = 1'b0;
tri_state = 1'b0;
bias_gen = 1'b1;
//delay input
//tristate input, to active low
//bias_gen to high
enable1 = 1'b1;
enable2 = 1'b0;
enable3 = 1'b0;
enable4 = 1'b1;
#1500
del = 3'b000;
sr = 3'b000;
data_in = 1'b1;
#1500 data_in = 1'b0;
// default on
// at bit 000
// at bit 000
#1500 del = 3'b001;
sr = 3'b001;
data_in = 1'b1;
#1500 data_in = 1'b0;
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
73
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
#1500 del = 3'b010;
sr = 3'b011;
data_in = 1'b1;
#1500 data_in = 1'b0;
#1500 del = 3'b011;
sr = 3'b111;
data_in = 1'b1;
#1500 data_in = 1'b0;
#1500
del = 3'b100;
data_in = 1'b1;
#1500 data_in = 1'b0;
#1500
del = 3'b101;
data_in = 1'b1;
#1500 data_in = 1'b0;
#1500
del = 3'b110;
data_in = 1'b1;
#1500 data_in = 1'b0;
#1500
del = 3'b111;
data_in = 1'b1;
#1500 data_in = 1'b0;
$monitor($time, ,"del= %b, data_in = %b, tri_state = %b, bias_gen = %b, sr = %b, enable1 = %b, enable2 =
%b, enable3 = %b, enable4 = %b, data_out = %b", del, data_in, tri_state, bias_gen, sr, enable1, enable2,
enable3, enable4, data_out);
end
endmodule
// Delay Module
`timescale 1ps/1ps
module delay(del[2:0], data_in, data_delay);
input data_in;
input [2:0] del;
output reg data_delay;
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
74
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
initial begin
data_delay = 1'b0;
end
always @(del, data_in)
begin
if (data_in == 1'bx || del[0] == 1'bx || del[1] == 1'bx || del[2] == 1'bx)
begin
data_delay = 1'bx;
end
else
begin
case (del)
3'b000:begin
#500 data_delay = data_in;
end
3'b001:begin
#600 data_delay = data_in;
end
3'b010:begin
#700 data_delay = data_in;
end
3'b011:begin
#800 data_delay = data_in;
end
// 2nd range of delay values
3'b100:begin
#750 data_delay = data_in;
end
3'b101:begin
#850 data_delay = data_in;
end
3'b110:begin
#950 data_delay = data_in;
end
3'b111: begin
#1050 data_delay = data_in;
end
endcase
end
end
endmodule
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
75
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
// Tri state module
`timescale 1ps/1ps
module tri_state_logic(tri_state, data_delay, data_up, data_dn);
input tri_state;
input data_delay;
output reg data_up;
output reg data_dn;
always @(tri_state, data_delay)
begin
if(tri_state == 1'bx || data_delay == 1'bx)
begin
data_up = 1'bx;
data_dn = 1'bx;
end
else if (tri_state == 1'b1)
begin
data_up = 1'b1;
data_dn = 1'b0;
end
else if (tri_state == 1'b0)
begin
case (data_delay)
1'b0:begin
data_up = 1'b0;
data_dn = 1'b0;
end
1'b1:begin
data_up = 1'b1;
data_dn = 1'b1;
end
endcase
end
end
endmodule
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
76
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
//Bias generator module
`timescale 1ns/1ps
module bias_gen_logic(bias_gen, vp_bias, vn_bias);
input bias_gen;
output reg vp_bias;
output reg vn_bias;
begin always @(bias_gen, vp_bias, vn_bias)
if(bias_gen == 1'bx)
begin
vp_bias = 1'bx;
vn_bias = 1'bx;
end
else if(bias_gen == 1)
begin
vp_bias = 0;
vn_bias = 1;
end
else if(bias_gen == 0)
begin
vp_bias = 1;
vn_bias = 0;
end
end
endmodule
// Slew rate module
`timescale 1ps/1ps
module slew_rate (sr[2:0], vn_bias, vp_bias, data_up, data_dn, p1, p2, p3, p4, n1, n2, n3, n4);
input [2:0] sr;
input vn_bias;
input vp_bias;
input data_up;
input data_dn;
output reg p1;
output reg p2;
output reg p3;
output reg p4;
output reg n1;
output reg n2;
output reg n3;
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
77
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
output reg n4;
always @(sr, vn_bias, vp_bias, data_up, data_dn)
begin
if (sr == 3'bxxx || vp_bias == 1'bx || vn_bias == 1'bx || data_up == 1'bx || data_dn ==1'bx)
begin
p1 = 1'bx;
p2 = 1'bx;
p3 = 1'bx;
p4 = 1'bx;
n1 = 1'bx;
n2 = 1'bx;
n3 = 1'bx;
n4 = 1'bx;
end
else if (vp_bias == 1'b1 && vn_bias == 1'b0)
begin
p1 = 1'b1;
p2 = 1'b1;
p3 = 1'b1;
p4 = 1'b1;
n1 = 1'b0;
n2 = 1'b0;
n3 = 1'b0;
n4 = 1'b0;
end
else if (vn_bias == 1'b1 && vp_bias == 1'b0 && data_up == 1'b0 && data_dn == 1'b0)
begin
case (sr)
3'b000:begin
p1 = 1'b1;
p2 = 1'b0;
p3 = 1'b0;
p4 = 1'b0;
n1 = 1'b1;
n2 = 1'b0;
n3 = 1'b0;
n4 = 1'b0;
end
3'b001:begin
p1 = 1'b1;
p2 = 1'b1;
p3 = 1'b0;
p4 = 1'b0;
n1 = 1'b1;
n2 = 1'b1;
n3 = 1'b0;
n4 = 1'b0;
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
78
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
end
3'b011:begin
p1 = 1'b1;
p2 = 1'b1;
p3 = 1'b1;
p4 = 1'b0;
n1 = 1'b1;
n2 = 1'b1;
n3 = 1'b1;
n4 = 1'b0;
end
3'b111:begin
p1 = 1'b1;
p2 = 1'b1;
p3 = 1'b1;
p4 = 1'b1;
n1 = 1'b1;
n2 = 1'b1;
n3 = 1'b1;
n4 = 1'b1;
end
endcase
end
//--------------------------------------------------------------------------------else if (vn_bias == 1'b1 && vp_bias == 1'b0 && data_up == 1'b1 && data_dn == 1'b1)
begin
case (sr)
3'b000:begin
p1 = 1'b0;
p2 = 1'b1;
p3 = 1'b1;
p4 = 1'b1;
n1 = 1'b0;
n2 = 1'b1;
n3 = 1'b1;
n4 = 1'b1;
end
3'b001:begin
p1 = 1'b0;
p2 = 1'b0;
p3 = 1'b1;
p4 = 1'b1;
n1 = 1'b0;
n2 = 1'b0;
n3 = 1'b1;
n4 = 1'b1;
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
79
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
end
3'b011:begin
p1 = 1'b0;
p2 = 1'b0;
p3 = 1'b0;
p4 = 1'b1;
n1 = 1'b0;
n2 = 1'b0;
n3 = 1'b0;
n4 = 1'b1;
end
3'b111:begin
p1 = 1'b0;
p2 = 1'b0;
p3 = 1'b0;
p4 = 1'b0;
n1 = 1'b0;
n2 = 1'b0;
n3 = 1'b0;
n4 = 1'b0;
end
endcase
end
end
endmodule
strength_control
`timescale 1ps/1ps
module strength_control (enable, p1, p2, p3, p4, n1, n2, n3, n4, data_out);
input enable;
input p1;
input p2;
input p3;
input p4;
input n1;
input n2;
input n3;
input n4;
output reg data_out;
always @(enable, p1, p2, p3, p4, n1, n2, n3, n4)
begin
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
80
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
if (enable == 1'bx || enable == 1'b0 || p1 == 1'bx || p2 == 1'bx || p3 == 1'bx || p4 == 1'bx ||
n1 == 1'bx || n2 == 1'bx || n3 == 1'bx || n4 == 1'bx)
begin
data_out = 1'bx;
end
//-----------------------------------------------else if (enable == 1'b1 && (p1== 1'b0 && n1== 1'b0))
begin
data_out = 1'b1;
end
else if (enable == 1'b1 && (p1== 1'b0 && p2 == 1'b0 &&
n1== 1'b0 && n2 == 1'b0))
begin
data_out = 1'b1;
end
else if (enable == 1'b1 && (p1== 1'b0 && p2 == 1'b0 && p3== 1'b0 &&
n1 == 1'b0 && n2 == 1'b0 && n3== 1'b0))
begin
data_out = 1'b1;
end
else if (enable == 1'b1 && (p1== 1'b0 && p2 == 1'b0 && p3== 1'b0 && p4 == 1'b0 &&
n1 == 1'b0 && n2 == 1'b0 && n3== 1'b0 && n4 == 1'b0))
begin
data_out = 1'b1;
end
//--------------------------------------------------------------else if (enable == 1'b1 && (p1== 1'b1 && n1== 1'b1))
begin
data_out = 1'b0;
end
else if (enable == 1'b1 && (p1== 1'b1 && p2 == 1'b1 &&
n1== 1'b1 && n2 == 1'b1))
begin
data_out = 1'b0;
end
else if (enable == 1'b1 && (p1== 1'b1 && p2 == 1'b1 && p3== 1'b1 &&
n1 == 1'b1 && n2 == 1'b1 && n3== 1'b1))
begin
data_out = 1'b0;
end
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
81
Verilog HDL modeling of CMOS Analog Circuit
Abdul Azeez (Q0805590)
_________________________________________________________________________________________________________
else if (enable == 1'b1 && (p1== 1'b1 && p2 == 1'b1 && p3== 1'b1 && p4 == 1'b1 &&
n1 == 1'b1 && n2 == 1'b1 && n3== 1'b1 && n4 == 1'b1))
begin
data_out = 1'b0;
end
end
endmodule
____________________________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
82