Multiple choice questions
23. One of the Reasons for Propagation Delay in Inverter is;
a. Resistance R of the Inverter
b. Inverter’s poor conductance
c. Transmission problem
d. The Capacitor Charge/Discharge before Output Change
24. When an Ideal Diode is ON;
a. V is low I is high
b. V is high I is low
c. V is zero I > zero
d. V is negative I is positive
25. When an Ideal Diode is OFF;
e. V is low I is high
f. V < zero I is zero
g. V is high I is low > zero
h. V is positive I is negative
26. In Thermal Equilibrium Recombination and Generation of Electrons and Holes;
a. Are Unknown
b. Recombination > Generation
c. Recombination < Generation
d. Are Equal
27. A BJT is Considered as Open Switch (or OFF) when;
a. Both Junctions are Forward Biased
b. EBJ is Forward and CBJ is Reverse
c. Both Junctions are Reverse Biased
d. EBJ is Reverse and CBJ is Forward
28. A BJT is considered as Closed Switch (or ON);
a. When Saturated
b. When Active
c. When Cutoff
d. When Forward Biased
29. Diode is;
a. Non-Linear Ckt Element
c. Simply a p-n junction
b. The Simplest and Most Fundamental Electronic Device
d. All of the a, b, and c
30. When no Gate Signal is applied to a MOSFET;
a. High R exist between Source and Drain and no current flows
b. Two Back-to-Back Diodes exist in Series between Drain and Source
c. Both a. and b.
d. A Channel is Created between Source and Drain
31. For a small value of VDS the channel in MOSFET is;
a. Not formed b. a linear resistor whose value is controlled by VGS.
c. Pinched off d. Enhanced
32.. Smallest Size Digital Logic Inverter is;
a. BJT Based
b. Diode Based
c. CMOS Based
d. Amplifier Based
Multiple choice questions
1.What is meant by VLSI
A device containing between 103 and 105 transistors.
A device containing between 105 and 107 transistors.
A device containing between 107 and 109 transistors.
A device containing between 109 and 1011 transistors.
Which 'law' describes the exponential growth of
integrated circuit complexity?
Moore's law.
Farday's law.
Nyquist's theorem.
Lenz's law.
Which of the following statements is incorrect?
RAM is volatile.
Dynamic RAM stores information by charging or discharging capacitors.
Static RAM stores information by energizing or de-energising inductors.
RAM is can be written and read quickly.
Which of the following statements is incorrect?
ROM devices must be programmed by the chip manufacturer.
EEPROMs can be written to (programmed) as well as read from.
Multiple choice questions
ROM devices are non-volatile.
EPROMs can be erased using an ultraviolet light source.
How many address lines would be found on a 128kbyte memory device (assuming that this is
arranged as an array of 8-bit registers)?
13
15
17
19
In the following PLA, which output implements
the logic function ABCD?
Multiple choice questions
X
Y
Z
The cells in a FPGA may contain registers, look-up
tables and memory.
True
False
Which of the following statements is incorrect?
Multiple choice questions
Some PLDs are programmed using electrically operated switches.
Some PLDs are programmed using mechanical switches.
Some PLDs are programmed using fuses that are selectively blown.
Some PLDs are programmed using anti-fuses that are selectively joined.
Communications within a microprocessor take
place over a number of serial buses.
True
False
What implementation method would be
appropriate for an application having a complexity
equivalent to about 20 standard logic gates?
A series of standard CMOS or TTL gate devices.
A simple PLD.
A complex PLD or FPGA.
A microprocessor.
A PLC.
11.The difference between a PLA and a PAL is:

1.

2.
the PLA has a programmable OR plane and a programmable AND plane, while
the PAL only has a programmable AND plane

3.
the PAL has a programmable OR plane and a programmable AND plane, while
the PLA only has a programmable AND plane
the PAL has more possible product terms than the PLA
Multiple choice questions

4.
PALs and PLAs are the same thing.
12. Question
Once a PAL has been programmed:

1.
its logic capacity is lost

2.
it cannot be reprogrammed.

3.
its outputs are only active LOWs

4.
its outputs are only active HIGHs
13. Question
The content of a simple programmable logic device (PLD) consists of:

1.
thousands of basic logic gates

2.
fuse-link arrays

3.
advanced sequential logic functions

4.
thousands of basic logic gates and advanced sequential logic functions
14. Question
The complex programmable logic device (CPLD) contains several PLD blocks
and:

1.
a language compiler

2.
AND/OR arrays

3.
field-programmable switches

4.
a global interconnection matrix
15. Question
Which type of PLD should be used to program basic logic functions?

1.
SLD
Multiple choice questions

2.
PAL

3.
PLA

4.
CPLD
16. Question
PLAs, CPLDs, and FPGAs are all which type of device?

1.
PLD

2.
SLD

3.
SRAM

4.
EPROM
17. Question
What input values will cause an AND logic gate to produce a HIGH output?

1.
All inputs are LOW.

2.
At least one input is LOW.

3.
All inputs are HIGH.

4.
At least one input is HIGH.
18. Question
The basic logic gate whose output is the complement of the input is the:

1.
OR gate

2.
AND gate

3.
INVERTER gate

4.
comparator
Multiple choice questions
19. Question
How many truth table entries are necessary for a four-input circuit?

1.
12

2.
8

3.
4

4.
16
20. Question
If a signal passing through a gate is inhibited by sending a low into one of the
inputs, and the output is HIGH, the gate is a(n):

1.
OR

2.
AND

3.
NAND

4.
NOR
21. Question
A +5 V PCB power source that has been “pulled down” to a +3.4 V level may be
due to:

1.
a circuit open

2.
a faulty regulator

3.
the half-split method

4.
a circuit short
22. Question
Measurement of pulse width should be taken at a 50% mean of the:

1.
damping and ringing

2.
overshoot and undershoot

3.
rise and fall
Multiple choice questions

4.
leading and trailing amplitude
33. Question
The time needed for a pulse to increase from 10% to 90% of its amplitude
defines:

1.
propagation delay

2.
pulse width

3.
rise time

4.
duty cycle
34) Chip utilization depends on ___.
a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads
35) In Soft blockages ____ cells are placed.
a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells
36) Why we have to remove scan chains before placement?
a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None
37) Delay between shortest path and longest path in the clock is called ____.
a. Useful skew
b. Local skew
c. Global skew
d. Slack
38) Cross talk can be avoided by ___.
a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets
39) Prerouting means routing of _____.
a. Clock nets
Multiple choice questions
b. Signal nets
c. IO nets
d. PG nets
40) Which of the following metal layer has Maximum resistance?
a. Metal1
b. Metal2
c. Metal3
d. Metal4
41) What is the goal of CTS?
a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack
42) Usually Hold is fixed ___.
a. Before Placement
b. After Placement
c. Before CTS
d. After CTS
43) To achieve better timing ____ cells are placed in the critical path.
a. HVT
b. LVT
c. RVT
d. SVT
44) Leakage power is inversely proportional to ___.
a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage
45) Filler cells are added ___.
a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing
46) Search and Repair is used for ___.
a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None
47) Maximum current density of a metal is available in ___.
a. .lib
b. .v
c. .tf
Multiple choice questions
d. .sdc
•
48) More IR drop is due to ___.
a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers
49) The minimum height and width a cell can occupy in the design is called as ___
a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell
50) CRPR stands for ___.
a. Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal
51) In OCV timing check, for setup time, ___.
a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths
52) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.
a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio
53) The Solution for Antenna effect is ___.
a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing
54) To avoid cross talk, the shielded net is usually connected to ___.
a. VDD
b. VSS
c. Both VDD and VSS
d. Clock
55) If the data is faster than the clock in Reg to Reg path ___ violation may come.
a. Setup
b. Hold
c. Both
d. None
56) Hold violations are preferred to fix ___.
Multiple choice questions
a. Before placement
b. After placement
c. Before CTS
d. After CTS
57) Which of the following is not present in SDC ___?
a. Max tran
b. Max cap
c. Max fanout
d. Max current density
58) Timing sanity check means (with respect to PD)___.
a. Checking timing of routed design with out net delays
b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays
59) Which of the following is having highest priority at final stage (post routed) of the design ___?
a. Setup violation
b. Hold violation
c. Skew
d. None
60) Which of the following is best suited for CTS?
a. CLKBUF
b. BUF
c. INV
d. CLKINV
61) Max voltage drop will be there at(with out macros) ___.
a. Left and Right sides
b. Bottom and Top sides
c. Middle
d. None
62) Which of the following is preferred while placing macros ___?
a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O
63) Routing congestion can be avoided by ___.
a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None
64) Pitch of the wire is ___.
a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing
Multiple choice questions
65) In Physical Design following step is not there ___.
a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS
66) In technology file if 7 metals are there then which metals you will use for power?
a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7
67) If metal6 and metal7 are used for the power in 7 metal layer process design then whichmetals you will use
for clock ?
a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7
68) In a reg to reg timing path Tclocktoq delay is 0.5ns andTCombo delay is5ns and Tsetup is 0.5ns then the clock
period should be ___.
a. 1ns
b. 3ns
c. 5ns
d. 6ns
69) Difference between Clock buff/inverters and normal buff/inverters is __.
a. Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to
normalbuff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to
Clockbuff/inverters.
70) Which configuration is more preferred duringfloorplaning ?
a. Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back
71) What is the effect of high drive strength buffer when added in long net ?
a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.
72) Delay of a cell depends on which factors ?
a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.
Multiple choice questions
73) After the final routing the violations in the design ___.
a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.
74) Utilisation of the chip after placement optimisation will be ___.
a. Constant
b. Decrease
c. Increase
d. None of the above
75) What is routing congestion in the design?
a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above
76) What are preroutes in your design?
a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.
77) Clock tree doesn't contain following cell ___.
a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above
78. The speed – power product of any MOS technology is measured in
a)KJ
b) MW-sec
c) PJ
d) Joules
79. For depletion mode MOSFET, threshold voltage
a) 0.2 VDD
b) -0.2 VDD
c) 0.8 VDD
d) -0.8 VDD
80. The technology which is characterized by high speed
a)CMOS
b) BICMOS
c) GaAs
d)ECL
81. L a t c h u p i n C M O S d e v i c e c a n b e a v o i d e d b y
A) Increasing temp
b) doping control
c) increasing the substrate resistance
Multiple choice questions
d)decreasing substrate doping level
Fill in the blanks:
82. Expansion of CVD is ___
83.______Electron_______________ lithography is preferred in submicron device dimension
84. The kinetics of thermal oxidation is modeled by ___deal andgroover___________________model.
85. The static power dissipation in CMOS technology is _____zero__________
86. In normal mode of operation in CMOS, substrate terminal of NMOS is connected to ____vss
_______ and substrate terminal of PMOS is connected to ___vdd
87. CMOS technology is high delay than ____bipolar_______________ Technology
88. The deficiency of MOS technology is ___limited load drivingcapacity_____________________
89. Under DEPLETION mode NMOS is ____ON____________state.
90. NMOS FET’s are ___faster_________than PMOS FET’s
91. Power dissipation in NMOS technology is ____high_______compared to CMOS technology.