Laboratory 3:
Low-pass FIR Filter Design
I. Introduction
In the present project, students are required to implement and simulate a low-pass FIR
filter using DSP Builder in the Simulink environment. The design has to be downloaded
to the FPGA device on the Stratix EP1S25 DSP development board to perform hardware
simulation and verification.
II. Theory
An FIR (Finite Impulse Response) filter, oppositely to IIR filters, has a finite response to
impulse signals, which is explained because it does not have feedback. This way, FIR
filters define a class of filter that has only zeros in the z-transform (the poles are in the
origin z=0).
In addition, FIR filters have other characteristics that become these filters very attractive
to many applications, such as linearity of phase, stability in the frequency response and
constant group delay.
Equation (1) describes an FIR filter of length K:
K 1
y[n]   ak x[ n  k ]
k 0
(1)
Where:
x and y represent the input and transformed data, respectively.
ak is the set of constant coefficients of the filter.
(K-1) is the order of the FIR filter.
An FIR filter can also be characterized by its number of taps (K), which is the order
incremented by one. The transfer function A(z) of the FIR filter is expressed as follows:
A( z ) 
Y ( z)
X ( z)
K 1
A( z )   ak z  k  a0  a1 z 1  ...  a( K 1) z  ( K 1)
k 0
(2)
Given equation (2), an FIR filter is also called an all-zero filter because the frequency
response is only determined by the zeros in the z-transform.
In general, FIR filters are preferred because of its linear phase characteristic and stability.
However, IIR filters can be used in applications that require sharp cut-off or narrow band
filters and where linear phase is not a requirement. That is because FIR filters require
much higher order implementations than IIR filters for a similar performance.
III. Background about DSP Builder and the Altera EP1S25 DSP development board
Capabilities of DSP Builder and Simulink were introduced with an example design in the
Tutorial: “A/D and D/A Conversion on Altera Stratix EP1S25 Development Board using
Simulink and DSP Builder” [1], which contain a design targeting the 12-bit 125MHz A/D
and 14-bit 165 MHz D/A converters onboard. For further information about the Stratix
EP1S25 DSP development board, the student is referred to [3] and [4].
Similarly to the previous lab design, the present project will include multirate capabilities
by using the PLL blocks in the Altera FPGA. The student is referred to Laboratory 1 [2]
for information about working with different sampling rates in the same circuit design.
IV. Requirements
For this laboratory, students are required to accomplish the next requirements:

Define the floating-point coefficients for a low-pass FIR filter with the next
specifications:
Direct-form FIR filter
Cut-off frequency:
Stop-band frequency:
Max. attenuation pass-band:
Min. attenuation stop-band:
0.1178 x FN
0.2958 x FN
3dB
97dB
Use fdatool from Matlab to design the filter under the previous specifications and
determine the number of coefficients. To open this tool, type ‘fdatool’ in the
Matlab command window. Set the Design Method of the FIR filter to Equiripple
and the Design Factor to 20. It is important to note that we are using normalized
frequency FN with a range from 0.0 to 1.0. The maximum value (1.0) corresponds
to the half of the sampling rate.

The coefficients of the designed filter using fdatool are in floating-point format.
You can plot very easily the frequency response of the filter by using one of the
available options in fdatool (Analysis>Magnitude Response). Check if the filter
requirements are fulfilled.

Export the coefficients from fdatool to the Matlab Workspace (File>Export…).
By default, coefficients are stored in the variable ‘Num’. Then, convert
coefficients to 16-bit fixed-point with the next command in Matlab:
Num1 = round (Num*2^16-1)

Check if the new fixed-point coefficients fulfill the filter specifications. File >
Import Filter from Workspace permits to analyze the fixed-point design. First,
select ‘Direct-Form FIR’ from the drop down menu in Filter Structure and then
type Num1 in the ‘Numerator’ field, which contains the 16-bit coefficients. In the
‘Units’ field, ‘Normalized (0 to 1)’ has to be select from the drop down menu
below Sampling Frequency. Then, click Import Filter, and now you can check the
frequency response of the fixed-point FIR filter. Analyze if it adjusts to the
requirements and compare it with the frequency response obtained from the
floating-point design.

Implement the direct-form FIR filter in Simulink (DSP Builder) using the 16-bit
fixed-point coefficients (stored in variable ‘Num1’) and the A/D and D/A
converters onboard. You can use the design given in the Tutorial [1] as a
template. The A/D converter must convert a sinusoidal signal to digital, filter it
and finally convert it back to analog through the D/A converter. Place a SignalTap
II node at the output of the filter to acquire the signal later (see Figure 1, Tutorial
[1]).
NOTE: filter symmetry property should be used for efficiency.

Simulate your filter in Simulink with different sinusoidal signals from 100KHz to
5MHz, observing at which frequencies the amplitude of the signal drops
significantly.

Introduce two additional sampling rates to your design: 2.5MHz and 10MHz,
similarly to Laboratory 1. Make two additional copies of the FIR filter working at
80MHz and make the necessary modifications to have them working at 2.5MHz
and 10MHz, respectively. A PLL and Tsamp blocks are required to modify the
sampling rate in these two additional circuits. At the output, use a Multiplexer and
two switches from SW3 onboard to select in real-time one out of the three FIR
filter outputs (default at 80MHz, 10MHz and 2.5MHz).
NOTE: the Down Sampling block would not be required since the FIR filter is not
combinatorial. Also, to simplify the complexity of the circuit, it is suggested to
use HDL Subsystem blocks from the Altera DSPBuilder library. Each of these
blocks would contain one of the three FIR filters working at different sampling
rates.

Simulate your filter in Simulink with different sinusoidal signals from 100KHz to
5MHz, observing at which frequencies the amplitude of the signal is attenuated
significantly. Observe the effects of the different sampling rates, and particularly,
observe the aliasing effect when working with the filter sampled at 2.5MHz.

Download your design to the Stratix EP1S25 DSP development board and test it
by using a signal generator and oscilloscope for the different sampling rate
options. Observe the effect of the different sampling rates, and again, observe the
aliasing effect when working with the circuit sampled at 2.5MHz.

Capture and analyze the data using SignalTap II Analysis. Show when the
amplitude of the signals drops significantly. Also, using the data acquired through
SignalTap II, show the frequency response using ‘fft’ command, choosing one
input signal frequency in pass-band and another in stop-band.
NOTE: you can use similar commands to those given in the Tutorial [1],
“Importing the data acquired from the board in Matlab workspace”, step2.

What happened if the bit-precision of the coefficients is fixed at 8 bits? Modify
your design by replacing 16-bit coefficients by 8-bit coefficients (convert your
floating-point coefficients to 8 bits), and observe the behavior. Acquire the data
through SignalTap II and show the frequency response using ‘fft’ command,
choosing one input signal frequency in pass-band and another in stop-band.
V. Submission
You must submit:
 The Simulink model (.mdl) developed using DSP Builder blocks with three FIR
filters working at three different sampling rates: 2.5, 10MHz and 80MHz,
respectively.
 A report describing the general procedure to accomplish the project
requirements, and answering questions regarding filtering and aliasing effects as
detailed in the requirements. The report must contain graphs showing the
filtered signals and frequency response using ‘fft’ command for different
sampling rates. Choose one input signal frequency in pass-band and another in
stop-band. Also, discuss and show the effects of reducing the coefficient
precision from 16 to 8 bits.
VI. References
[1] Tutorial: “A/D and D/A Conversion on Altera Stratix EP1S25 Development Board
using Simulink and DSP Builder”.
[2] Laboratory 1: Real-Time Implementation for Observing Quantization Effects
[3] DSP Builder User Guide, ver. 5.1.0,
c:\altera\61\DSPBuilder\Doc\ug_dspbuilder.pdf
Altera,
2005.
Local
copy
at:
[4] Stratix EP1S25 DSP Development Board Data Sheet, ver. 1.6, Altera, 2004. Available
online at: http://www.altera.com/literature/ds/ds_stratix_dsp-board-starter.pdf or local
copy at: c:\altera\61\kits\stratix_dsp_kit-v1.3.0\Docs\ds_stratix_dsp_bd.pdf
[5] DSP Development Kit Stratix & Stratix Professional Edition (Getting Started User
Guide),
ver.
1.3.0
rev.
1,
Altera,
2004.
Available
online
at:
http://www.altera.com/literature/ug/ug_stratix_dsp_kit.pdf
or
local
copy
at:
c:\altera\61\kits\stratix_dsp_kit-v1.3.0\Docs\ug_stratix_dsp_kit.pdf