EDA Vendor Support
This document describes the EDA environments that Actel
supports. This document also covers each of the
Actel-supported vendors. Within each vendor’s tool set the
features will be described that are supported by Actel. Also
listed are the software and computer requirements for
integrating Designer Series with the EDA front-end tools.
Actel’s Alliance Partners
Actel’s Alliance program was established to assist EDA
vendors in providing support for Actel FPGAs. The Alliance
program provides early technical information on new Actel
releases to all partners so they can offer timely support.
Table 1 lists the complete set of EDA vendors that support
the design of Actel FPGAs.
Table 1 • Alliance Program EDA Vendors
Company
Contact
Address
Acugen
J. W. Brooks (603) 881-8821
427-3 Amherst St., Suite 391, Nashua, NH 03063
Aldec
Stanley Hyduke (805) 499-6867
3525 Old Conejo Road, Suite 111
Newbury Park, CA 91320
Cadence
Itzhak Shapira (408) 944-7734
2655 Seely Road, Bldg. 6, San Jose, CA 95134
Compass
John Goldsworthy
(408) 383-4720 ext. 52931
1865 Lundy Ave., San Jose, CA 95131
Escalade
Mark Miller (408) 481-1300
2475 Augustine Dr., 2nd Floor, Santa Clara, CA 95054
Exemplar Logic
Mary Murphy (510) 337-3785
815 Atlantic Ave., Suite 105, Alameda, CA 94501-2274
Intergraph
Will Wong (415) 691-6447
381 East Evelyn Avenue, Mountain View, CA 94041
Isdata
Ralph Remme 49 721 751087
Daimlerstr. 51, Karlsruhe, D-76185, Germany
IST
Gabriele Saucier 33 76 574687
Europole, 4 Place Robert Schuman
38024 Grenoble Cedex 1, France
Logic Modeling
(Synopsys)
Marnie McCollow (503) 531-2412 19500 N.W. Gibbs Drive, Beaverton, OR 97006
Logical Devices
David Motarjemi (305) 974-0967
1201 N.W. 65th Place, Ft. Lauderdale, FL 33309
Mentor Graphics
Sam Picken (503) 685-1298
8005 S.W. Boeckman Road, Wilsonville, OR 97070-7777
Minc
Wayne Merrill (719) 590-1155
6755 Earl Drive, Colorado Springs, CO 80918
OrCAD
Troy Scott (503) 671-9500
9300 S.W. Nimbus, Beaverton, OR 97005
Quad Design
Hector Lai (805) 988-8250
1385 Del Norte Road, Camarillo, CA 93010
Simucad
John Williamson (415) 487-9700
32970 Alvarado-Niles Rd., Suite 744, Union City, CA 94587
Synario Design
Automation
Dave Kohlmeiyer (206) 867-6802
10525 Willows Road N.E., Redmond, WA 98073-9746
Synopsys
Lynn Fiance (415) 694-4289
700 East Middlefield Road, Mountain View, CA 94043
Synplicity
Alisa Yaffa (415) 961-4962
465 Fairchild Dr., Suite 115, Mountain View, CA 94043
Teradyne
Bill Loring (617) 422-2769
179 Lincoln St., M/S L50, Boston, MA 02111
Veda Design Automation
(formerly Genrad)
Rastgow Shale (408) 496-4518
2041 Mission College Blvd., Suite 259
Santa Clara, CA 95054
Viewlogic
Dave Orecchio (508) 480-0881
293 Boston Post Road, Marlboro, MA 01752
Zuken
Dwight Dagenais (408) 562-0177 3945 Freedom Circle, Suite 1100, Santa Clara, CA 95054
April 1996
© 1996 Actel Corporation
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2
Concept
Verilog, RapidSIM
Synergy
Leapfrog
Designer Series Development System
Concept
RapidSIM
ACTgen
Compile
ACTmap
Pin Editor
ChipEdit
Layout
Standard/DirectTime
DirectTime
Editor
Programmers
EDA Tools
Designer Series for Cadence Design Systems
Actel
Activator 2
DT Analyzer &
Back Annotation
Actel
Activator 2s
Data I/O
Programmers
Figure 1 • The Cadence EDA Environment
The Designer Series Development System for the Cadence
Design Systems environment (see Figure 1) allows FPGAs
with from 1,000 to 30,000 gates to be designed with Cadence’s
Concept (Logic Workbench) or Composer schematic capture
tools. Designer Series provides libraries that support the
design of ACT 1, the Integrator Series, and the Accelerator
Series families of FPGAs. In addition, Designer Series
provides ACTmap VHDL Synthesis (a complete VHDL
synthesis and logic optimization tool) and ACTgen Macro
Builder, which creates complex logic functions to match
user-specified parameters.
For Cadence, Designer Series supports the following
combinations of schematic capture and simulation:
• Composer and Verilog XL
• Concept and RapidSIM
• Concept and Verilog
These design flows allow schematics to be created using
Composer or Concept. Designer Series products include
netlisters that convert Composer or Concept schematics into
a netlist format that Designer Series can accept. The netlist is
2-18
then simulated with unit delays to verify the design
functionally before running place and route. After place and
route, actual module and net delays are backannotated to the
netlist for timing simulation. Actel’s DirectTime Analyzer is
used to perform static timing analysis on a design—
identifying critical path delays and performance deltas
relative to design specifications. Once the implementation
has met all timing requirements, the design can be
programmed into an FPGA.
Actel’s optional DirectTime Layout feature can be added to
the basic Designer Series Cadence interface. DirectTime
Layout supports specification-driven design. With DirectTime
Layout, the system clock frequency or delay constraints for
individual signals can be entered. After Actel’s standard
place-and-route algorithm is executed, the results are shown
in the DirectTime Analyzer. DirectTime Analyzer displays a
comparison between required versus actual delays.
DirectTime Layout can typically improve design performance
by an amount equivalent to the next fastest speed grade. It
makes performance-runtime trade-offs during placement and
routing to achieve the requested timing.
E D A V e n dor S upport
If the results of standard layout are substantially slower than
the required timing, more aggressive measures are needed.
The designer has the option of moving to a faster-speed-grade
FPGA or even to a faster family. DirectTime Analyzer makes
these decisions easy by clearly showing whether the target
performance is reached and showing the distance between
target and achieved when target is missed.
There are many high-level design solutions that support Actel
in the Cadence environment. Cadence’s Synergy and PIC
Designer products as well as Synopsys’s Design and FPGA
Compilers all work within the Cadence environment.
Synthesized blocks in any of these synthesis tools can be
combined with schematics to support mixed-level design
definition. Cadence provides Actel libraries for the PIC
Designer and Synergy synthesis products. Actel’s Synopsys
synthesis libraries can be added to the Designer Series
Development System to support Synopsys synthesis in the
Cadence environment. Actel also makes available Verilog and
VITAL VHDL libraries so that designs captured in these
languages can be simulated directly with Verilog XL or
Leapfrog.
The Designer Series Development System for Cadence
provides a tight link between Cadence’s suite of design
capture and analysis tools and Actel’s FPGA implementation
software. The integration of Designer Series with the
Cadence tools provides a design environment that delivers
high-performance, high-capacity FPGA solutions quickly.
Combining the Actel architecture with powerful
place-and-route software provides short turnaround time for
ECNs. Designer Series makes it easy to include custom logic
in any product.
Sun SPARC or HP 700
Hardware Requirements
2
• 64 MB RAM
• 125 MB DISK (executables), 5 MB DISK (per design)
• CD-ROM drive
Software Requirements
• Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or
later
• Version 9404 or later
2-19
Design Architect
QuickSim II
Designer Series Development System
Autologic
QuickVHDL
ACTgen
Compile
ACTmap
Pin Editor
ChipEdit
Layout
Standard/DirectTime
DirectTime
Editor
Programmers
EDA Tools
Designer Series for Mentor Graphics
Actel
Activator 2
DT Analyzer &
Back Annotation
Actel
Activator 2s
Data I/O
Programmers
Figure 2 • The Mentor Graphics EDA Environment
The Designer Series Development System for the Mentor
Graphics environment (see Figure 2) allows FPGAs with from
1,000 to 30,000 gates to be designed with Mentor Graphics’
Design Architect. Designer Series provides libraries that
support the design of ACT 1, the Integrator Series, and the
Accelerator Series families of FPGAs. In addition, Designer
Series provides ACTmap VHDL Synthesis (a complete VHDL
synthesis and logic optimization tool) and ACTgen Macro
Builder, which creates complex logic functions to match
user-specified parameters.
The design flow for Mentor Graphics allows schematics to be
entered using Design Architect. Designer Series products
include netlisters that convert Design Architect schematics
into EDIF, which Designer Series can accept. The netlist is
then simulated with unit delays to verify the design
functionally before running place and route. After place and
route, actual module and net delays can be backannotated to
the netlist for timing simulation. Actel’s DirectTime Analyzer
can be used to perform static timing analysis on a design—
identifying critical path delays and performance deltas
relative to design specifications. Once the implementation
has met all timing requirements, the design can be
programmed into an FPGA.
2-20
Actel’s optional DirectTime Layout feature can be added to
the basic Designer Series Mentor Graphics interface.
DirectTime Layout supports specification-driven design. With
DirectTime Layout, the system clock frequency and delay
constraints for individual signals can be entered. After Actel’s
standard place-and-route algorithm is executed, the results
are shown in DirectTime Analyzer. DirectTime Analyzer
displays a comparison between required versus actual delays.
DirectTime Layout can typically improve design performance
by an amount equivalent to the next fastest speed grade. It
makes performance-runtime trade-offs during placement and
routing to achieve the requested timing.
If the results of standard layout are substantially slower than
the required timing, more aggressive measures are needed.
The designer has the option of moving to a faster-speed-grade
FPGA or even to a faster family. DirectTime Analyzer makes
these decisions easy by clearly showing whether the target
performance is reached and showing the distance between
target and achieved when target is missed.
There are many high-level design solutions that support Actel
in the Mentor Graphics environment. Mentor Graphics’
Autologic and Autologic II products as well as Synopsys’s
Design and FPGA Compilers all work within the Mentor
E D A V e n dor S upport
Graphics environment. Synthesized blocks in any of these
synthesis tools can be combined with schematics to support
mixed-level design definition. Mentor Graphics provides the
Actel libraries for Autologic synthesis products. Actel’s
Synopsys synthesis libraries can be added to the Designer
Series Development System to support Synopsys synthesis in
the Mentor Graphics environment. Actel also makes available
Verilog and VITAL VHDL libraries so that designs captured in
these languages can be simulated directly with QuickSim or
QuickVHDL.
Sun SPARC or HP 700
The Designer Series Development System for Mentor
Graphics provides a tight link between the Mentor Graphics
suite of design capture and analysis tools and Actel’s FPGA
implementation software. The integration of Designer Series
with the Mentor Graphics tools provides a design
environment that delivers high-performance, high-capacity
FPGA solutions quickly. Combining the Actel architecture
with powerful place-and-route software provides short
turnaround time for ECNs. Designer Series makes it easy to
include custom logic in any product.
• Version 8.2_5 or later (A.1 recommended)
Hardware Requirements
• 64 MB RAM
• 125 MB DISK (executables), 5 MB DISK (per design)
• CD-ROM drive
Software Requirements
• Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or
later
2
2-21
PowerView
ViewDraw
ViewSim
ViewSyn
SpeedWave
Designer Series Development System
PRO Series
ACTgen
Compile
ACTmap
Pin Editor
ChipEdit
Layout
Standard/DirectTime
DirectTime
Editor
Programmers
EDA Tools
Designer Series for Viewlogic
Actel
Activator 2
PRO Capture
PRO Sim
DT Analyzer &
Back Annotation
Actel
Activator 2s
Data I/O
Programmers
Figure 3 • The Viewlogic EDA Environment
The Designer Series Development System for the Viewlogic
environment (see Figure 3) allows FPGAs with from 1,000 to
30,000 gates to be designed with Viewlogic’s Workview Office
or PowerView tools. Designer Series provides libraries that
support the design of ACT 1, the Integrator Series, and the
Accelerator Series families of FPGAs. In addition, Designer
Series provides ACTmap VHDL Synthesis (a complete VHDL
synthesis and logic optimization tool) and ACTgen Macro
Builder, which creates complex logic functions to match
user-specified parameters.
For Viewlogic, Designer Series supports the following
workstation-product combinations:
• 486 and Pentium PCs: Workview Office
• HP 700 and Sun workstations: PowerView
These design flows allow schematics to be created using
PowerView on the workstations or Workview Office on the PC.
The Designer Series products include netlisters that convert
PowerView or Workview Office schematics into an EDIF
netlist that Designer Series can accept. The netlist is then
simulated with unit delays to verify the design functionally
before running place and route. After place and route, actual
module and net delays are backannotated to the netlist for
2-22
timing simulation. Actel’s DirectTime Analyzer is used to
perform static timing analysis on a design—identifying
critical path delays and performance deltas relative to design
specifications. Once the implementation has met all timing
requirements, the design can be programmed into an FPGA.
Actel’s optional DirectTime Layout feature can be added to
the basic Designer Series Viewlogic interface. DirectTime
Layout supports specification-driven design. With DirectTime
Layout, the system clock frequency and delay constraints for
individual signals can be entered. After Actel’s standard
place-and-route algorithm is executed, the results are shown
in DirectTime Analyzer. DirectTime Analyzer displays a
comparison between required versus actual delays.
DirectTime Layout can typically improve design performance
by an amount equivalent to the next fastest speed grade. It
makes performance-runtime trade-offs during placement and
routing to achieve the requested timing.
If the results of standard layout are substantially slower than
the required timing, more aggressive measures are needed.
The designer has the option of moving to a faster-speed-grade
FPGA or even to a faster family. DirectTime Analyzer makes
these decisions easy by clearly showing whether the target
E D A V e n dor S upport
performance is reached and showing the distance between
target and achieved when target is missed.
There are many high-level design solutions that support Actel
in the Viewlogic environment. Viewlogic’s ViewSynthesis as
well as Synopsys’s Design and FPGA Compilers all work
within the Viewlogic environment. Synthesized blocks in any
of these synthesis tools can be combined with schematics to
support mixed-level design definition. Viewlogic provides
Actel libraries for the ViewSynthesis product. Actel’s
Synopsys synthesis libraries can be added to the Designer
Series Development System to support Synopsys synthesis in
the Viewlogic environments. Actel also makes available
Verilog and VITAL VHDL libraries so that designs captured in
these languages can be simulated directly with Chronologic
or Speedwave.
The Designer Series Development System for Viewlogic
provides a tight link between Viewlogic’s suite of design
capture and analysis tools and Actel’s FPGA implementation
software. The integration of Designer Series with the
Viewlogic tools provides a design environment that delivers
high-performance, high-capacity FPGA solutions quickly.
Combining the Actel architecture with powerful
place-and-route software provides short turnaround time for
ECNs. Designer Series makes it easy to include custom logic
in any product.
486 or Pentium PC
Hardware Requirements
• VGA, EGA graphics card
• 32 MB RAM
• 60 MB virtual disk
• 70 MB DISK (executables), 5 MB DISK (per design)
• CD-ROM drive
Software Requirements
• Windows 3.1 or later, Windows NT 3.5.1 or later,
Windows 95
2
• PROSeries 6.1 or later
• Workview Office 7.1 or later
Sun SPARC or HP 700
Hardware Requirements
• 64 MB RAM
• 125 MB DISK (executables), 5 MB DISK (per design)
• CD-ROM drive
Software Requirements
• Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or
later
• PowerView 5.3 or later
2-23
EDA Tools
Designer Series for Synopsys
Designer Series Development System
ACTgen
Compile
ACTmap
Pin Editor
ChipEdit
Layout
Standard/DirectTime
DirectTime
Editor
Programmers
Synopsys
Verilog HDL/VHDL
Synthesis
Actel
Activator 2
DT Analyzer &
Back Annotation
Actel
Activator 2s
Data I/O
Programmers
Figure 4 • The Synopsys EDA Environment
The Synopsys libraries support synthesis of Actel FPGAs from
Verilog HDL or VHDL. (See Figure 4.) Support for synthesis,
DesignWare, and VHDL System Simulator (VSS) is included.
The Synopsys libraries provide a complete top-down design
solution. Actel FPGA designs can be compiled with either the
Design Compiler or the FPGA Compiler, with the FPGA
Compiler yielding more efficient, high-performance FPGA
implementations.
The combination of Actel’s fine-grain, routing-resource-rich
architecture and Synopsys’s powerful synthesis program
delivers high-performance, high-capacity FPGAs. The
Synopsys libraries allow designs to be efficiently mapped to
the Actel architecture, taking complete advantage of all
possible logic module functions. Design implementation
efficiency is enhanced by the DesignWare library, which
contains Actel-optimized adders, counters, multiplexers,
registers, and so on. These logic elements all can be
instantiated into a high-level design description. Adders,
comparators, and subtracters can be inferred from arithmetic
operators that are used in the behavioral description.
Synopsys has included Actel-specific optimization, such as
sequential mapping, which takes full advantage of the
2-24
multiplexer-based, flip-flop-oriented FPGA architecture. The
combination of Synopsys’s optimizations for Actel FPGAs and
the optimized DesignWare logic elements generates designs
that are typically within 5 percent of what can be achieved by
laborious handcrafting.
Simulation of the design with its surrounding test bench can
be accomplished by using VSS and Actel’s VHDL libraries for
Synopsys or by using any Verilog simulator and the separately
available Verilog libraries. Both the Verilog and VHDL
simulation libraries support preroute functional simulation to
verify the design’s functionality and accurate postroute
timing simulation with backannotated (using SDF) actual
delays. Timing simulation can be performed with best-case,
worst-case, or typical delays to account for variations in
voltage, process, and temperature. This accurate timing
simulation can identify areas in which timing error is causing
a design to malfunction.
The Synopsys libraries support many of the FPGA-specific
architectural feature, such as ACT 3’s complex I/O cells,
1200XL’s wide-decode feature, and 3200DX’s quad-clock and
embedded RAM features. Synopsys’s support of architectural
specialties allows designers to maximize FPGA performance
E D A V e n dor S upport
and usefulness by synthesizing a design that includes
high-speed FIFOs or dual-port RAMs in a 32200DX device, or
by targeting the I/O flip-flops of the ACT 3 family to locate a
high-speed counter right on a data bus.
Sun SPARC or HP 700
The DesignWare libraries provide a strong advantage in the
design of Actel FPGAs. Actel provides a synthetic library in
DesignWare, which includes commonly used functions such
as accumulators, adders, comparators, counters, decoders,
multiplexers, and registers up to 32 bits wide. Each logic
function can be created with a designer-selected
combination of control signals. By taking advantage of the
synthetic library, the VHDL or Verilog code can be fine-tuned
for optimal Actel implementation. These libraries are based
upon Actel’s ACTgen Macro Builder parameterized macro
generator, which allows designers to achieve performance
comparable to schematic-drawn macros. DesignWare
elements can be instantiated into the code or inferred by the
compilers, resulting in an extremely efficient design process.
• 125 MB DISK (executables), 5 MB DISK (per design)
Hardware Requirements
• 64 MB RAM
• CD-ROM drive
Software Requirements
• Sun OS 4.1.3 or later, Solaris 5.3 or later, OR HP-UX 9.03 or
later
• Synopsys 3.2b or later
2
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