Microprocessors
2nd stage
24-1-2013
Lec.‫(ح‬11)
College of sciences for women ((())) Dept. of computer sciences
Year 2012-2013
14. RISC and CISC Designs
The two basic types of processor design philosophies: reduced instruction set computers
(RISC) and complex instruction set computers (CISC). First, let us talk about the trend line.
The current trend in processor design is to use RISC philosophy. In the 1970s and early
1980s, processors followed the CISC designs. To understand this shift from CISC to RISC,
we need to look at the motivation for going the CISC way initially. But first we have to
explain what these two types of design philosophies are.
For example, adding two integers is considered a simple instruction. But, an instruction
that copies an element from one array to another and automatically updates both array
subscripts is considered a complex instruction. RISC systems use only simple instructions
such as the addition. Furthermore, RISC systems assume that the required operands are
in the processor’s registers, not in main memory. A CISC processor does not impose such
restrictions. So what? It turns out that characteristics like simple instructions and restrictions
like register-based operands not only simplify the processor design but also result in a
processor that provides improved application performance.
How come the early designers did not think about the RISC way of designing
processors? Several factors contributed to the popularity of CISC in the 1970s. In those days,
memory was very expensive and small in capacity. For example, even in the mid-1970s, the
price of a small 16 KB memory was about $500. You can imagine the cost of memory in the
1950s and 1960s. So there was a need to minimize the amount of memory required to store a
program. An implication of this requirement is that each processor instruction must do more,
leading to complex instructions. This caused another problem. How can a processor be
designed that can execute such complex instructions using the technology of the day?
Complex instructions meant complex hardware, which was also expensive. This was a
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problem processor designers grappled with until Wilkes proposed microprogrammed control
in 1951.
A microprogram is a small run-time interpreter that takes the complex instruction
and generates a sequence of simple instructions that can be executed by hardware. Thus
the hardware need not be complex. Once it became possible to design such complex
processors by using microprogrammed control, designers went crazy and tried to close the
semantic gap between the instructions of the processor and high-level languages. This
semantic gap refers to the fact that each instruction in a high-level language specifies a lot
more work than an instruction in the machine language. Think of a while loop statement in a
high-level language such as C, for example. If we have a processor instruction with the while
loop semantics, we could just use one machine language instruction. Thus, most CISC
designs use microprogrammed control, as shown in Figure 21.
Figure 21 The ISA-level architecture can be implemented either directly
in hardware or through a microprogrammed control.
RISC designs, on the other hand, eliminate the microprogram layer and use the
hardware to directly execute instructions. Here is another reason why RISC processors can
potentially give improved performance. One advantage of using microprogrammed control
is that we can implement variations on the basic ISA architecture by simply modifying the
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microprogram; there is no need to change the underlying hardware, as shown in Figure 22.
Thus, it is possible to come up with cheaper versions as well as high-performance processors
for the same family.
Figure 22 Variations on the ISA-level architecture can be implemented by
changing the microprogram.
The Pentium processor, belongs to what is known as the complex instruction set
computer (CISC) design. The obvious reason for this classification is the “complex” nature of
its instruction set architecture (ISA). It is sufficient to know that the Pentium ISA provides a
lot of support for higher-level languages (HLLs) at the expense of increased instruction set
complexity. Two examples of complexity are the large number of addressing modes provided
and wide range of operations—from simple to complex—supported. The motivation for
designing such a complex instruction set is to provide an instruction set that closely supports
the operations and data structures used by HLLs.
The decision of CISC processor designers to provide a variety of addressing modes
leads to variable-length instructions. For example, instruction length increases if an operand
is in memory as opposed to in a register. This is because we have to specify the memory
address as part of instruction encoding, which takes many more bits. As we show later, this
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complicates instruction decoding and scheduling. The side effect of providing a wide range of
instruction types is that the number of clocks required to execute instructions also varies
widely. This again leads to problems in instruction scheduling and pipelining.
For these and other reasons, in the early 1980s designers started looking at simple ISAs.
Since these ISAs tend to produce instruction sets with far fewer instructions, they coined the
term reduced instruction set computer (RISC). Even though the main goal was not to reduce
the number of instructions, but the complexity.
Lecturer: Salah Mahdi Saleh
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