EE210: Switching Systems
Lecture 20: Shift Register & ASM Diagrams
Prof. YingLi Tian
Nov. 25, 2015
Department of Electrical Engineering
The City College of New York
The City University of New York (CUNY)
1
Shift Registers


A Shift register – is a set of flip flops such
that the data moves once place to the
right/left on each clock or shift input.
The flip flops can be SR, JK, or D.
http://en.wikipedia.org/wiki/Shift_register
2
Shift Input of Shift Register
Input shift to right
3
Shift Register: Adding NOT Gates for Loadreducing
Purpose of adding the NOT gate:
1. Reducing loads of the circuit from 4 to 1.
2. Changing the trigger edge from Trailing-edge to leading-edge.
Loads is not calculated based on the number of flip flops. It is based
on the electric current (amperes). For example, loads of a truck are
measured by weight, not the number of objects.
4
Adding NOT Gates for Load-reducing
Purpose of adding NOT gates:
1. Reducing loads of the circuit.
2. Changing the trigger edge type.
5
Serial-in, Serial-out shift register
Only 1 bit is loaded into the register at a time.
Load = 0, input (S1) = qn,
Load = 1, input (S1) = x.
6
Shift Register with Clear Input, Serial
in, and Parallel Outputs
Clear’– Active low
8-bit 74162 Shift Register with:
1. D flip flops
2. Clear input to initialize the output of each bit to 0.
3. Parallel outputs to get the contents of each flip flop.
7
Parallel-in Serial-out Shift Register
A parallel-in shift register allows the register to be loaded in one step!
Need: a) an input line for each flip flop; 2) a control line for load.
8
Parallel-in Serial-out Shift Register
Load’ = high (don’t load)
Enable’ = low (enable shift)
Then, we have:
PRE’ = high
CLR’ = high
Shift works.
Load’ = low (load)
Then, we have:
PRE’ = IN2’
CLR’ = IN2
IN2 is loaded into the flip
flop.
1
0
clo
1
9
Parallel-in Serial-out Shift Register
Load’ = high (don’t load)
Enable’ = low (enable shift)
Then, we have:
q1 is shifted into q2.
Shift works.
Load’ = low (load)
Enable’ = low (enable shift)
Then, we have:
IN2 is loaded into q2.
Enable’ = high (clock is disabled, nothing changes)
10
Right/Left Shift Registers
Don’t load,
don’t shift
Hold
1
1
Clock signal
is disabled.
0
1
0
0
1
11
Right/Left Shift Registers
Don’t load,
don’t shift
Shift left
S = q3
R = q3’
1
0
0
0
1
1
12
Right/Left Shift Registers
Don’t load,
don’t shift
Shift right
S = q1
R = q1’
1
0
0
1
0
1
q1
0
0
0
0
1
13
Right/Left Shift Registers
Don’t load,
don’t shift
Load
0
0
1
0
S = IN2
R = IN2’
IN2
0
0
1
1
0
0
IN2’
1
14
Practice: design system using
shift register

Using the following an 8-bit serial-in,
parallel-out shift register to design a system
with one output , z, which is 1 if the input,
x, has been alternating for seven clock
times (including the present).
15
Practice: design system using
shift register

Using the following an 8-bit serial-in, parallel-out
shift register to design a system with one output ,
z, which is 1 if the input, x, has been alternating
for seven clock times (including the present).
X
A
B
C
D
E
F
z
1010101
0101010
0010101
0001010
0000101
0000010
0000001
0000001
Case 1
X
A
B
C
D
E
F
z
0101010
0010101
0001010
0000101
0000010
0000001
0000000
0000001
Case 2
16
Practice:
1
1
1
0
1
0
1
0
1
17
Design Using ASM Diagrams

Algorithm State Machine (ASM) Diagram
is a tool combines a state diagram and a
flow chart.
Moore
18
ASM Diagram
The output z is 1 when the
system is in state A and the
input x is 1. The system
goes to state B when x=1,
and back to state A when
x=0.
19
Example of Moore state ASM Diagram
The output is 1 iff the input
has been 1 for at least 3
consecutive clocks.
20
Example of Mealy state ASM Diagram
a Mealy system
with one input x
and one output z
such that z = 1
iff x has been 1
for three
consecutive
clock times.
21
Announcement

Review Chapter 8.1, 8.4.
Next class: Design using Counters

Final Exam:




Time: Dec. 16, Wednesday, 1:00-3:15pm
Location: Shepard Hall, Room 75
Can bring 2-A4-Pages of notes
22