Solution for VHDL Lab-2
Solution for Lab Exercise-1:-
entity adder_e is
port(
a0,b0,a1,b1,a2,b2,a3,b3:in bit;
s0,s1,s2,s3:out bit;
ignore:out bit
);
end entity;
architecture adder_a of adder_e is
signal c0,c1,c2,c3,c4:bit;
signal nb0,nb1,nb2,nb3:bit;
begin
c0<='1';
nb0<=not b0;
s0<=a0 xor nb0 xor c0;
c1<=(a0 and nb0) or (c0 and (a0 xor nb0));
nb1<=not b1;
s1<=a1 xor nb1 xor c1;
c2<=(a1 and nb1) or (c1 and (a1 xor nb1));
nb2<=not b2;
s2<=a2 xor nb2 xor c2;
c3<=(a2 and nb2) or (c2 and (a2 xor nb2));
nb3<=not b3;
s3<=a3 xor nb3 xor c3;
c4<=(a3 and nb3) or (c3 and (a3 xor nb3));
ignore<=c4;
-- In subtraction remember to ignore the last carry.
end architecture;
Prepared By: Aws Yousif Al-Taie
Computer Science & Engineering Department
1
¾
Subtracting a = 0001 from b = 0010 will yield to sum = F (Explain and then justify your answer)
A = 0001
B = 0010
Addition: Sum = A + B
Subtraction: A – B Æ A + (-B) Æ A + B' + ‘1’
⇒ 1'S Compliment: Is the Process of inverting each bit of B
⇒ 2's Compliment: Is the process of adding binary I to B
1101
1110
Sum = 0001 + 1110 = 1111, Which is equivalent to Hexadecimal F
Solution for Lab Exercise-2:-
entity sub4 is
port (
a,b:in bit_vector(3 downto 0);
cin:in bit;
z:out bit;
v:out bit
);
end entity;
architecture behavior of sub4 is
signal c: bit_vector(4 downto 0);
signal nb,cout,sum: bit_vector(3 downto 0);
begin
Prepared By: Aws Yousif Al-Taie
Computer Science & Engineering Department
2
process(a,b,cin,nb,c)
begin
c(0)<=cin;
for i in 0 to 3
loop
nb(i)<=not b(i);
sum(i)<=a(i) xor nb(i) xor c(i);
c(i+1)<=(a(i) and nb(i)) or (c(i) and(a(i) xor nb(i)));
end loop;
cout<=c(4);
v<=cout;
z<=(not(sum(0) or sum(1) or sum(2) or sum(3)));
end process;
end behavior;
Prepared By: Aws Yousif Al-Taie
Computer Science & Engineering Department
3