EDITH COWAN UNIVERSITY
SCHOOL OF ENGINEERING & MATHEMATICS
THE BJT IN PRACTICE
• the BJT revolutionized the electronics industry (and human
society)
• however, the BJT suffers from some major drawbacks:
SCP2341 ELECTRONIC DEVICES
LECTURE 9
JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
Copyright  Dr S. Hinckley, ECU (1993-2001).
s.hinckley@cowan.edu.au
TEXT: B.G. Streetman & S. Banerjee (2000). Solid State Electronic
Devices. 5th Edition, Prentice-Hall, Chapter 6.
• the input is the forward biased base-emitter pn junction → low
input resistance & relatively large input power requirements
• the BJT is a minority carrier device → large capacitance delay
effects → slow switching speeds & low frequency operation
• to solve the input resistance problem, it is usual to place a
common-collector stage (with higher input resistance) in front of a
common-emitter stage (high gain)
• the switching speed problem can be improved using a Schottky
clamp
• the input power problem is difficult to solve
• another type of transistor (whose concept predates the BJT by
about 20 years) overcomes all these drawbacks
Note: This lecture material is provided exclusively for the use of students
enrolled in SCP2341 Electronic Devices. Some of the figures contained in this
material may have been obtained from other copyright material. The author
acknowledges the copyright of this imported material. Also, students using this
material are warned not to infringe any copyright legislation related to its use
and distribution.
2
THE FIELD-EFFECT TRANSISTOR
• remember our analogy of water flow through a pipe of fixed area –
the water flow was controlled by a tap that changed the area of the
pipe:
See figure from lecture 9
• in a FET, a voltage is applied perpendicular to the direction of flow
of current through the channel - the Gate Voltage (VG) varies the
conductivity of the channel by inducing or depleting charge within
the channel
• the Gate can be formed a number of different ways:
•
•
•
•
p-n junction
metal-semiconductor junction
metal-oxide-semiconductor junction
heterostructure
JFET
MESFET
MOSFET
MODFET or
HEMT
• since the bar is uniform, the potential sets up a uniform electric
field ξ along the length of the bar, i.e. ξ = VDS / l
• electrons move from one face (S ≡ source), through the bar (the
channel), towards the other face (D ≡ drain) under the influence of
the electric field ξ
• semiconductor resistivity is fixed by the doping density:
1
ρ=
qµ n N D
• resistance of bar is:
R = ρl A
• the current (ID) flowing through the bar is:
ID =
VDS
VDS A
R= l ⋅ρ
i.e. I D ∝ A
• therefore, if we plot ID vs VDS for different areas, we get:
• ?
See handout Fig 3.
Let us examine two simple phenomena that we have studied:
• the potential varies linearly along the bar (i.e. the channel):
Resistance of a uniform bar of semiconductor material
• consider a uniform bar of n-type semiconducting material of length
l and cross-sectional area A
See handout Fig 4.
⇒
channel resistance varies with changes in the effective crosssectional area of the channel
See handout Fig 2.
• a potential VDS is then applied across the faces of the bar (contacts
at these faces are assumed to be ohmic, i.e. low resistance and obey
Ohm’s Law)
3
4
PN junction behaviour under reverse bias
• under reverse bias, the junction potential is Vj = - Vreverse, so that
the barrier height under bias becomes VBi + Vreverse
• the total DL width of a p-n junction is given by:
W=
where ND
NA
VBi
Vj
εr
εo
and
q
• if the applied bias is large compared to the equilibrium barrier
height, then VBi + Vreverse ~ Vreverse
2ε r ε o  N D + N A 

 VBi − V j = Wn + W p
q  N D N A 
(
)
• under these special conditions, the DL width becomes:
is the donor concentration in the n-region
is the acceptor concentration in the p-region
is the equilibrium barrier height
is the external bias applied to the junction
is the dielectric constant of the semiconductor
is the permittivity of free space
is the electronic charge
W≈
• therefore, the DL width increases as Vreverse increases
• but I ~ - IS ~ 0 since the junction is reverse biased
• consider a p+-n junction:
⇒
very heavily doped p-side (NA >> ND)
⇒
1
ND + N A
≈
NDN A
ND
⇒
2ε r ε oVreverse
qN D
• this final condition is important - it indicates that in applying a
reverse bias to a p+-n junction, we will be able to vary the width of
the DL and the device will draw very little current
⇒
negligible DL width on p-side (Wp ~ 0 and W ~ Wn), and
all the DL appears in the least-doped side of the junction
(the n-side in this case)
2ε r ε o
VBi − V j
qN D
(
⇒
the DL width becomes: W ≈ Wn ≈
⇒
almost all the barrier height (VBi) on n-side
⇒
almost all the applied external bias (Vj) appears
across the DL on the n-side
• if the reverse-biased p+-n junction is the input of a device:
)
⇒
the effective input resistance of the device will be very
large (almost infinite)
⇒
the device will draw a very small current
⇒
the device will not load the output of any other circuit or
device to which it is connected
⇒
since charge is carried by majority carriers, there is no
minority carrier capacitance effects
5
6
• with no applied external bias in equilibrium, we have:
See handout Fig 5.
low power consumption
BIPOLAR DEVICES
Bipolar
⇒
operation determined by the flow of both carrier
types (i.e. minority and majority carriers)
BJT
⇒
⇒
Bipolar Junction Transistor
the current through two terminals (E and C) is
controlled by a current flowing through a third
terminal (B)
• if we apply a reverse bias laterally across the p-n junction:
See handout Fig 6.
• increasing Wn decreases the cross-sectional area (A) of the n-type
region
UNIPOLAR (FIELD-EFFECT) DEVICES
The two phenomena described above explain the operation of a device
that behaves similar to the BJT, but operates using the Field Effect:
• the conductance along the channel between Source and Drain is
modulated by the electric field (resulting from an applied Gate
voltage) applied normal to the direction of current flow:
Unipolar ⇒
⇒
FET
⇒
⇒
See handout Fig 7.
⇒
JFET⇒
⇒
⇒
MODFET ⇒
⇒
7
Field-Effect Transistor
current flowing through two terminals (S and D)
is controlled by a voltage at a third terminal (G)
called the Field Effect
Junction FET
⇒ control voltage varies the DL width of a reverse
biased pn junction
MESFET ⇒
⇒
IGFET
operation determined by the flow of only one
carrier type (majority carriers)
works on the Field Effect
Metal-Semconductor FET
replace pn junction with a Schottky barrier
Insulated-Gate FET
also called MOSFET (Metal-Oxide
Semiconductor FET) or MISFET (Metal
Insulator-Semiconductor FET)
Modulation-Doped FET - also called High
Electron Mobility Transistor (HEMT)
Quantum-Well device
8
The Field-Effect Transistor (FET)
• FET proposed ~ 20 years before the BJT – patented by Julius
Lilienfeld in 1926 (as a MESFET)
• JFET proposed by W. Shockley in 1952, first built by Dacey and
Ross in 1953
JUNCTION FET (JFET)
Structure
• can be n-channel FET or p-channel FET
• the structure of a modern epilayer n-channel JFET is:
• MOSFET invented in 1960, and commercially available 1964
• DRAM = Dynamic Random Access Memory - invented in late
1960’s by Dennard - one transistor dynamic memory cell:
See handout Fig 8.
• possible structure of a discrete n-channel JFET is:
See handout Fig 9.
DRAM
⇓
charge storage element (capacitor or p-n junction)
+
MOSFET as a switch
• CCD = Charge-Coupled Detector (early 1970’s) - MOSFET with a
segmented gate
• CMOS = Complimentary MOS (n-MOSFET + p-MOSFET) conceived in 1960’s; realised in 1980’s
• JFET's use reverse-biased pn junctions:
⇒
⇒
⇒
⇒
⇒
⇒
have very high input resistances (~ 100's MΩ)
input current negligible cf BJT
ideal voltage-controlled device
ideal for switching applications (digital circuits)
majority carrier devices, so there is no minority carrier
capacitance effects
FETs are much faster devices than BJTs
Principle of Operation
• majority carriers enter at the source (S), pass through the channel
(of length L) under the influence of the electric field due to the
applied drain potential VDS, and leave at the drain (D)
• the width of the channel is varied by the potential applied at the
gate (G)
• n-channel FET - electrons (e-) are the majority carriers
• p-channel FET - holes (h+) are majority carriers
• the resistance of the channel is R =
ρl
, and the current flowing
A
through the channel is:
ID =
VDS VDS A
=
⋅
R
l ρ
i. e. I D ∝ A
• the current flowing through the channel is controlled by varying
the effective area of the channel from S to D
9
10
JFET OUTPUT CHARACTERISTICS - QUALITATIVE
• we use the properties of a p+-n junction under reverse bias (as
reviewed earlier) to control the area of the channel by varying the
width of the DL layer of the p+-n junction
• output is ID vs VDS controlled by VG, but ID is a function of both
VDS and VGS
• this leads to the idealised device structure below:
• the source (S) is assumed to be grounded
See handout Fig 9.
• the effective resistance of the conducting channel between the two
p-n junctions is varied by the applied gate voltage, by reversebiasing the junctions and varying the width of their DL's
• the potential at any point x along the channel will depend on the
gate voltage VGS and the drain voltage VDS relative to the source (S)
at ground potential
• therefore, with both VDS and VGS applied, the potential in the
channel becomes a function of x
Circuit Symbols
• the normal circuit symbols for JFETs are:
See handout Fig 10.
• the direction of the arrow on the Gate indicates the polarity of the
FET (i.e. n-channel or p-channel) - the arrow points in the forward
direction of the gate-channel p-n junction
Case (a): VGS = 0
• first consider the case VGS = 0, i.e. with the gate short-circuited to
the source
• we will neglect the voltage drops between the S and D contacts and
the respective ends of the channel
Linear Region:
JFET Biasing Conditions
• it is usual to operate the JFET with the source (S) grounded
• if VDS ~ 0 (i.e. zero or small values), the DLs are essentially parallel
and have their approximate equilibrium values
• the normal bias conditions for an n-channel JFET are:
• the channel then acts as a variable resistance
See handout Fig 11.
• the normal bias conditions for a p-channel JFET are:
• the ID-VDS curve is then linear:
See handout Fig 13.
See handout Fig 12.
11
12
Non-Linear Region:
• as VDS increases, the potential along the channel V(x) changes
approximately linearly for a uniform channel
• as a result of this linearly varying potential, the DL widths become
asymmetric towards the drain end of the channel
⇒ this ensures that any carrier that reaches the front-end of the
pinch-off region is transported to the drain
⇒ there is no change in V(x) along the channel, and
⇒ ID remains constant
• therefore, the total ID-VDS characteristic for VGS = 0 is:
See handout Fig 17.
See handout Fig 14.
• since the channel is constricted, its resistance gradually increases,
so that the ID-VDS curve departs from linearity:
Case (b): VGS > 0
• what happens when we now increase VGS to more negative values
(i.e. - VGS)
See handout Fig 15.
⇒
⇒
⇒
⇒
⇒
⇒
Saturation or Pinch-Off:
• eventually, the DLs touch near the drain:
See handout Fig 16.
• this condition is called Pinch-Off, and the potential at which this
occurs is called the pinch-off voltage VP
• the drain current reaches a maximum value at the pinch-off
potential, and saturates
Beyond Saturation:
DLs are wider than for lower values of VGS
the channel width is smaller
resistance of channel is larger
lower current
pinch-off reached for lower VDS
same shape output characteristic as above
• therefore, the output characteristic is:
See handout Fig 18.
Case (c): VDS ~ 0 (i.e. VDS ~ 0 or very small)
• in this case, the DL are essentially parallel along the length of the
channel:
• any further increase in VDS beyond pinch-off:
⇒ only changes the potential across the pinch-off region
⇒ since its resistance is large, all the increase in VDS appears
across the pinch-off region
⇒ increases the electric field across the pinch-off region
See handout Fig 21.
• as VGS is made more negative, the DL will widen along the entire
length of the channel and will eventually touch
13
14
• the drain current ID reduces to practically zero, and VGS = VP, the
pinch-off voltage (+ve for n-channel JFET; -ve for p-channel
JFET)
Device Structure
• therefore, VP = value of VGS at which ID → 0, with the condition
|VGS| >> |VDS|
• consider an n-channel JFET, under standard operating (bias)
conditions:
OUTPUT CHARACTERISTIC - QUANTITATIVE
VGS ≤ 0
• when |VDS| > |VGS| (see above), the DL becomes asymmetrical,
since applying VDS induces a potential V(x) from S to D:
and
V DS ≥ 0
See handout Fig 20.
See handout Fig 4 and 14.
• the gate-drain potential is then VGD = VGS − VDS , and at pinchoff
VGD = VGS − VDS = VP
⇒
p+-n junctions always reverse-biased, or at zero bias
⇒
electron flow from S to D
Assumptions
TRANSFER CHARACTERISTIC
• gives output current IDS as a function of the input voltage VGS
• the y-axis is directed vertically down from the top gate, with origin
at the edge of the equilibrium DL width
See handout Fig 19.
• experimentally, the output current as a function of VGS is:
 V 
I DS = I DS ( sat ) 1 − GS 
VP 

• the x-axis is directed along the channel from S to D
2
• IDS(sat) is the saturated output current IDS when VGS = 0
• this is an experimental approximation that models the real currentvoltage characteristic above saturation quite well
• the z-direction is normal out of the page
• the length of the channel in the x-direction is L
• the width of the channel in the z-direction is Z
• the equilibrium height of the channel in the y-direction is 2a
• ignore the effect of the S and D electrodes, and the regions between
the edges of the G electrode and S/D electrodes ⇒ we have
reduced the problem to a simple 2-dimensional situation as shown:
Insert Figure 6-6 from Streetman.
15
16
• the p+-n junctions are step/abrupt junctions
How To Determine Drain Current
• the n-type channel is uniformly doped (ND) and all donors are
ionized
• below pinch-off (i.e. 0 ≤ VDS ≤ VDS(sat) and 0 ≥ VGS ≥ VP), we
determine ID from the total current density expression:
• the device is structurally symmetric about the centre of the channel
(i.e. about y = a)
J = qµ n nξ + qDn
dn
dx
• current flow is confined to the undepleted n-type region, and
directed exclusively in the x-direction along the channel
• within the channel, n ~ ND and the current is flowing almost
exclusively in the x-direction
• the p+-n junction DL width W(x) can be increased to pinch-off
without inducing breakdown in the p+-n junctions
• majority carriers ⇒ diffusion current density should be relatively
small ⇒ drift dominates in the channel:
• voltage drops from S at x = L to D at x = 0 are negligible
J = qµ n N D ξ = qµ n N D
• the channel length L >> channel half-width a
• carrier mobility µn is constant, even in the pinch-off region with
high electric fields
• the current flowing through any cross-sectional plane within the
channel must = ID (i.e. no carrier sinks or sources)
• the drain current is obtained by integrating J over the crosssectional area through which the current is passing:
Gradual-Channel Approximation
•
dV ( x, y )
dx
dξ( y )
dξ( x)
>>
⇒ the change in W(x) is only a function of the
dy
dx
voltage between the gate and the channel
I D = − ∫∫ J ⋅ dy ⋅ dz
• the differential volume element of neutral (undepleted) channel
material is Z2h(x)dx
• the resistance of this differential element is:
R=
dx
ρdx
=
2 Zh( x) 2 Zh( x)qµ n N D
• the total effective channel resistance is: R =
17
L
2 Zqµ n N D [a − W ( x)]
18
Pinch-Off Voltage
Channel Voltage and Depletion Layer Width
• we have already discussed the concept of pinch-off – the situation
where the p+-n junction DL extends across the entire channel
• the potential V(x) at any point in the channel depends on both VDS
and VGS
• the channel width along the channel depends on both VGS and VDS
• the applied voltage at any point x in the channel is given by:
V A = VGS − V (x)
• we can calculate the pinch-off voltage (VP) by considering what
happens at the drain end of the channel
• in this case, we are considering the gate-to-drain voltage:
VGD = VBi − VGS + VDS
• VGD is the potential of the drain relative to the gate, as a result of
VGS and VDS being applied
• usually, the equilibrium barrier height (VBi) of the p+-n junction is
negligible
• pinch-off occurs at the drain end (x = 0) of the channel when:
h( x = 0) = a − W ( x = 0)
i.e. when W ( x = 0) = a
• therefore, VP is the value of -VGD at pinch-off:
VP = VBi −
qa 2 N D
2ε o ε r
• VP is related to VDS and VGS by:
• V(x) is the voltage drop from point x in the channel to S
• the DL width for a p+-n junction is:
2ε r ε o
(VBi − V A )
qN D
W ≈ Wn =
• therefore, the DL width W(x) at any point x in the channel is:
W ( x) =
2ε r ε o
(VBi − VGS + V ( x) )
qN D
• in terms of the pinch-off voltage VP, this can be written as:
W ( x) = a
VBi − VGS + V ( x)
VBi − VP
• if VBi is negligible:
W ( x) = a
VP = −VGD ( pinch − off ) = VBi − VGS + VDS
− VGS + V ( x)
VP
• remember that VGS is negative for normal operation
19
20
Current (ID) vs Voltage (VDS & VGS) Characteristic
• let us now explicitly examine the output characteristic that will
come from the previous information
• we will consider a few specific regions of operation, before trying
to develop a general theory
2a
Z
L
W(x)
h(x)
=
=
=
=
=
equilibrium channel width in the x-direction
channel width in the z-direction
length of channel in the y-direction
DL width
W(x) – a = width of undepleted region (channel)
• the resistance of the channel is:
a) No Gate Voltage (VGS = 0)
R=
• if VGS = 0, then the only input variable is VDS
• since VGS = 0 and we assume that the voltage along the channel
does not vary (i.e. V(x) ~ 0), the p+-n junction DL width becomes:
W =
2ε r ε o
VBi
qN D
L
ρL
=
A qµ n N D 2Z [a − W ( x)]
• therefore, the drain current is (for VGS = 0 and small VDS):
ID =
VDS 2Zqµ n N D a  W 
=
1 − VDS
R
L
a

• we will now write this as:
• VDS = 0:
⇒ ID = 0 since there is no electric field to transport majority
carriers along the channel
• VDS > 0 (but only slightly increasing):
⇒ ID begins to flow into the D through the non-depleted nregion (the channel)
⇒ the channel behaves as a resistance for small VDS
⇒ ID(VDS) in linear
 W
I D = G0 1 − VDS where
a

G0 =
2 Zqµ n N D a
L
• G0 is the conductance of the n-type region if it were completely
undepleted (the “metallurgical channel”)
• the DL width W is constant along the channel
• the channel acts as a constant resistance, and the output current ID
varies linearly with the applied voltage VDS:
See handout Fig 22.
• to determine an explicit expression for ID, consider the device
structure as follows:
See handout Fig 21.
21
22
b) Negative Gate Voltage Applied (VGS < 0)
c) General Bias Conditions (VDS < VDS(sat) and VGS ≤ 0)
• p+-n junction DL extends further into the channel than for the VGS
= 0 case:
• we have studied the linear region above, i.e. where VDS is such that
the channel acts as a constant resistance
W≈
2ε r ε o
(VBi − VGS )
qN D
• what happens between the linear region and saturation?
• the channel (drain) current is:
• once again, for small VDS, W does not vary along the channel
ID = −
• put back into expression for ID:
ID
  V − V
GS
= G0 1 −  Bi
 VBi − VP
î
1/ 2 




VDS

• note that if VGS = 0 we obtain the previous ID expression of case (a)
• the above analyses for cases (a) and (b) (i.e. for VDS small and VGS
≤ 0) is for the linear region, i.e. ID is a linear function of VDS (only
applies for small VDS), so that the channel acts as a constant
resistance
• this condition requires that VDS << VBi – VGS (linear region)
• dV is the differential voltage drop in the dfiferential volume
element in the channel
• the minus sign indicates that V(x) decreases as x increases along the
channel (because we have defined the D as the origin and the S is
grounded)
• the quantity 2h(x) is the channel width at x:
 V − V + V ( x) 1 / 2 
GS
h( x) = a − W ( x) = a 1 −  Bi
 
VBi − VP

 
î
• the drain current then becomes:
Notes:
ID = −
• ID(max) occurs for VGS = 0
• we have ID(VGS < 0) ≤ ID(VGS = 0) always
1/ 2
2 Za  VBi − VGS + V ( x)   dV ( x)
1 − 


VBi − VP
ρ  
  dx
î
• separating dx and dV(x), we can rewrite the above as:
I D dx = −
23
2 Zh( x) dV
ρ
dx
1/ 2
2 Za  VBi − VGS + V ( x)  
1 − 
dV ( x)

VBi − VP
ρ  
 
î
24
• ID is obtained by integrating the above expression along the
channel from D [x = 0 & V(x) = VDS] to S [x = L & V(x) = 0]:
L
∫I
D dx
0
=−
2 Za
ρ
0
∫
VDS
 V − V + V ( x) 1 / 2 
Bi
GS
1 − 
 dV ( x)
VBi − VP

 
î
• since ID is independent of x, this integral is easy to solve, and we
obtain:
ID
3/ 2
3/ 2
 V
2 V − VGS + VDS 
2  VBi − VGS  
= G0VP  DS −  Bi
+


VBi − VP
3 VVBi − VP  

îVBi − VP 3 

⇒
for the general expression:
 2 V 1 / 2 
I D ≈ G0VDS 1 −  DS  
3  VP  
î

• hence, for VGS = 0, ID is reduced for the non-linear region (VDS
large) compared to the linear region (VDS small)
d) Beyond Saturation (VDS > VDS(sat))
• beyond pinchoff, the above epxressions do not give the correct
ID(VDS, VGS) behaviour
• that is: ID = f(VDS, VGS, VBi, L, Z, a, µn, ND)
• however, ID is approximately constant if VDS > VDS(sat)
• this represents the drain current up to the saturation (pinch-off)
condition
• we assume that:
• we want to know how ID varies with VDS for specific VGS
• therefore, the drain current beyond saturation becomes:
• as we have seen, qualitatively, an increase in VDS beyond the linear
region causes the DL width to increase along the channel, so that
the channel resistance decreases as a function of VDS
3/ 2
3/ 2

 V
 V − VGS   
+ V Bi − VGS 
2


 
−  Bi
I Dsat = G0 V Dsat − (V Bi − V P ) Dsat


3
V Bi − V P


 V Bi − V P   
î
• the characteristics then become non-linear, and ID eventually
reaches saturation at the pinch-off voltage
• since V Dsat = VGS − V P , we have:
• this behaviour is also predicted by the above expression for ID as a
function of VDS for specific VGS
I D (V DS > V DS ( sat )) ≡ I D (V DS = V DS ( sat )) ≡ I Dsat

 V − V
2

GS
I Dsat = G0 VGS − V P − (V Bi − V P )1 −  Bi
3
  V Bi − V P
î



3 / 2 


 

2
 V 
• experimentally, it is found that I DS = I DS ( sat ) 1 − GS  - since
 VP 
I DS ( sat ) = I Dsat (VGS = 0) and usually V Bi << VGS or V P , this is
the same result as that obtained theoretically
• for VGS = 0:
⇒ for the linear region:
ID = G0VDS
25
26
Note: Threshold or Turn-Off Voltage VT
Mutual Conductance gm
• if VGS is large enough so that it depletes the entire channel region,
IDS will become ideally zero
• in the saturation region, we can represent the device by an
equivalent circuit (we will look at this in depth later)
• this value of VGS is called the turn-off voltage VT
• changes in the drain current can be related to gate voltages changes
through the mutual conductance (often called the transconductance
= effect of input VGS of output IDS):
• VT is the value of VGS such that W = a:
1/ 2
 2ε ε

W = a =  o r (VBi − VT )
qN
î

D
with VGS = VT
∂I D
∂VGS
• the transconductance is a measure of the transistor gain – it
indicates the amount of control the gate vaoltage has on the drain
current
• therefore, VT is given by:
VT = VBi −
gm ≡
qN D a 2
4ε o ε r
• the linear region applies for small VDS, which means that there is
very little potential drop along the channel
• this means that the DL width is approximately constant along the
channel, and W is not a function of x
• the units of conductance are A/V, which are called Siemens (S) or
mhos (Ω-1)
• it is common to use the unit of transconductance per unit channel
width (gm/Z) as a figure of merit for FET devices
• the channel then acts as a simple resistance, with the value of the
resistance controlled by VGS:
1/ 2

 
V
1   2ε o ε r 
R = DS =
V
V
−
(
)

1 − 

Bi
GS
ID
G0   qN D a 2 
 
î
−1
• note that R increases as VGS increases
• the threshold voltage is a very important parameter in determining
FET operation
27
28
SMALL-SIGNAL EQUIVALENT CIRCUIT
• represents the operation of the FET as changes in the gate and drain
voltages are made about a d.c. operating point, on the
characteristic, which is determined by ID, VD, and VG
• these changes are initiated by υgs (a change in VGS), which causes
changes in ID and therefore VDS
• in general, we can write: iD = iD(υG, υD)
• each of the above variables is the sum of its d.c. value (at the
operating point) plus a small incremental change
• for example, for the drain current:
i D = I D + id = I D (VD + υ ds ,VG + υ gs )
• the incremental change in the drain current is then:
• using the above equation, we can draw the small-signal equivalent
circuit of the output (id) as:
See handout Fig 23.
• the above circuit does not include the relevant capacitances, so it is
valid only at low frequency
• since the input (the gate) is a reverse-biased p+-n junction, with
very high resistance and very small current flow, it can be
represented as an open circuit
• the output drain current depends on two components – one related
to the gate voltage (VGS) and one related to the drain voltage (VDS)
Channel Conductance (gd)
• the channel conductance is defined as the slope of the ID-VDS
characteristic at a certain value of VGS:
id = I D (VD + υ ds ,VG + υ gs ) − I D (VD ,VG )
• expanding the first term on the RHS using a Taylor series, and
subtracting the LHS term, we obtain:
id =
∂I D
∂I
υ gs + D υds + higher order terms
∂VG V
∂VD V
D
G
• neglecting the higher order terms: id = gmυ gs + gd υds
gd ≡
Transconductance (gm)
• relates the change in the drain current ID (output) to the change of
the gate voltage VGS (input) at constant drain voltage VDS:
gm ≡
∂I D
∂VGS
• the largest values of gm and gd are obtained when VGS = 0
30
1
L
L
=
R= ρ
2 Za / 2 qµ n ZaN D
• the charging time constant is then:
High-Frequency Equivalent Circuit
• to adapt the low-frequency circuit for high frequencies, we must
include any junction capacitances:
VDS = constant
• the transconductance is related to the channel transit time, which
determines the switching speed of the FET
29
• it is also a measure of the voltage gain of a JFET amplifier
VGS = constant
• in the saturation region, gd = 0 since the current is constant
• gm and gd are the transconductance and channel conductance
• this is a general method for determining the small-signal equivalent
circuit of a two-port network
∂I D
∂VDS
TC = RC g =
2ε o ε r L2
qµ n a 2 N D
• the limiting frequency for this time constant is:
See handout Fig 24.
fT =
• the capacitance is actually the gate-to-channel capacitance, but we
approximate it as the combination of two components:
Gate-to-Source Capacitance Cgs
Gate-to-Drain Capacitance Cds
qµ a 2 N D
1
= n
2πTC 4πεo ε r L2
• this is the frequency where the short-circuit current gain = 1; it is
called the cut-off frequency
• the limiting frequency can also be written in general terms as:
• the capacitances limit the high-frequency response
fT =
RC Time Constants
• the combination of the channel resistance and effective capacitance
creates an RC time constant that must be overcome in timedependent applications (switching and amplification)
• if we assume that we have only one gate (asymmetrical JFET), the
gate-to-channel capacitance Cg at the centre of the channel is:
2ε ε ZL
Cg = o r
a
• this capacitance then charges through half the channel resistance
(channel has length L and average area Za/2):
31
gm
2π C gs + C gd
(
)
Carrier Transit Time
• the carrier transit time down the channel (ttr) can be approximated
assuming a uniform channel electric field and constant carrier drift
velocity:
ttr =
L
L
L2
=
=
υd µ n ξ( x) µ nVDS
• the channel transit time is usually small compared to the RC time
constant
32
High-Frequency Limitations
• the high-frequency limit of operation depends on the dimensions
and physical constants of the transistor
• how do we improve the high-frequency response:
Channel Length L - decreasing L decreases Cg and increases gm –
this improves the gain-bandwidth product
Carrier Mobility - use semiconductors with high mobility
Channel Doping - as ND increases, the high-frequency response is
enhanced (as long as the channel conductivity is not too high)
SECONDARY EFFECTS
• there are a number of non-ideal or secondary effects that alter the
output characteristics of our device from those detailed above:
•
•
•
•
Channel-Length Modulation
Breakdown
Mobility Variation
Temperature Effects
• there are summarised in the text
• make sure you have a qualitative understanding of the effect of
secondary effects on the behaviour of the transistor
33