Atmel AT17A (1) series configurators use a simple serial-access procedure to configure one or more Field Programmable Gate Arrays (FPGAs) or Field Programmable System Level Integrated Circuits (FPSLIC ™ ) devices.
This application note provides circuits showing how to perform In-System Programming (ISP) on two cascaded AT17(A) devices, as well as how to use these devices to configure Atmel, Xilinx and Altera FPGAs.
The A2 input of cascaded configurators must be used as an address pin (set to logic level “0” for one configurator and logic level “1” for the other). Each configurator responds only to messages from the programming interface bearing its unique address.
The A2 pin of the AT17LVXXX and AT17LVXXXA series configurator has internal weak pull-down circuitry. However, the A2 pin of the AT17FXXX an AT17FXXXA series configurator has internal weak pull-up resistor. This default setting of the A2 pin requires the appropriate A2 bit level setting in the message of the programming software.
To enter programming mode, the SER_EN pin has to be set to logic Low. For in-system programming, this is accomplished by connecting the 10-pin ISP connector to the
ISP cable. Since pin 10 of the ISP cable is connected to GND, SER_EN is grounded automatically.
For drop-in/stand-alone programming, the SER_EN pin is set to logic Low by the programmer.
In configuration mode, the SER_EN pin has to be set to logic High. For In-system programming, this can be achieved by releasing the ISP cable to allow the external pullup resistor to pull the SER_EN pin to V
CC
(High). For stand-alone and drop-in programming, the SER_EN pin can be directly connected to V
CC
.
1.
AT17(A) = AT17/AT17A
AT17 = AT17LV/FXXX
AT17A = AT17LV/FXXXA
AT17NXXX series configurators should not be used in the cascaded circuits of this document.
Rev. 3034C–CNFG–05/2004
1

The In-System Programming (ISP) circuit diagrams are shown in Figures 1 through 4. Atmel ATDH2200E or ATDH2225 ISP
download cable is recommended to use for the ISP circuit. Refer to the ATDH2200E or ATDH2225 user guides, available on the Atmel web site, for the ISP programming procedure.
Figure 1. ISP of AT17LVXXXA Series Devices for Altera FPGA Applications, Internal Oscillator and Cascaded
Arrangement
1 k
Ω
V
CC
V
CC
1 k
Ω
DATA 1
SCLK 3
5
7
9
6
8
2
4
10
V
CC
V
CC V
CC
V
CC
GND
1 k
Ω
22
µ
F
GND
APEX II, EP20K, EP1K,
EPF10K, EPF6K
1 k
Ω nCONFIG
(3)
DATA0
DCLK nCE
MSEL0
CONF_DONE nSTATUS
MSEL1
1 k
Ω
AT17LVXXXA Series Device 1
DATA
(4)
SER_EN
DCLK nCS nCASC (A2)
(5)
RESET/OE
(1)
SER_EN
GND
V
CC
4.7 k
Ω
AT17LVXXXA Series Device 2
DATA SER_EN
DCLK nCS (5)
RESET/OE
(1)
READY
(2)
Notes: 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by ISP programmer.
2. Use of the READY pin is optional.
3. RC filter recommended for input to nCONFIG to delay configuration until V
CC
is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used.
4. The internal oscillator of the second cascaded configurator must be disabled by the programmer.
5. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to low for ISP access to Series
Device 1, and set to high for Series Device 2.
2
3034C–CNFG–05/2004

Figure 2. ISP of AT17FXXXA Series Devices for Altera FPGA Applications, Internal Oscillator and Cascaded Arrangement
V
CC
V
CC
1 k
Ω
1 k
Ω
DATA 1
SCLK 3
5
7
9
2
4
6
8
10
V
CC
V
CC V
CC
V
CC
GND
1 k
Ω
22
µ
F
GND
APEX II, EP20K, EP1K,
EPF10K, EPF6K
1 k
Ω nCONFIG
(2)
DATA0
DCLK
CONF_DONE nSTATUS nCE
MSEL0
MSEL1
1 k
Ω
AT17FXXXA Series Device 1
DATA
(4)
SER_EN
DCLK nCS nCASC (A2)
(3)
RESET/OE
SER_EN
GND
AT17FXXXA Series Device 2
DATA
RESET/OE
SER_EN
DCLK nCS (3)
READY
(1)
4.7 k
Ω
Note: 1. Use of the READY pin is optional.
2. RC filter recommended for input to nCONFIG to delay configuration until V
CC
is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used.
3. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to high for ISP access to
Series Device 1, and set to low for Series Device 2.
3
3034C–CNFG–05/2004

Figure 3. ISP of AT17LVXXX Series for Xilinx/Lattice
®
FPGA Applications, Cascaded Arrangement
V
CC
V
CC
4.7 k
Ω
4.7 k
Ω
DATA 1
SCLK 3
5
7
9
V
CC
4.7 k
Ω GND
PROGRAM
ORCA, VIRTEX-II, VIRTEX-E,
VIRTEX, SPARTAN, SPARTAN II,
XC5000, XC4000, XC3000
PROGRAM
(4)
M2
M1
DIN
CCLK
DONE
(3)
INIT
M0
AT17LVXXX Series Device 1
DATA SER_EN
CLK
CE
RESET/OE
(1)
CEO(A2)
(5)
V
CC
4.7 k
Ω
GND
AT17LVXXX Series Device 2
DATA SER_EN
CLK
CE
RESET/OE
CEO(A2)
(5)
(1)
READY
(2)
SER_EN
6
8
2
4
10
V
CC
Notes: 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by ISP programmer.
2. Use of the READY pin is optional.
3. A 330
Ω
external pull-up resistor on the DONE pin is required for Virtex ® and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin.
4. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA ® FPGAs can use PRGM instead of the PROGRAM pin.
5. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to low for ISP access to Series
Device 1, and set to high for Series Device 2.
4
3034C–CNFG–05/2004

Figure 4. ISP of AT17FXXX Series for Xilinx/Lattice
®
FPGA Applications, Cascaded Arrangement
V
CC
V
CC
4.7 k
Ω
4.7 k
Ω
DATA 1
SCLK 3
5
7
9
V
CC
4.7 k
Ω GND
PROGRAM
ORCA, VIRTEX-II, VIRTEX-E,
VIRTEX, SPARTAN, SPARTAN II,
XC5000, XC4000, XC3000
PROGRAM
(3)
M2
M1
DIN
CCLK
DONE
(2)
INIT
M0
AT17FXXX Series Device 1
DATA SER_EN
CLK
CE
RESET/OE
(1)
CEO(A2)
(4)
SER_EN
2
4
6
8
10
V
CC
GND
AT17FXXX Series Device 2
DATA SER_EN
CLK
CE
RESET/OE
CEO(A2)
(4)
READY
(1)
4.7 k
Ω
Notes: 1. Use of the READY pin is optional.
2. A 330
Ω
external pull-up resistor on the DONE pin is required for Virtex
®
and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin.
3. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA
®
FPGAs can use PRGM instead of the PROGRAM pin.
4. The A2 bit level setting in the Configurator Programming System (CPS) software must be set to high for ISP access to
Series Device 1, and set to low for Series Device 2.
5
3034C–CNFG–05/2004

The Drop-in/stand-alone programming circuit diagrams are displayed in Figure 5 and Figure 6. Atmel ATDH2200E pro-
gramming kit and many other third-party programmers can be used to program the configuration bitstream to the
EEPROMs, before the parts are placed into the drop-in/stand-alone programming circuits.
Figure 5. Drop-In Replacement of AT17A Devices for Altera FPGAs, Internal Oscillator and Cascaded Arrangement
V
CC V
CC
V
CC
CC
1 k
Ω
(2)
0.1
µ
F
GND
APEX II, EP20K, EP1K,
1 k
Ω
EPF10K, EPF6K
(2)
(3)
1 k
Ω
AT17A Series Device 1
(1)
CC
AT17A Series Device 2
(1)
Notes: 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by programmer if AT17LVXXXA series configurators are used.
2. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. nCONFIG can instead be connected to an active Low system reset signal. The capacitor is only recommended if slow or fast power up ramp rate of the power supply is used.
3. If AT17LVXXXA series configurators are used, the internal oscillator of the DCLK pin of the second configurator must be disabled to avoid clock contention.
6
3034C–CNFG–05/2004

Figure 6. Drop-In Replacement of AT17 Series Devices for Xilinx and Lattice Applications, Cascaded Arrangement
V
CC
PROGRAM
ORCA, VIRTEX-II, VIRTEX-E,
VIRTEX, SPARTAN, SPARTAN II,
XC5000, XC4000, XC3000
PROGRAM
(4)
M2
M1
DIN
CCLK
DONE
(2)
INIT
M0
4.7 k
Ω
AT17 Series Device 1
DATA
CLK
CE
RESET/OE
(1)
SER_EN
CEO/A2
V
CC
GND
AT17 Series Device 2
DATA
CLK
CE
RESET/OE
(1)
SER_EN
READY
(3)
Notes: 1. Reset polarity level of the configurator must be set to active Low (RESET/OE) by programmer if AT17LVXXX series configurators are used.
2. A 330
Ω
external pull-up resistor on the DONE pin is required for Virtex and Virtex-II FPGAs. Xilinx FPGAs can use LDC instead of the DONE pin.
3. Use of the READY pin is optional.
4. Xilinx FPGAs can use RESET instead of the PROGRAM pin. ORCA FPGAs can use PRGM instead of the PROGRAM pin.
7
3034C–CNFG–05/2004

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®
and combinations thereof, are the registered trademarks and FPSLIC
™
is the trademark of Atmel Corporation or its subsidiaries. Xilinx
®
, Spartan
®
and Virtex
®
are the registered trademarks of Xilinx, Inc.; Altera
®
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™
and APEX
™
II are the trademarks of Altera Corporation; Lattice
®
and ORCA
®
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