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Analog and Mixed-Signal Center Edgar Sánchez-Sinencio How to measure and/or compare wide-bands? iin gm fT = 2p (C gs + C gd ) + iout Vin ∼ or − Cg = port 1 gm w T port 2 An equivalent circuit of an MOS transistor as a two-port device. Cgd G D g mVin Cgs Cdb S (a) Hybrid- π Model D G gm wT g mVin S fT Simplified Model valid if Cdb << Cgs + Cgd Small-signal MOS transistor models. Reference J.M. Steinger, “Understanding Wide-Band MOS Transistors”, IEEE Circuits and Devices, pp. 26-31, May 1990. What Bandwidths are possible? Vdd Vdd Av M2 Av + + Vin M1 = − = − g g m1 (W / L)1 (W / L) Vin − − max Vout swing ≤ Vdd - VTn Vin − g m1 gm 2 wT wT g m1Vin M2 Vout − w + gm 2 wT g m 2Vout M1 Simple practical CMOS amplifier. Enhancement-mode inverter. + + + 2 Vout − bias M3 m2 Vout − p = w m2 T = gm1 gm2 Ao + 1 + g w T w T where | Ao |= gm1 / gm 2 f p / fT = 1 /(1+ Ao ) A small-signal equivalent circuit of the simple amplifier shown above based on the fT transistor model. To obtain an amplifier with the highest possible bandwidth a cascade of low-gain stages is desirable. How to optimize the cascade gain stages must be addressed. Scaled MOS and fT fT fT ↑ ↑ and/or Cg ↓ If Cg is only the parallel plate capacitance between the gate and channel, then ID fT Cg ≈ Cox WL Furthermore gm = fT vs. V on and ID. if g m Von dI d dVgs g m = m C ox W (Vgs − VT ) L and Von = Vgs − VT fT g m = m C ox W Von L then log I CC fT fT of a bipolar transistor vs. log ICC. = 1 gm 2p C g ≅ 1 2p m Von L2 To compare fT of MOS transistors from different technologies is by holding Von constant or by keeping the same current inversion level if. fT For Various Size Technologies 20 16 fT Von = Vgs − Vth 12 [Ghz] = 0.75 2.25 mm simple theory measured data 8 1.3m m 4 3 .0 m m 0 1 0 0.4 0.8 1.2 1.6 fT vs. Leff for various CMOS technologies Remarks 2 Leff [ 2 1 m 2 ] • Short-channel transistors operated at practical bias votlages do not behave as square-law devices. • tox < 500 Å produce high electric fields in the channel, both in the longitudinal and transverse directions. g m ↓ Vdrift ↓ • Simple theory neglects gate-to-drain overlap and assumes an optimistic Cg. Wide-Band CMOS Amplifiers Vdd M6 M5 M4 M3 M11 M12 1: a I1 aI1 out − in + M1 M2 out + in − abI 1 b :1 M9 M7 bias Mbias M8 M 10 Gnd Simple differential wideband amplifier. Av = Gm Ro ≅ Av = g m1 (W / L) 6 (W / L )9 g m11(W / L ) 3(W / L ) 7 ( g m1ab) / g m11 • Limited output swing • DC bias current and small signal are both amplified by the current mirrors. This might be solved by using interstage DC substractors. An alternative structure is next shown bias 2 MB4 bias 4 − MB 2 + I o− vo vin M7 M 11 bias M9 M1 MB M2 bias 3 MB1 bias1 MB3 • − vin Vo+ + Io • M3 M8 M4 M6 M5 M 10 • All current-mirrors are N-type (faster) • The output bias current is set by the current source (MB3 and MB4) • Optimal current-gain and matching are easier to obtain. M 12 Wide Output and Good Linearity Observations Gm = RL gm 1 + gm Rs vo vi Av gm = − Gm R L = = 1 1 + Rs gm −R L 1 + Rs gm Rs vi gm vo RL Rs N-driver Transconductor P-driver Transconductor • In order to make Av independent of gm, it is required that Rs >> 1/gm • Large Rs take up large area and have large parasitic capacitances which limit the amplifier bandwith. • It would be desirable to have Av independent of gm with small Rs Wide Output Swing and Improved Linearity Amplifier VDD Ib m Ib Ib m Ib Vx • 2 Rs m >> 1 VY id M2 RL + M3 M1 in + M4 in − RL − out + out − M7 M5 M6 M8 • • This circuit is capable to cancel the effect of gm1, gm4 • We need to force the DC components of Vx and VY to be equal, such that the current through 2RS is only a function of the differential input vin+ − vin− = vd , thus id becomes vd/2RS. • Condition to satisfy v gs1 + vgs 2 = v gs4 + vgs3 ⇒ Vx = VY Amplifiers with Wide Output Swing and Good Single-Ended Linearity A Circuit Implementation. Vdd bias Mb 4 Mb1 2 Rs Mb 2 Mb3 RL − RL + M2 M3 out − out + in + M7 M1 M4 M5 M6 in − Gnd Resistively loaded MOS amplifier with gm cancellation. Vgs1 + Vgs2 = Vgs3 + V gs4 i2 RS = (v in+ − v in− ) / 2 Rs = v d / 2 RS If I b1,b 4 << I b 2 ,b 3 then Av ≅ RL (W / L) 7 RS (W / L) 5 M8 A Bipolar Amplifier version is next shown. This Circuit is called Gilbert Gain Cell. x (I E + I B ) VCC (1 − x)( I E + I B ) RL+ − + vo • •vo I1 RL− Q1 Q1 I 3 = xIE Q1 I2 Q4 Q2 Q2 Q3 (1 − x) I B xI B Q3 IE xI B = I B 1 IE (1 − x) I B = I B 2 vin+ I2 IB 2 I4 = = I 3 I B 1 I1 I o1 = ( I1 + I 3 ) − ( I 2 + I 4 ) I I +I AI = o = B E I in IB − VEE Q5 RE Q6 RE vin− IB − VEE v Av = o vin = RL I (1 + E ) RE IB The dominant pole is placed at Reference w p = wT AI A.B. Grebene, “Bipolar and MOS Analog Integrated Circuit Design”, John Wiley & Sons, New York 1984. An alternative transconductor to handle the resistors is shown below. • Enhanced Gm • A single ended is shown here, but a differential version should be used. • Some applications allow input current in that case the input can be applied to the source of M1 Vb M2 . M5 vin M4 vo M1 M3 Reference.- J. Rijns., “ CMOS Low Distortion High-Frequency Variable-Gain Amplifier,” IEEE J. Solid-State Circuits, Vol. 31, No. 7, July 1996. Even without source degeneration, the voltage gain can be set by a ratio of resistors by using a bias current proportional to RL. Vdd biasp M4 M3 Vdd RL − RL + out + out − in + M1 M2 in − M5 M7 • M6 I bias biasn M8 M9 A MOSFET amplifier with Av=gm1,2RL . • Tapped resistive load • Simple output common-mode setting network • Vo ,CM = Vgs5 + Vgs7 • The bias current Ibias should be set such that gm1,m2 is a function of 1/Rb. Bias circuit for the previous amplifier that produces gm = 1 Rb Vdd g m1, 2 MB4 MB3 biasp 1 :1 Ib Ib biasn MB1 W 4 L W L Rb 1 / Rb Av = Av = + (4 K g m1, 2 RL I B )1/ 2 RL RL Rb bias M 1 and M 2 such that 1 g m1, 2 = Rb Av MB2 = = Gnd Vgs2 = Vgs1 + I b Rb , Vgs = Id K − VT Then Ib K Ib = Rb = 1 Ib + I b Rb 2 K 1 1 = 2 4 KRb 2 m C ox (W / L ) Rb2 = 1 gm = 1 2 m C o (W / L ) I b W W = = L B2 L 9 W L 1, 2 2 W W W = = L L L B 3, B 4 3 4 LV Transconductance Amplifier iR=vin/R VDD M5 M12 M6 M14 ix = - iR Vbias IB IB IB IB B M1 vin ib M3 R X ON A ix iR M13 M2 IB M8 Fig. 1 M4 M9 io+ M10 M11 VSS Min Supply voltage = Max{3VD SAT, VT+2VD SAT} OP io- i > max{ R} =(max{vin}-VA)/R v+ OP X Figure 1 ON Single-ended v- Amplifier Design Using Linear transconductor with Resistor Input”, IEEE Trans on Circuits and Systems-II, vol 47, pp776-778, August 2000 io- OP X Figure 1 ON Fig. 2 Refe.- E.K.F. Lee, “Low-Voltage OpAmp Design and Differential Difference io+ Pseudo Differential VDD Transimpedance amplifier Vbias CC vo io+ v+ Figure 2 io- v- R1 R1 VSS Voltage-Current-Voltage Amplifier io1+ v1+ v1- Figure 2 io2+ v2+ v2- io1- Figure 2 io2- Transimpedance amplifier vo Self-Biased CMOS Differential Amplifiers • Capable of supplying switching currents greater than the quiescent bias current. • Double differential mode gain (+6 dB) • Less sensitive of active-region biasing to variations in processing, temperature, and power supply. • Properties suitable for precision comparators. • A Transconductance for linear applications using double source degeneration is possible. CMOS Differential OP AMP Vb i a s P A2 ≅ − M3 Vin+ g M 1B g o1 + g o1 B VinM1A M1B Vb i a s P Vb i a s P M3 Vout M3 M1A Vin+ Vin+ Vin- Vout VH M1B Vin- Vb i a s Vout M2A VbiasN M2B Vin+ VL M2A Vout VbiasN M4 M2B M4 VinM3 & M4 OHMIC VbiasN M4 Ad ≅ − gM 2 B A1 ≅ − g o1 + g o 2B Application of CSDA (gM 1 + gM 2 ) g o1 + g o 2 B External TTL Input PAD Vo Vin - CSDA Vin+ Note: connect an additional capacitor at node Vb i a s to improve speed. V ref (midpoint of = 1.4V standard TTL input voltage) Is a source degeneration OTA developed using this architecture ? How can we make a transconductance amplifier with the combined P-N differential pairs? Ib Ib Rp Mp Mp - vin+ + Rn Rn Mn Ib Vo Vcm Vcm vin− Mn Ib • Increased effective transconductance • Rp and Rn can be implemented with transistors in ohmic region. • Vcm signal can be used for the CMFB • The differential output current is next iod vd = vin+ − vin− where g mn , p = 2 W m n , p Cox I B L n, p n = 1 − N n + 1 g m Vd + vd VDSAT 2( N n + 1) 2 g mp vd vd VDSAT 1 − N p 2(N p + 1) 2 1 2 1 2 A possible transistor level implementation is: VDD Vp 2 g mn Nn = b 3 (VGS3 − Vtn ) vin− 2 g mp Np = b 4 (VGS 4 − Vt p ) M4 Mp Vgp i cd vin+ - vo + Vgn M3 Mn M3 V cm Gm = Vn Ib Ib VSS gmp gmn Gm = + Nn + 1 N p + 1 HD3 d1, 2 = 1 = 32 2 2 vd VDSATp vd VDSAT d1 + N n + 1 N p + 1 g m n, p (N p,n + 1) g m n (N p + 1) + g m p ( N n + 1) ∂i ∂ vin vo = 0