APPLICATION NOTE
RZ/A1H Group
Multi-Function Timer Pulse Unit 2
R01AN1979EJ0100
Rev.1.00
Oct 16, 2015
Waveform Output by Using PWM Mode 1
Abstract
This application note describes how to output waveforms using PWM mode 1 of the RZ/A1H group Multi-function
timer pulse unit 2 (hereinafter called "MTU2").
Products
RZ/A1H
When using this application note with other Renesas MCUs, careful evaluation is recommended after making
modifications to comply with the alternate MCU.
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
Contents
1.
Specifications ..................................................................................................................................... 4
2.
Operation Confirmation Conditions .................................................................................................... 5
3.
Reference Application Notes .............................................................................................................. 5
4.
Peripheral Functions........................................................................................................................... 6
5.
Hardware ............................................................................................................................................ 7
5.1 Hardware Configuration ............................................................................................................... 7
5.2 Pins Used ..................................................................................................................................... 7
6.
Software ............................................................................................................................................. 8
6.1 Operation Overview ..................................................................................................................... 8
6.1.1 Setting Cycle and Duty ......................................................................................................... 9
6.1.2 Setting Values for Duty and Registers ................................................................................ 11
6.1.3 Cycle and Duty Setting for Interrupt Processing Generated by Compare Match ............... 16
6.1.4 Sample Operation 1 ............................................................................................................ 17
6.1.5 Sample Operation 2 ............................................................................................................ 19
6.2 Peripheral Function Settings and Memory Allocation Used in Sample Code ............................ 21
6.2.1 Peripheral Function Settings .............................................................................................. 21
6.2.2 Section Assignment of Sample Code ................................................................................. 22
6.3 Interrupts .................................................................................................................................... 25
6.4 Fixed-Width Integers .................................................................................................................. 25
6.5 Constants ................................................................................................................................... 26
6.6 Variables .................................................................................................................................... 27
6.7 Functions.................................................................................................................................... 28
6.8 Function Specifications .............................................................................................................. 29
6.9 Flowcharts .................................................................................................................................. 39
6.9.1 Main Function ..................................................................................................................... 39
6.9.2 Sample Code Main Function .............................................................................................. 40
6.9.3 Sample Main Function to Output Waveforms in PWM Mode 1 of MTU2 ........................... 41
6.9.4 Sample Function for PWM Waveform Output .................................................................... 42
6.9.5 Stop Function for PWM Waveform Output ......................................................................... 43
6.9.6 PORT Initial Setting Function ............................................................................................. 43
6.9.7 TGRA_4 Interrupt Sample Function ................................................................................... 44
6.9.8 TGRB_4 Interrupt Sample Function ................................................................................... 45
6.9.9 Converting Cycle and Duty into Register Setting Values ................................................... 46
6.9.10 MTU2 Initial Settings ......................................................................................................... 49
6.9.11 MTU2 Timer Count Start Function .................................................................................... 50
6.9.12 MTU2 Timer Count Stop Function ..................................................................................... 51
6.9.13 TGInA Interrupt Function ................................................................................................... 52
6.9.14 TGInB Interrupt Function ................................................................................................... 53
6.9.15 MTU2 Channel 4 Initial Settings ........................................................................................ 54
6.10 Running Sample Code ............................................................................................................... 57
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
7.
Notes ................................................................................................................................................ 58
7.1 Notes for Changing Cycle and Duty Setting Values .................................................................. 58
7.1.1 Specifying Duty Value......................................................................................................... 58
7.1.2 Time Calculated in Cycle and Duty Setting ........................................................................ 59
7.1.3 Differences between Cycle and Duty Setting Values and Output Waveforms ................... 61
7.1.4 TGRA_4 and TGRB_4 Interrupt Processing Time ............................................................. 63
8.
Sample Code .................................................................................................................................... 65
9.
Reference Documents ...................................................................................................................... 65
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
1.
Specifications
PWM waveforms are output by using the PWM mode 1 of MTU2.
In this application note, the interrupt controller, the general I/O port, the serial communication interface with FIFO, and
the power-down mode are abbreviated as INTC, PORT, SCIF, and STB respectively.
Table 1.1 lists the Peripheral Functions and Their Applications, and Figure 1.1 shows the Operation Overview.
Table 1.1 Peripheral Functions and Their Applications
Peripheral Function
MTU2
STB
PORT
INTC
SCIF
Application
Used to output PWM waveforms using the PWM mode 1 of the MTU2
channel 4.
Used to supply a clock to MTU2.
Used to switch the multiplexed pin of the MTU2 channel 4.
Used to control the MTU2 interrupts
Used for communication between the SCIF channel 2 and the host PC.
Terminal software
(message output and command input)
TIOC4A
Host PC
COMMAND>
R7S72100
R7S72100 CPU board
RTK772100BC00000BR
Serial interface
(RS-232C cable)
Figure 1.1 Operation Overview
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
2.
Operation Confirmation Conditions
The sample code accompanying this application note has been run and confirmed under the conditions below.
Table 2.1 Operation Confirmation Conditions
Item
MCU used
Operating frequency*
Contents
RZ/A1H
CPU clock (If): 400MHz
Image processing clock (Gf): 266.67MHz
Internal bus clock (Bf): 133.33MHz
Peripheral clock 1 (P1f): 66.67MHz
Peripheral clock 0 (P0f): 33.33MHz
Operating voltage
Power supply voltage (I/O): 3.3V
Power supply voltage (internal): 1.18V
®
Integrated development
ARM integrated development environment
TM
environment
ARM Development Studio 5 (DS-5 ) Version 5.16
C compiler
ARM C/C++ Compiler/Linker/Assembler Ver.5.03 [Build 102]
Compiler option (excluding addition of directory path)
-O3 -Ospace --cpu=Cortex-A9 --littleend --arm --apcs=/interwork
--no_unaligned_access --fpu=vfpv3_fp16 -g --asm
Operating mode
Boot mode 0
(CS0-space 16-bit booting)
Setting for communication with • Communication speed: 115200bps
terminal software
• Data length: 8 bits
• Parity: None
• Stop bit length: 1 bit
• Flow control: None
Board used
GENMAI board
• R7S72100 CPU board RTK772100BC00000BR
Device used
• NOR flash memory (Connected to CS0 and CS1 spaces)
(Functions used on the board)
Manufacturer: Spansion Inc., Product No.: S29GL512S10TFI01
• Serial inter face (D-sub 9-pin connector)
• LED1
Note: * Operating frequencies when clock mode 0 is used (13.33MHz clock input from EXTAL pin).
3.
Reference Application Notes
For additional information associated with this document, refer to the following application notes.
• RZ/A1H Group I/O definition header file <iodefine.h> (R01AN1860EJ)
• RZ/A1H Group Example of Initialization (R01AN1864EJ)
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Waveform Output by Using PWM Mode 1
4.
Peripheral Functions
This chapter provides supplementary information about MTU2. The basic information is described in "RZ/A1H group
User's Manual: Hardware"
Buffer operation can be specified when the MTU2 channel 0, 3, or 4 is selected. In this sample code, PWM outputs are
output using the buffer operation when a compare match occurs by transferring the buffer register value to the timer
general register (TGR). The MTU2 channel 4 is used in this sample code. Channels other than 0, 3, and 4 cannot be
used to output PWM waveforms when this sample code is customized to perform MTU2.
The selectable count clock in MTU2 differs depending on the channel used. The count clock on channel 0 can be set at
P0f/1, P0f/4, P0f/16, or P0f/64, and on channel 3 and 4, P0f/1, P0f/4, P0f/16, P0f/64, P0f/256, or P0f/1024 can be
specified for the count clock. In this sample code, the external clocks (TCLKA, CLKB, TCLKC, and TCLKD) cannot
be specified as the count clock.
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
5.
5.1
Hardware
Hardware Configuration
Figure 5.1 shows a Configuration Example to confirm the PWM waveform output using MTU2 on the RZ/A1H. The
waveforms are output from the TIOC4A pin in this sample code.
RZ/A1H
Connector
(CN6)
P4_4/TIOC4A
Output from pin No.28
28
Figure 5.1 Configuration Example
5.2
Pins Used
Table 5.1 lists the Pins Used and Their Functions.
Table 5.1 Pins Used and Their Functions
Pin Name
A25 to A1
D15 to D0
CS0#
I/O
Output
Input/output
Output
Function
Output address signals to the NOR flash memory
Input/output data signals to the NOR flash memory
Outputs device select signal to the NOR flash memory connected to
the CS0 space
RD#
Outputs read control signal to the NOR flash memory
Output
WE0#
Outputs write enable control signal to the NOR flash memory
Output
MD_BOOT1
Selects boot mode
Input
MD_BOOT1: "L", MD_BOOT0: "L" (Set to boot mode 0)
MD_BOOT0
Input
P4_10
Turns LED on/off
Output
RxD2
Serial receive data signal
Input
TxD2
Serial transmit data signal
Output
TIOC4A
Outputs PWM waveform signal from MTU2 channel 4
Output
Note: The symbol # indicates negative logic (or active low).
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
6.
Software
6.1
Operation Overview
The peripheral functions (MTU2, PORT, STB, and INTC) are initialized to output PWM waveforms by using MTU2.
The cycle and duty of waveforms are changed by the buffer operation and the interrupt processing generated by
compare match. The MTU2 channel 4 is set to PWM mode 1 to output PWM waveforms from the TIOCA4 pin using
the count clock at P0f/64. In this application note, the duty is considered as the percentage of high width for one cycle.
This sample code provides two types of PWM waveform output processing, which have different output levels at
TGRA_4 compare match and TGRB_4 compare match (sample operation1 and sample operation2).
The waveforms shown in Figure 6.1 are continuously output by changing the cycle and duty every cycle in the order
from phase (1) to (6) as indicated in Table 6.1. In this sample code, cycle and duty can be specified in 2µs unit and in %
respectively.
In sample operation1, the initial output level of output pin is set to "0", and the output levels at TGRA_4 compare match
and TGRB_4 compare match are respectively set to "0" and "1". In sample operation 2, the initial output level of output
pin is set to "1", and the output levels at TGRA_4 compare match and TGRB_4 compare match are respectively set to
"1" and "0".
Table 6.1 Cycle and Duty of Sample Code
Phase of Waveform
Cycle (µs)
(1)
(2)
(3)
(4)
(5)
(6)
10000
12000
14000
16000
8000
4000
Duty (%)
Sample operation 1
Sample operation 2
70
30
10
90
0
100
40
60
100
0
100
0
(1) Output waveform when Sample operation 1 is selected
[1]
[2]
[3]
[4]
[5]
[6]
Duty (%)
70%
10%
0%
40%
100%
100%
4000μs
Cycle (μs)
10000μs
12000μs
14000μs
16000μs
8000μs
[3]
[4]
[5]
[6]
0%
0%
8000μs
4000μs
(2) Output waveform when Sample operation 2 is selected
[1]
[2]
Duty (%)
30%
90%
100%
60%
Cycle (μs)
10000μs
12000μs
14000μs
16000μs
Figure 6.1 Output Waveform of Sample Code
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
6.1.1
Setting Cycle and Duty
This section describes about setting cycle and duty in the sample code.
TGRA_4 and TGRB_4 registers are configured for compare match function, and the initial output level and the output
level at compare match are specified. TCNT_4 is set to be cleared by TGRA_4 compare match. In this setting, the value
specified for TGRA_4 is used as cycle and the one specified for TGRB_4 is used as duty as shown in Figure 6.2.
TCNT_4 value
Counter is cleared by TGRA_4 compare match
TGRA_4
TGRB_4
H'0000
Time
TIOC4A
Duty
Duty
Duty
Cycle
Cycle
Cycle
Figure 6.2 PWM Mode Operation Example using MTU2
In this sample code, the duty is considered as High width for one cycle, therefor, the calculation for the value set in
TGRB_4 using the cycle and duty information differs in sample operation 1 and 2. Figure 6.3 shows the Relationship
between Cycle and Duty and Register Setting Values.
(1) Cycle and duty in sample operation 1
Current cycle
Next cycle
Duty
Duty
Setting value of
TGRB_4 register
Setting value of TGRA_4 register
(2) Cycle and duty in sample operation 2
Current cycle
Duty
Next cycle
Duty
Setting value of
TGRB_4 register
Setting value of TGRA_4 register
Figure 6.3 Relationship between Cycle and Duty and Register Setting Values
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
By setting MTU2 in buffer operation, TGRC_4 and TGRD_4 are used as buffer registers so that the values specified for
TGRC_4 and TGRD_4 can be respectively transferred to TGRA_4 and TGRB_4 at TGRA_4 compare match. When the
next cycle is set to TGRC_4 and the next duty to TGRD_4 for the use of buffer operation, the setting values can be
changed automatically for PWM waveforms after the cycle of the current PWM waveform output ends.
In this sample code, the values of the cycle and duty for TGRC_4 and TGRD_4 are set by using the interrupt processing
executed when TGRA_4 compare match occurs.
In the sample code, the setting tables for cycle and duty (mtu2_pwm_usertbl1[][] in sample operation1, and
mtu2_pwm_usertbl2[][] in sample operation2) are provided. In reference to the relationship shown in Figure 6.3, the
values of cycle and duty in the setting table are converted into the setting values of TGRA_4 and TGRB_4 registers,
and the values are stored in the setting table for these registers (mtu2_pwm_regtbl[][]).
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Waveform Output by Using PWM Mode 1
6.1.2
Setting Values for Duty and Registers
This section describes the setting values for duty and registers.
When the information of cycle and duty setting table is converted into the values to be stored in the setting table for
TGRA_4 and TGRB_4 registers, if the duty is in the range between 1 and 99%, the duty (%) is calculated by reference
to the relationship shown in Figure 6.3 in the preceding section. On the other hand, to output waveforms with duty of
0% and 100%, the output level should be set to avoid a change during one cycle interval. In the operation of MTU2
PWM mode, TGRB_4 compare match does not occur when the value of duty register (TGRB_4) is larger than the one
of cycle register (TGRA_4).
TCNT_4 value
TCNT_4 value
TGRB_4
TGRB_4
TGRA_4
TGRA_4
Time
H'0000
Time
H'0000
(1) Sample operation 1
• Waveform in duty 100%
• Waveform in duty 0%
TIOC4A
TGRB_4
compare match
does not occur
Duty 0%
Current cycle
TGRB_4
compare match
does not occur
Level "0" is continuously
output by TGRA_4
compare match
Next cycle
Duty 100%
Current cycle
Level "0" is output
by TGRA_4
compare match
Next cycle
(2) Sample operation 2
• Waveform in duty 0%
• Waveform in duty 100%
TIOC4A
TGRB_4
compare match
does not occur
Level "1" is continuously
output by TGRA_4
compare match
Duty 100%
Current cycle
TGRB_4
compare match
does not occur
Level "1" is output
by TGRA_4
compare match
Duty 0%
Next cycle
Current cycle
Next cycle
Figure 6.4 Setting for Cycle and Duty to Generate PWM Waveforms with Duty of 0% and 100%
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Waveform Output by Using PWM Mode 1
Even the duty is 100% or 0%, the output level of the current cycle should be set to avoid a change in order to maintain
100% or 0% for the next cycle. As shown in Figure 6.5, in the operation of MTU2 PWM mode, the output level does
not change if the TGRA_4 compare match and TGRB_4 compare match occur at the same time (TGRA_4 and
TGRB_4 have the same values),
TGRA_4 compare match and
TGRB_4 compare match occur at
the same time
TCNT_4 value
TGRB_4
TGRA_4
H'0000
Time
(1) Sample operation 1
No change in output
level
TIOC4A
Duty 100%
Duty 100%
Current cycle
Next cycle
(2) Sample operation 2
No change in output
level
TIOC4A
Duty 0%
Duty 0%
Current cycle
Next cycle
Figure 6.5 Setting for Cycle and Duty to Maintain Duty of 100% or 0% during Current Cycle and Next
Cycle
Waveforms with the duty in the range between 1 and 99%, of 0%, and 100% can be output by using the settings
described above.
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Waveform Output by Using PWM Mode 1
Table 6.2 lists the Conversion Pattern for Register Setting Value in Sample Operation 1. The values to be set in the
registers vary depending on the combination of the duty for the current cycle and the duty for the next cycle.
Table 6.2 Conversion Pattern for Register Setting Value in Sample Operation 1
Duty
1 to 99%
Current cycle
Register (TGRB_4) setting value
Calculate using cycle (µs) and duty (%)
1 to 99%
1 to 99%
Calculate using cycle (µs) and duty (%)
*1
Calculate using cycle (µs) and duty (%)
0%
0%
0%
100%
100%
100%
Add "1" to the cycle (TGRA_4) setting
value
Add "1" to the cycle (TGRA_4) setting
value
*3
Setting prohibited
Add "2" to the cycle (TGRA_4) setting
value
Add "2" to the cycle (TGRA_4) setting
value
Same value with the cycle (TGRA_4)
Duty
0%
1 to 99%
*2
100%
0%
1 to 99%
100%
0%
1 to 99%
*3
Setting prohibited
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
*2
Same value with the cycle (TGRA_4)
when the cycle after next cycle is in
between 0 and 99%
Add "2" to the cycle (TGRA_4) setting
value when the cycle after next cycle is
100%
Notes *1: The same value as the cycle (TGRA_4) is set to the duty (TGRB_4) by using the TGRB_4 interrupt
processing. Regarding the TGRB_4 interrupt processing, refer to "6.1.3 Cycle and Duty Setting for
Interrupt Processing Generated by Compare Match" to be hereinafter described.
*2: To change the duty from 100% to the range between 0 and 99%, "0" level should be output for the
next waveform at TGRA compare match by increasing the value of TGRB than the one of TGRA.
Therefore, the values to be set in the duty (TGRB_4) differ depending on the duty for the cycle
after next cycle described under "Next cycle" in the table.
*3: When the output levels at TGRA_4 compare match and TGRB_4 compare match are respectively
set to "0" and "1" to output waveforms, the level of "1" cannot be output at the time that the next
cycle with 0% (output with "0" level) is switched. Refer to "7.1.1 Specifying Duty Value" for more
details.
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100%
Next cycle
Register(TGRB_4) setting value
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
Same value with the cycle (TGRA_4)
when the cycle after next cycle is in
between 0 and 99%
Add "2" to the cycle (TGRA_4) setting
value when the cycle after next cycle is
100%
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
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Waveform Output by Using PWM Mode 1
Table 6.3 lists the Conversion Pattern for Register Setting Value in Sample Operation 2.
Table 6.3 Conversion Pattern for Register Setting Value in Sample Operation 2
Duty
1 to 99%
Current cycle
Register(TGRB_4) setting value
Calculate using cycle (µs) and duty (%)
1 to 99%
1 to 99%
Calculate using cycle (µs) and duty (%)
*1
Calculate using cycle (µs) and duty (%)
100%
100%
100%
0%
0%
0%
Add "1" to the cycle (TGRA_4) setting
value
Add "1" to the cycle (TGRA_4) setting
value
*3
Setting prohibited
Add "2" to the cycle (TGRA_4) setting
value
Add "2" to the cycle (TGRA_4) setting
value
Same value with the cycle (TGRA_4)
Duty
100%
1 to 99%
*2
0%
100%
1 to 99%
0%
100%
1 to 99%
*3
Setting prohibited
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
*2
Same value with the cycle (TGRA_4)
when the cycle after next cycle is in
between 1 and 100%
Add "2" to the cycle (TGRA_4) setting
value when the cycle after next cycle is
0%
Notes *1: The same value as the cycle (TGRA_4) is set to the duty (TGRB_4) by using the TGRB_4 interrupt
processing. Regarding the TGRB_4 interrupt processing, refer to "6.1.3 Cycle and Duty Setting for
Interrupt Processing Generated by Compare Match" to be hereinafter described.
*2: To change the duty from 0% to the range between 1 and 100%, "1" level should be output for the
next waveform at TGRA compare match by increasing the value of TGRB than the one of TGRA.
Therefore, the values to be set in the duty (TGRB_4) differ depending on the duty for the cycle
after next cycle described under "Next cycle" in the table.
*3: When the output levels at TGRA_4 compare match and TGRB_4 compare match are respectively
set to "1" and "0" to output waveforms, the level of "0" cannot be output at the time that the next
cycle with 100% (output with "1" level) is switched. Refer to "7.1.1 Specifying Duty Value" for more
details.
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0%
Next cycle
Register (TGRB_4) setting value
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
Same value with the cycle (TGRA_4)
when the cycle after next cycle is in
between 1 and 100%
Add "2" to the cycle (TGRA_4) setting
value when the cycle after next cycle is
0%
Add "1" to the cycle (TGRA_4) setting
value
Calculate using cycle (µs) and duty (%)
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Waveform Output by Using PWM Mode 1
Table 6.4 lists the Setting Tables Used in Sample Code. The values to be stored in the register setting table are
calculated by using the conversion pattern instead in Table 6.2 and Table 6.3.
Table 6.4 Setting Tables Used in Sample Code
Table
No.
(1)
(2)
(3)
(4)
(5)
(6)
Cycle and duty setting table
Cycle
(μs)
10000
12000
14000
16000
8000
4000
*1
Duty
(%)
*3
70 (30)
*3
10 (90)
*3
0 (100)
*3
40 (60)
*3
100 (0)
*3
100 (0)
Setting table for TGRA_4 and
*2
TGRB_4 registers
TGRA_4 setting value TGRB_4 setting value
(cycle)
(duty)
H'1457
H'0619
H'1868
H'15F7
H'1C7A
H'1C7B
H'208C
H'1386
H'1045
H'1045
H'0822
H'0824
Notes *1: Cycle and duty setting table indicates mtu2_pwm_usertbl1[][] in sample operation 1 and
mtu2_pwm_usertbl2[][] in sample operation 2.
*2: Setting table for TGRA_4 and TGRB_4 registers indicates mtu2_pwm_regtbl[][].
*3: The values in parentheses are used in sample operation 2.
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Waveform Output by Using PWM Mode 1
6.1.3
Cycle and Duty Setting for Interrupt Processing Generated by Compare Match
PWM waveform output is changed by using the interrupt processing generated at TGRA_4 compare match (TGRA_4
interrupt processing) and the interrupt processing generated at TGRB_4 compare match (TGRB_4 interrupt processing).
These processing are described as follows.
• TGRA_4 interrupt processing
In the TGRA_4 interrupt, the value for the next PWM cycle is set to TGRC_4, and the one for the next duty is set to
TGRD_4. In the sample code, the values stored in mtu2_pwm_regtbl[][] are specified for TGRC_4 and TGRD_4
registers. To change the waveforms in the order of table number from (1) to (6) shown in Table 6.4, the table
number to be set should be changed every time the interrupt request occurs at TGRA_4 compare match. In sample
operation 1, TGRB_4 interrupt is enabled to change the next duty from the range between 1 and 99% to 100% (to
change from the range between 1 and 99% to 0% in sample operation 2).
• TGRB_4 interrupt processing
In theTGRB_4 interrupt, the current value of TGRA_4 is set to TGRB_4. When TGRA_4 and TGRB_4 have the
same value, the compare match of TGRA_4 and TGRB_4 for the next cycle occurs at the same time. This retains
the output level to avoid a change in waveform output. TGRB_4 interrupt is disabled after the TGRB_4 interrupt
processing ends.
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Waveform Output by Using PWM Mode 1
6.1.4
Sample Operation 1
Figure 6.6 and Figure 6.7 show the Register Sequence when PWM Waveform is Output in Sample Operation 1.
Figure 6.6 Register Sequence when PWM Waveform is Output in Sample Operation 1 (1/2)
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Figure 6.7 Register Sequence when PWM Waveform is Output in Sample Operation 1 (2/2)
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6.1.5
Sample Operation 2
Figure 6.8 and Figure 6.9 show the Register Sequence when PWM Waveform is Output in Sample Operation 2.
Figure 6.8 Register Sequence when PWM Waveform is Output in Sample Operation 2 (1/2)
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Figure 6.9 Register Sequence when PWM Waveform is Output in Sample Operation 2 (2/2)
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6.2
6.2.1
Peripheral Function Settings and Memory Allocation Used in Sample Code
Peripheral Function Settings
Table 6.5 lists the Peripheral Function Settings.
Table 6.5 Peripheral Function Settings
Module
MTU2
STB
PORT
INTC
SCIF
Note: *
Setting
Channel 4
Operating mode: PWM mode1
Count clock: Set at P0f/64
Source of counter clear: TGRA_4 compare match
Edge of input clock: Count on rising edge
Buffer operation A: TGRA_4 and TGRC_4
Buffer operation B: TGRB_4 and TGRD_4
• Settings for sample operation 1
Function of TGRA: 0 output for initial output, 0 output at compare match
Function of TGRB: 0 output for initial output, 1 output at compare match
• Settings for sample operation 2
Function of TGRA: 1 output for initial output, 1 output at compare match
Function of TGRB: 1 output for initial output, 0 output at compare match
Transfer timing from TGRC_4 to TGRA_4: When TCNT is cleared.
Transfer timing from TGRD_4 to TGRB_4: When TCNT is cleared.
Interrupt request by the TGFA bit (TGIA): TGRA_4 interrupt enabled
(The interrupt request is occurred by the TGFA bit when TCNT_4=TGRA_4.)
Interrupt request by the TGFB bit (TGIB): TGRB_4 interrupt enabled*
(The interrupt request is occurred by the TGFB bit when TCNT_4=TGRB_4.)
TCNT independent operation: Do not synchronized with the channel 4
Clock is supplied to MTU2
PORT 4 multiplexed pin function setting
P4_4 : TIOC4A
Registration and execution of handlers for MTU2 channel 4 TGRA compare
match interrupt (Interrupt ID: 159) and MTU2 channel 4 TGRB compare
match interrupt (Interrupt ID: 160).
Channel 2 is set to asynchronous mode
• Data length: 8 bits
• Stop bit length: 1 bit
• Parity : None
Settings such that when P1f=66.67MHz, the clock is not divided, the bit rate
value is 17, and the bit rate is 115200pbs.
Error: 0.46%
The TGRB_4 interrupt is enabled by initial setting or TGRA_4 interrupt processing when the next
duty is 100% in sample operation 1 (0% in sample operation 2).
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6.2.2
Section Assignment of Sample Code
Table 6.6 and Table 6.7 list the Sections Used in the sample code. Figure 6.10 shows the section assignment in initial
state of the sample code (load view) and the section assignment after the scatter loading function applied.
For more details about the sections and the scatter loading function, refer to "Image structure and generation" in ARM
Compiler toolchain: Using the Linker.
Table 6.6 Sections Used (1/2)
Area Name
Description
VECTOR_TABLE
RESET_HANDLER
Exception handling vector table
Program code area for reset handler
This area consists of the following sections.
• INITCA9CACHE (L1 cache setting)
• INIT_TTB (MMU setting)
• RESET_HANDLER (Reset handler)
CODE_BASIC_SETUP Program code area for operating frequency
and flash memory optimization
InRoot
This section consists of the sections
assigned to the root area such as C
standard library.
CODE_FPU_INIT
CODE_RESET
CODE_IO_REGRW
CODE
CONST
Program code area for NEON and VFP
initial settings
This area consists of the following sections.
• CODE_FPU_INIT
• FPU_INIT
Program code area for hardware initial
setting
This area consists of the following sections.
• CODE_RESET (Startup processing)
• INIT_VBAR (Vector base setting)
Program code area for I/O register
read/write functions
Program code area for default
Code type sections whose names are not
defined in the C source are all assigned to
this area.
Constant data area for default
RO Data type sections whose names are not
defined in the C source are all assigned to
this area.
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Type
Code
Code
Load
Area
FLASH
FLASH
Execution
Area
FLASH
FLASH
Code
FLASH
FLASH
Code
and
RO Data
Code
FLASH
FLASH
FLASH
FLASH
Code
FLASH
FLASH
Code
FLASH
LRAM
Code
FLASH
FLASH
RO Data
FLASH
FLASH
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Table 6.7 Sections Used (2/2)
Area Name
VECTOR_MIRROR_
TABLE
Description
Type
Load Area
Execution
Area
LRAM
Exception handling vector table
Code
FLASH
(Section for transferring program data to
large-capacity on-chip RAM)
CODE_HANDLER_
Program code area for user-defined
Code
FLASH
LRAM
functions of IRQ interrupt handler
JMPTBL
CODE_HANDLER
Program code area for IRQ interrupt
Code
FLASH
LRAM
handler
This area consists of the following
sections.
• CODE_HANDLER
• IRQ_FIQ_HANDLER
CODE_CACHE_
Program code area for setting the L1 and
Code
FLASH
LRAM
L2 caches*3
OPERATION
DATA_HANDLER_
Registration table data area for userRW Data
FLASH
LRAM
defined functions of IRQ interrupt handler
JMPTBL
ARM_LIB_STACK
Application stack area
ZI Data
LRAM
IRQ_STACK
IRQ mode stack area
ZI Data
LRAM
FIQ_STACK
FIQ mode stack area
ZI Data
LRAM
SVC_STACK
Supervisor (SVC) mode stack area
ZI Data
LRAM
ABT_STACK
Abort (ABT) mode stack area
ZI Data
LRAM
TTB
MMU translation table area
ZI Data
LRAM
ARM_LIB_HEAP
Application heap area
ZI Data
LRAM
DATA
Data area with initial value for default
RW Data
FLASH
LRAM
RW Data type sections whose names are
not defined in the C source are all
assigned to this area.
BSS
Data area without initial value for default
ZI Data
LRAM
ZI Data type sections whose names are
not defined in the C source are all
assigned to this area
Notes: 1. In the table above, FLASH in the load area indicates the NOR flash memory area, and LRAM in
the execution area indicates the large-capacity on-chip RAM area.
2. The section names basically are the same as the area names, but each area for the
RESET_HANDLER, InRoot, CODE_FPU_INIT, CODE_RESET, CODE, CONST,
CODE_HANDLER, DATA, and BSS consists of multiple sections. Refer to the ARM compiler
toolchain manual about areas and sections.
3. This section should be placed in the cache-disabled area.
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Section assignment
(load view)
RZ/A1H group
address space
(virtual address)
H'FFFF FFFF
Section assignment
(execution view)
Memory allocation after
scatter loading
H'609F FFFF
CODE_CACHE_OPERATION
H'6050 0000
Transfer cache
operation
process to
cache-disabled
area in on-chip
RAM
H'6000 0000
H'209F FFFF
Clear to 0
BSS
Initialize data with
initial values
DATA
H'200B 8000
Obtain areas
for stacks
and the like
H'2003 8000
H'2003 4000
H'2003 2000
H'2003 0000
H'2002 E000
H'2002 C000
H'60A0 0000
H'6000 0000
Cache-disabled space in
large-capacity on-chip
RAM (10MB)
ARM_LIB_HEAP
TTB
ABT_STACK
SVC_STACK
FIQ_STAC
IRQ_STACK
ARM_LIB_STACK
H'2002 4000
Initialize
data with
initial values
DATA_HANDLER_JMPTBL
CODE_IO_REGRW
CODE_HANDLER
H'2002 0100
CODE_HANDLER_JMPTBL
H'2002 0000
VECTOR_MIRROR_TABLE
H'2000 0000
H'03FF FFFF
CODE_CACHE_OPERATION
H'4000 0000
DATA
DATA_HANDLER_JMPTBL
H'20A0 0000
CODE_IO_REGRW
Large-capacity on-chip
RAM (10MB)
CODE_HANDLER
H'2000 0000
CODE_HANDLER_JMPTBL
CONST
H'1C00 0000
CODE
Transfer program
code that requires
high-speed
processing to the
on-chip RAM
CONST
CODE
H'1800 0000
H'1000 0000
H'0C00 0000
H'0800 0000
CODE_RESET
CODE_RESET
CODE_FPU_INIT
CODE_FPU_INIT
InRoot
InRoot
CODE_BASIC_SETUP
CODE_BASIC_SETUP
RESER_HANDLER
H'0000 0200
H'0400 0000
H'0000 0000
CS0 space (64 MB)
H'0000 0100
VECTOR_MIRROR_TABLE
H'0000 0000
VECTOR_TABLE
Transfer exception
processing vector
to the on-chip RAM
RESER_HANDLER
VECTOR_TABLE
Figure 6.10 Section Assignment
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6.3
Interrupts
Table 6.8 lists the Interrupts Used in Sample Code.
Table 6.8 Interrupts Used in Sample Code
Interrupt source
(Interrupt ID)
TGI4A (159)
Processing Overview
1
Interrupt generated by TGRA_4 compare match
Set the next cycle and duty to TGRC_4 and TGRD_4 registers.
TGI4B (TGRB_4 interrupt) is enabled in the following conditions.
• The duty is changed from the range between 1 and 99% to
100% in sample operation 1.
• The duty is changed from the range between 1 and 99% to
0% in sample code 2.
Interrupt generated by TGRB_4 compare match
Set the value of TGRA_4 for TGRB_4 to disable TGI4B (TGRB_4
interrupt) in order to avoid a change in waveform output at the
next TGRA_4 compare match.
1
TGI4B (160)
6.4
Priority
Fixed-Width Integers
Table 6.9 lists the Fixed-Width Integers Used in Sample Code.
Table 6.9 Fixed-Width Integers Used in Sample Code
Symbol
char_t
bool_t
int_t
int8_t
int16_t
int32_t
int64_t
uint8_t
uint16_t
uint32_t
uint64_t
float32_t
float64_t
float128_t
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Description
8-bit character
Logical type. The value is true (1) or false (0)
High-speed integer, signed
32-bit integers are used in this sample code.
8-bit integer, signed (defined in the standard library)
16-bit integer, signed (defined in the standard library)
32-bit integer, signed (defined in the standard library)
64-bit integer, signed (defined in the standard library)
8-bit integer, unsigned (defined in the standard library)
16-bit integer, unsigned (defined in the standard library)
32-bit integer, unsigned (defined in the standard library)
64-bit integer, unsigned (defined in the standard library)
32-bit floating point number
(defined in the standard library when "__ARM_NEON__" is specified)
64-bit floating point number (defined in the standard library)
(defined in the standard library when "__ARM_NEON__" is specified)
128-bit floating point number
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6.5
Constants
Table 6.10 lists the Constants Used in Sample Code.
Table 6.10 Constants Used in Sample Code
Constant Name
Setting
Value
MTU2_USER_TABLE_NUM
DEVDRV_CH_0
DEVDRV_CH_3
DEVDRV_CH_4
MTU2_CKS_DIVISION_1
MTU2_CKS_DIVISION_4
MTU2_CKS_DIVISION_16
MTU2_CKS_DIVISION_64
MTU2_CKS_DIVISION_256
MTU2_CKS_DIVISION_1024
MTU2_CMP_MATCH_A0_B1
(6)
(0)
(3)
(4)
(0)
(1)
(2)
(3)
(4)
(5)
(0x21)
MTU2_CMP_MATCH_A1_B0
(0x56)
MTU2_TABLE_CYCLE
(0)
MTU2_TABLE_DUTY
(1)
MTU2_P0_CLOCK_FREQ_Hz
(33.333333
*1000000)
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Contents
Amount of information of cycle and duty setting tables
Channel 0 is used
Channel 3 is used
Channel 4 is used (used in this sample code)
TCNT count clock is set at P0 f/1
TCNT count clock is set at P0f/4
TCNT count clock is set at P0f/16
TCNT count clock is set at P0f/64
TCNT count clock is set at P0f/256
TCNT count clock is set at P0f/1024
Set the initial output level to "0" and the output levels
at TGRA_4 compare match and TGRB_4 compare
match to "0" and "1" respectively (TIORH register
setting)
Set the initial output level to "1" and the output levels
at TGRA_4 compare match and TGRB_4 compare
match to "1" and "0" respectively (TIORH register
setting)
Definition for specifying the cycle information
regarding the array in cycle and duty setting table and
setting table for TGRA_4 and TGRB_4 registers
Definition for specifying the duty information regarding
the array in cycle and duty setting table and setting
table for TGRA_4 and TGRB_4 registers
Definition of P0f frequency
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6.6
Variables
Table 6.11 lists the static Variables.
Table 6.11 static Variables
Type
static
uint32_t
Variable Name
mtu2_pwm_num
static
uint32_t
mtu2_pwm_usertbl1[][]
static
uint32_t
mtu2_pwm_usertbl2[][]
static
uint16_t
mtu2_pwm_regtbl[][]
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Contents
Table number of setting
table for TGRA_4 and
TGRB_4 registers
Cycle and duty setting
table used in sample
operation 1
Cycle and duty setting
table used in sample
operation 2
Setting table for
RGRA_4 and TGRB_4
registers
(Table which converted
the values in cycle and
duty setting table into
the values to be set to
the registers)
Function Used
Sample_MTU2_PWM1_Output
Sample_MTU2_PWM1_TGI4A_Interrupt
Sample_MTU2_PWM1_Output
Sample_MTU2_PWM1_Output
Sample_MTU2_PWM1_Output
Sample_MTU2_PWM1_TGI4A_Interrupt
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Waveform Output by Using PWM Mode 1
6.7
Functions
The sample code consists of interface functions to perform the MTU2 PWM waveform output, user-defined functions
(functions called from the API functions) to be prepared by users according to their systems, and sample functions
required to operate the sample code.
Table 6.12, Table 6.13, and Table 6.14 list the Sample Functions, the API Functions, and the User-Defined Functions
respectively.
Table 6.12 Sample Functions
Function Name
main
Sample_Main
Sample_MTU2_PWM1_Main
Sample_MTU2_PWM1_Output
Sample_MTU2_PWM1_Stop
MTU2_PWM1_PORT_Init
Sample_MTU2_PWM1
_TGI4A_Interrupt
Sample_MTU2_PWM1
_TGI4B_Interrupt
Outline
Main processing
Sample code main processing
Sample code main processing to output waveforms in PWM mode 1
of MTU2
Sample processing to output PWM waveforms
Sample processing to stop the timer used in PWM waveform output
Initial settings for PORT used in PWM waveform output.
TGRA_4 interrupt processing
TGRB_4 interrupt processing
Table 6.13 API Functions
Function Name
R_MTU2_PWM1_RegTblConv
R_MTU2_PWM1_Init
R_MTU2_PWM1_Open
R_MTU2_PWM1_Close
R_MTU2_PWM1_TGInA_Interrupt
R_MTU2_PWM1_TGInB_Interrupt
Outline
Converting cycle and duty into register setting values
Initial settings in PWM mode 1 of MTU2
Start of timer count in PWM mode 1 of MTU2
Stop of timer count in PWM mode 1 of MTU2
TGInA interrupt processing in PWM mode 1 of MTU2
TGInB interrupt processing in PWM mode 1 of MTU2
Table 6.14 User-Defined Functions
Function Name
Userdef_MTU2_PWM1_Ch0_Init
Userdef_MTU2_PWM1_Ch3_Init
Userdef_MTU2_PWM1_Ch4_Init
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Outline
MTU2 channel 0 initial settings in PWM mode 1
(In the sample code, this function returns after providing only STB
initial settings.)
MTU2 channel 0 initial settings in PWM mode 3
(In the sample code, this function returns after providing only STB
initial settings.)
MTU2 channel 0 initial settings in PWM mode 4
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6.8
Function Specifications
The following tables list the sample code function specifications.
main
Outline
Declaration
Description
Argument
Return Value
Sample_Main
Outline
Declaration
Description
Arguments
Return Value
Main processing
int_t main(void)
Displays the sample code information to the terminal running on the host PC
connected to the GENMAI board via the serial interface.
None
0
Sample code main processing
void Sample_Main(void)
Waits for character input from the terminal running on the host PC connected to the
GENMAI board via the serial interface. When "MTU2_PWM1" + "Enter" keys are
input from the terminal, this function executes the sample code to output waveforms
in PWM mode 1 of MTU2.
None
None
Sample_MTU2_PWM1_Main
Sample code main processing to output waveforms in PWM mode 1 of MTU2
Outline
int32_t Sample_MTU2_PWM1_Main(int32_t argc, char_t ** argv)
Declaration
Waits for character input from the terminal running on the host PC connected to the
Description
GENMAI board via the serial interface. When the following commands are input, this
function executes the sample codes to output waveforms in PWM mode 1 of MTU2.
Input "1" + "Enter" key: Execute sample operation 1
Input "2" + "Enter" key: Execute sample operation 2
Input "STOP" + "Enter" key: Stop PWM waveform output
int32_t argc
: Number of command arguments input from the terminal
Arguments
char_t **argv
: Pointer to commands input from the terminal
COMMAND_EXIT
: End of MTU2 sample code processing
Return Value
When the sample code is executed, PWM waveforms are continuously output. To
Note
subsequently execute the sample code, the waveform output must be suspended by
"STOP" + "Enter" keys.
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Sample_MTU2_PWM1_Output
Sample processing to output PWM waveforms
Outline
int32_t Sample_MTU2_PWM1_Output(int32_t argc, char_t ** argv)
Declaration
The MTU2 channel 4 is used to output waveforms in PWM mode 1.
Description
Converts the information specified by the cycle (μs) and duty (%) into the register
setting values using the P0f/64 clock source for the count clock to output PWM
waveforms from the TIOC4A pin.
In sample operation 1, the initial output level of output pin is set to "0" and output
levels for TGRA_4 compare match and TGRB_4 compare match to "0" and "1"
respectively, and the waveforms with the cycle and duty of 10ms/70%, 12ms/10%,
14ms/0%, 16ms/40%, 8ms/100%, and 4ms/100% are continuously output.
In sample operation 2, the initial output level of output pin is set to "1" and output
levels for TGRA_4 compare match and TGRB_4 compare match to "1" and "0"
respectively, and the waveforms with the cycle and duty of 10ms/30%, 12ms/90%,
14ms/100%, 16ms/60%, 8ms/0%, and 4ms/0% are continuously output.
int32_t argc
: Number of command arguments input from the terminal
Arguments
Not used in this function.
char_t **argv
: Pointer to commands input from the terminal
When argv[0][0] is "1", sample operation 1 is executed.
When argv[0][0] is "2", sample operation 2 is executed
COMMAND_SUCCESS
: Success of MTU2 PWM waveform output
Return Value
COMMAND_ERROR
: Failure of MTU2 PWM waveform output
Sample_MTU2_PWM1_Stop
Sample processing to stop timer used in PWM waveform output
Outline
int32_t Sample_MTU2_PWM1_Stop(int32_t argc, char_t ** argv)
Declaration
Stops the timer count on MTU2 channel 4 to stop the PWM waveform output. The
Description
level at the time the timer count stopped is continuously output using the TIOC4A
pin.
int32_t argc
: Number of command arguments input from the terminal
Arguments
Not used in this function.
char_t **argv
: Pointer to commands input from the terminal
Not used in this function.
COMMAND_SUCCESS
: Success in stopping timer used in PWM waveform
Return Value
output
COMMAND_ERROR
: Failure in stopping timer used in PWM waveform
output
MTU2_PWM1_PORT_Init
Initial setting for PORT used in PWM waveform output
Outline
static void MTU2_PWM1_PORT_Init(void)
Declaration
Initializes the PORT used to output PWM waveforms of MTU2.
Description
In the sample code, the PORT is initialized to use P4_4 pin as the TIOC4A function.
None
Argument
None
Return Value
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Sample_MTU2_PWM1_TGI4A_Interrupt
TGRA_4 interrupt processing
Outline
void Sample_MTU2_PWM1_TGI4A_Interrupt(uint32_t int_sense)
Declaration
This is an interrupt handler executed when an interrupt generated by TGRA_4
Description
compare match has been accepted.
Sets the setting values for the next cycle and duty to the argument and executes the
processing to output specified PWM waveforms during the next cycle by calling the
API function R_MTU2_PWM1_TGInA_Interrupt.
Also, increments the variables which indicate table number for cycle and duty.
In the sample code, this function is registered as INTC handler by using the userdefined function Userdef_MTU2_PWM1_Ch4_Init.
uint32_t int_sense
: Interrupt detection method (not used)
Argument
INTC_LEVEL_SENSITIVE
: Level sense
INTC_EDGE_TRIGGER
: Edge
None
Return Value
Sample_MTU2_PWM1_TGI4B_Interrupt
TGRB_4 interrupt processing
Outline
void Sample_MTU2_PWM1_TGI4B_Interrupt(uint32_t int_sense)
Declaration
This is an interrupt handler executed when an interrupt generated by TGRB_4
Description
compare match has been accepted.
Execute the processing to avoid a change in PWM waveforms at the next TGRA_4
compare match by calling the API function R_MTU2_PWM1_TGInB_Interrupt.
In the sample code, this function is registered as INTC handler by using the userdefined function Userdef_MTU2_PWM1_Ch4_Init.
uint32_t int_sense
: Interrupt detection method (not used)
Argument
INTC_LEVEL_SENSITIVE
: Level sense
INTC_EDGE_TRIGGER
: Edge
None
Return Value
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R_MTU2_PWM1_RegTblConv
Converting cycle and duty into register setting values
Outline
int32_t R_MTU2_PWM1_RegTblConv(uint8_t cks, uint8_t tior_mode,
Declaration
uint32_t p0clk_freq, uint32_t tbl_num,
uint32_t (* mtu2_pwm_usertbl)[2],
uint16_t (* mtu2_pwm_regtbl)[2])
Converts the cycle and duty information of the table specified by the argument*
Description
mtu2_pwm_usertbl[] into the values of the cycle and duty to be set in the registers for
the amount specified by the argument tbl_num, and stores them in the table specified
by the argument* mtu2_pwm_regtbl[].
The cycle and duty register setting values are converted from the values of cycle (μs)
and duty (%) in the specified table using the P0f frequency (Hz) specified by the
argument p0clk_freq and the count clock specified by the argument cks. The duty is
defined as percentage for High width in cycle, and the conversion expression for the
register setting values differs depending on the argument tior_mode specification.
When the cycle (μs) or the duty (%) that cannot be converted into register setting
values is specified, DEVDRV_ERROR is returned.
uint8_t cks
TCNT count clock
Arguments
MTU2_CKS_DIVISION_1
: P0 f/1 clock
MTU2_CKS_DIVISION_4
: P0 f/4 clock
MTU2_CKS_DIVISION_16
: P0 f/16 clock
MTU2_CKS_DIVISION_64
: P0 f/64 clock
MTU2_CKS_DIVISION_256
: P0 f/256 clock
MTU2_CKS_DIVISION_1024 : P0 f/1024 clock
uint8_t tior_mode
: TGRA and TGRB operations
MTU2_CMP_MATCH_A0_B1:
Select "0" for initial output level of output pin
Select "0" for output level at TGRA compare match
Select "1" for output level at TGRB compare match
MTU2_CMP_MATCH_A1_B0:
Select "1" for initial output level of output pin
Select "1" for output level at TGRA compare match
Select "0" for output level at TGRB compare match
uint32_t p0clk_freq
Frequency of P0f (Hz)
uint32_t tbl_num
Amount of cycle and duty information
uint32_t
Cycle and duty setting table
(* mtu2_pwm_usertbl)[2]
uint16_t
Setting table for TGRA_4 and TGRB_4 registers
(* mtu2_pwm_regtbl)[2]
DEVDRV_SUCCESS : Success in converting into register setting values
Return Value
DEVDRV_ERROR
: Failure in converting into register setting values
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Waveform Output by Using PWM Mode 1
R_MTU2_PWM1_Init
Initial settings in PWM mode 1 of MTU2
Outline
int32_t R_MTU2_PWM1_Init(uint32_t channel, uint8_t cks, uint8_t tior_mode,
Declaration
uint16_t (* mtu2_pwm_regtbl)[2])
Initializes MTU2 specified by the argument channel by using the count clock specified
Description
by the argument cks in operating state of TGRA and TGRB specified by the argument
tior_mode. The initial values are set to TGRA and TGRB registers based on the table
information specified by the argument* mtu2_pwm_regtbl.
Initial settings are made by using the user-defined function Userdef_MTU2_Chn_Init
(n=0, 3, or 4).
This function should be called after converting the cycle and duty information into the
register setting values by calling the API function R_MTU2_PWM1_RegTblConv and
storing them in the setting table for TGRA and TGRB registers.
uint32_t channel
: MTU2 channel (0,3, or 4)
Arguments
uint8_t cks
: TCNT count clock
MTU2_CKS_DIVISION_1
: P0 f/1 clock
MTU2_CKS_DIVISION_4
: P0 f/4 clock
MTU2_CKS_DIVISION_16
: P0 f/16 clock
MTU2_CKS_DIVISION_64
: P0 f/64 clock
MTU2_CKS_DIVISION_256
: P0 f/256 clock
MTU2_CKS_DIVISION_1024 : P0 f/1024 clock
uint8_t tior_mode
: TGRA and TGRB operations
MTU2_CMP_MATCH_A0_B1:
Select "0" for initial output level of output pin
Select "0" for output level at TGRA compare match
Select "1" for output level at TGRB compare match
MTU2_CMP_MATCH_A1_B0:
Select "1" for initial output level of output pin
Select "1" for output level at TGRA compare match
Select "0" for output level at TGRB compare match
uint16_t
: Setting table for TGRA and TGRB registers
(* mtu2_pwm_regtbl)[2])
DEVDRV_SUCCESS : Success of MTU2 initialization
Return Value
DEVDRV_ERROR
: Failure of MTU2 initialization
In the sample code, the external clocks (TCLKA, TCLKB, TCLKC, and TCLKD) cannot
Note
be specified as the count clock.
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Waveform Output by Using PWM Mode 1
R_MTU2_PWM1_Open
Start of timer count in PWM mode 1 of MTU2
Outline
int32_t R_MTU2_PWM1_Open(uint32_t channel)
Declaration
Starts the MTU2 timer count specified by the argument channel. Channel 0, 3, or 4
Description
can be specified.
uint32_t channel
: MTU2 channel (0,3, or 4)
Argument
DEVDRV_SUCCESS : Success in starting MTU2 timer count
Return Value
DEVDRV_ERROR
: Failure in starting MTU2 timer count
R_MTU2_PWM1_Close
Stop of timer count in PWM mode 1 of MTU2
Outline
int32_t R_MTU2_PWM1_Close(uint32_t channel)
Declaration
Stops the MTU2 timer count specified by the argument channel. Channel 0, 3, or 4
Description
can be specified.
uint32_t channel
: MTU2 channel (0,3, or 4)
Argument
DEVDRV_SUCCESS : Success in stopping MTU2 timer count
Return Value
DEVDRV_ERROR
: Failure in stopping MTU2 timer count
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Waveform Output by Using PWM Mode 1
R_MTU2_PWM1_TGInA_Interrupt
TGInA interrupt processing in PWM mode 1 of MTU2
Outline
int32_t R_MTU2_PWM1_TGInA_Interrupt(uint32_t channel, uint16_t cycle_reg,
Declaration
uint16_t duty_reg)
Sets the values specified by the arguments cycle_reg and duty_reg to the buffer
Description
registers (TGRC and TGRD) of the channel specified by the argument channel as
the cycle and duty information of PWM waveform to be output next.
When the values specified by the arguments cycle_reg and duty_reg are equal, or
the value where "2" is added to the argument cycle_reg and the value specified by
the argument duty_reg are equal, and also when the duty of the current PWM
waveform is in the range between 1 and 99%, the TGRB interrupt specified by the
argument channel is enabled to avoid a change in the waveform at the next TGRA
compare match.
uint32_t channel
: MTU2 channel (0,3, or 4)
Arguments
uint16_t cycle_reg
: Setting value for the next cycle
uint16_t duty_reg
: Setting value for the next duty
DEVDRV_SUCCESS : Success of TGInA interrupt processing
Return Value
DEVDRV_ERROR
: Failure of TGInA interrupt processing
R_MTU2_PWM1_TGInB_Interrupt
TGInB interrupt processing in PWM mode 1 of MTU2
Outline
int32_t R_MTU2_PWM1_TGInB_Interrupt(uint32_t channel)
Declaration
When the value of TGRA is specified for the one of TGRB to avoid a change in the
Description
waveform at TGRA compare match of the channel specified by the argument
channel, the duty of the current waveform is in the range between 1 and 99% and
the next waveform to be output can be controlled. If PWM waveform is output at the
levels of "0" at TGRA compare match and "1" at TGRB compare match, the
waveform with the duty of 100% is output next. If PWM waveform is output at the
levels of "1" at TGRA compare match and "0" at TGRB compare match, the
waveform with the duty of 0% is output next.
The TGRB interrupt specified by the argument channel is disabled.
uint32_t channel
: MTU2 channel (0,3, or 4)
Argument
DEVDRV_SUCCESS : Success of TGInB interrupt processing
Return Value
DEVDRV_ERROR
: Failure of TGInB interrupt processing
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Waveform Output by Using PWM Mode 1
Userdef_MTU2_PWM1_Ch0_Init
MTU2 channel 0 initial settings
Outline
void Userdef_MTU2_PWM1_Ch0_Init(uint8_t cks, uint8_t tior_mode,
Declaration
uint16_t (* mtu2_pwm_regtbl)[2])
This is a user-defined function. Initial settings for the MTU2 channel 0 and settings to
Description
use interrupts are required when the channel 0 is applied.
In the sample code, this function returns after providing only STB initial settings to
supply a clock to MTU2 if the clock has not been supplied.
uint8_t cks
: TCNT count clock
Arguments
MTU2_CKS_DIVISION_1
: P0 f/1 clock
MTU2_CKS_DIVISION_4
: P0 f/4 clock
MTU2_CKS_DIVISION_16
: P0 f/16 clock
MTU2_CKS_DIVISION_64
: P0 f/64 clock
uint8_t tior_mode
: TGRA and TGRB operations
MTU2_CMP_MATCH_A0_B1:
Select "0" for initial output level of output pin
Select "0" for output level at TGRA compare match
Select "1" for output level at TGRB compare match
MTU2_CMP_MATCH_A1_B0:
Select "1" for initial output level of output pin
Select "1" for output level at TGRA compare match
Select "0" for output level at TGRB compare match
uint16_t
: Setting table for TGRA and TGRB registers
(* mtu2_pwm_regtbl)[2]
None
Return Value
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Waveform Output by Using PWM Mode 1
Userdef_MTU2_PWM1_Ch3_Init
MTU2 channel 3 initial settings
Outline
void Userdef_MTU2_PWM1_Ch3_Init(uint8_t cks, uint8_t tior_mode,
Declaration
uint16_t (* mtu2_pwm_regtbl)[2])
This is a user-defined function. Initial settings for the MTU2 channel 3 and settings to
Description
use interrupts are required when the channel 3 is applied.
In the sample code, this function returns after providing only STB initial settings to
supply a clock to MTU2 if the clock has not been supplied.
uint8_t cks
: TCNT count clock
Arguments
MTU2_CKS_DIVISION_1
: P0 f/1 clock
MTU2_CKS_DIVISION_4
: P0 f/4 clock
MTU2_CKS_DIVISION_16
: P0 f/16 clock
MTU2_CKS_DIVISION_64
: P0 f/64 clock
MTU2_CKS_DIVISION_256
: P0 f/256 clock
MTU2_CKS_DIVISION_1024 : P0 f/1024 clock
uint8_t tior_mode
: TGRA and TGRB operations
MTU2_CMP_MATCH_A0_B1:
Select "0" for initial output level of output pin
Select "0" for output level at TGRA compare match
Select "1" for output level at TGRB compare match
MTU2_CMP_MATCH_A1_B0:
Select "1" for initial output level of output pin
Select "1" for output level at TGRA compare match
Select "0" for output level at TGRB compare match
uint16_t
: Setting table for TGRA and TGRB registers
(* mtu2_pwm_regtbl)[2]
Note
Return Value
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Waveform Output by Using PWM Mode 1
Userdef_MTU2_PWM1_Ch4_Init
MTU2 channel 4 initial settings
Outline
void Userdef_MTU2_PWM1_Ch4_Init(uint8_t cks, uint8_t tior_mode,
Declaration
uint16_t (* mtu2_pwm_regtbl)[2])
This is a user-defined function. Initial settings for the MTU2 channel 4 are required.
Description
In the sample code, STB initial settings are provided to supply a clock to MTU2 if the
clock has not been supplied. The arguments cks and tior_mode are respectively
specified for the TPSC bit in the TCR_4 register and the TIORH_4 register.
By using the argument* mtu2_pwm_regtbl[], the cycle and duty of the waveform to be
output first is set to TGRA_4 and TGRB_4 registers from the first information in the
setting table for TGRA and TGRB registers. The cycle and duty of the second
waveform to be output is set to TGRC_4 and TGRD_4 registers from the second
information in the setting table for TGRA and TGRB registers.
If the argument tior_mode is MTU2_CMP_MATCH_A0_B1, the TGRB_4 interrupt is
enabled when the duty of the second waveform to be output is set to 100%. If the
argument tior_mode is MTU2_CMP_MATCH_A1_B0, the TGRB_4 interrupt is
enabled when the duty of the second waveform to be output is set to 0%.
Settings to use TGRA_4 and TGRB_4 interrupts and INTC setting are made by this
function.
uint8_t cks
: TCNT count clock
Arguments
MTU2_CKS_DIVISION_1
: P0 f/1 clock
MTU2_CKS_DIVISION_4
: P0 f/4 clock
MTU2_CKS_DIVISION_16
: P0 f/16 clock
MTU2_CKS_DIVISION_64
: P0 f/64 clock
MTU2_CKS_DIVISION_256
: P0 f/256 clock
MTU2_CKS_DIVISION_1024 : P0 f/1024 clock
uint8_t tior_mode
: TGRA and TGRB operations
MTU2_CMP_MATCH_A0_B1:
Select "0" for initial output level of output pin
Select "0" for output level at TGRA compare match
Select "1" for output level at TGRB compare match
MTU2_CMP_MATCH_A1_B0:
Select "1" for initial output level of output pin
Select "1" for output level at TGRA compare match
Select "0" for output level at TGRB compare match
uint16_t
: Setting table for TGRA and TGRB registers
(* mtu2_pwm_regtbl)[2]
None
Return Value
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Waveform Output by Using PWM Mode 1
6.9
6.9.1
Flowcharts
Main Function
Figure 6.11 shows the flowchart of Main Function.
main
Output to terminal software
printf()
OSTM0-related settings
Startup function of sample code
for each peripheral function
Sample_Main()
Output the sample code version information to the terminal
running on the host PC connected by the serial interface.
Blink the LED every 500ms using the OSTM channel 0 interrupt.
Refer to the RZ/A1H group application note Example of
Initialization.
Branch to the processing to wait for receiving commands from
the terminal.
Execute the sample codes for peripheral functions according
to the commands received.
return (0)
Figure 6.11 Main Function
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Waveform Output by Using PWM Mode 1
6.9.2
Sample Code Main Function
Figure 6.12 shows the flowchart of Sample Code Main Function. This function waits character input from the terminal
running on the host PC.
When "MTU2_PWM1" + "Enter" keys are input, the sample code is executed to output waveforms in PWM mode 1 of
MTU2.
Sample_Main
Output to terminal software
printf()
Output the sample code prompt to the terminal running on the
host PC.
Obtain command list of
main processing
Sample_GetCmdList()
Obtain the command list of the main processing. In this sample
code, the menu list is obtained to start the sample code of the
MTU2 PWM waveform output.
Register command list of
main processing
CommandSetCmdList()
Register the command list of the main processing. In this sample
code, the menu list is registered to start the sample code of the
MTU2 PWM waveform output.
Wait for command input
gets()
Wait for the command input from the terminal, and store it in the
command buffer.
Analyze and execute
commands
CommandExe()
Input "EXIT"?
Analyze and execute the contents of the command buffer. In this
sample code, the menu list of the sample code processing for the
MTU2 PWM waveform output is registered, and this function
branches to the Sample_MTU2_PWM1_Main function to execute the
sample code processing.
No "EXIT" input
"EXIT" input
Reobtain command list of
main processing
Sample_GetCmdList()
Re-register command list of
main processing
CommandSetCmdList()
Figure 6.12 Sample Code Main Function
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Waveform Output by Using PWM Mode 1
6.9.3
Sample Main Function to Output Waveforms in PWM Mode 1 of MTU2
Figure 6.13 shows the flowchart of Sample Main Function to Output Waveforms in PWM Mode1 of MTU2. This
function waits for character input from the terminal running on the host PC and branches to the sample code processing
to output waveforms in PWM mode 1 of MTU2.
When "1" + "Enter" keys are input, sample operation 1 (which outputs waveforms at the initial output level of "0", the
output level at TGRA_4 compare match of "0", and the output level at TGRB_4 compare match of "1") is executed.
When "2" + "Enter" keys are input, sample operation 2 (which outputs waveforms at the initial output level of "1", the
output level at TGRA_4 compare match of "1", and the output level at TGRB_4 compare match of "0") is executed.
When "STOP" + "Enter" keys are input, the sample code to stop the timer count of the MTU2 channel 4 is executed.
When executing the sample code by changing the sample operation 1 and 2 or terminating the PWM1 sample code
operation of MTU2 by inputting "EXIT" + "Enter" keys, it should be executed after "STOP" + "Enter" keys are input to
stop the count operation.
Sample_MTU2_PWM1_Main
Output to terminal software
printf()
Obtain command list of PWM
sample processing for MTU2
Sample_MTU2_PWM1
_GetCmdList()
Obtain the command list of the sample processing for the MTU2
PWM waveform output. In this sample code, the menu list is
obtained to start the sample code for the MTU2 PWM waveform
output.
Register command list of
main processing
CommandSetCmdList()
Register the command list of the sample processing for the MTU2
PWM waveform output. In this sample code, the menu list is
registered to start the sample program for the MTU2 PWM
waveform output.
Wait for command input
gets()
Wait for command input from the terminal and store it in the
command buffer.
Analyze and execute
commands
CommandExe()
No "EXIT" input
Output the sample program version information of the MTU2 PWM
waveform output to the terminal running on the host PC.
Input "EXIT"?
Analyze and execute the contents of the command buffer. In the
sample code, this function branches to the sample code
processing for the MTU2 PWM waveform output according to the
commands input.
"1": Branch to the Sample_MTU2_PWM1 function
(Execute sample operation 1)
"2": Branch to the Sample_MTU2_PWM1_Inverse function
(Execute sample operation 2)
"STOP": Branch to the Sample_MTU2_PWM1_STOP function
"HELP": Display available commands
"EXIT" input
return (COMMAND_EXIT)
Figure 6.13 Sample Main Function to Output Waveforms in PWM Mode1 of MTU2
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Waveform Output by Using PWM Mode 1
6.9.4
Sample Function for PWM Waveform Output
Figure 6.14 shows the flowcharts of Sample Function for PWM Waveform Output.
Two types of samples are provided to output PWM waveforms.
In sample operation 1, the initial output level of output pin is set to "0", and the output levels at TGRA_4 compare
match and TGRB_4 compare match are respectively set to "0" and "1". The PWM waveforms with the values of
10ms/70%, 12ms/10%, 14ms/0%, 16ms/40%, 8ms/100%, and 4ms/100% which are set in the cycle and duty setting
table (mtu2_pwm_usertbl1[][]) are continuously output in this operation.
In sample operation 2, the initial output level of output pin is set to "1" and the output levels at TGRA_4 compare match
and TGRB_4 compare match are respectively set to "1" and "0". The PWM waveforms with the values of 10ms/30%,
12ms/90%, 14ms/100%, 16ms/60%, 8ms/0%, and 4ms/0% which are set in the cycle and duty setting table
(mtu2_pwm_usertbl2[][]) are continuously output in this operation.
Sample_MTU2_PWM1_Output
Specify channel and count clock
Specify operation for TGRA and
TGRB compare match
Specify cycle and duty setting table
Convert into register setting
values for cycle and duty
R_MTU2_PWM1_RegTblConv()
Specify channel 4 for the MTU2 channel used in PWM waveform output and
P0f/64 for the TCNT count clock.
Specify the level of waveform output when TGRA compare match and TGRB
compare match occur. Also specify cycle and duty setting table to be used.
Sample operation 1 : Set the initial output level to "0", and respective
output level of TGRA_4 compare match and
TGRB_4 compare match to "0" and "1"
The information stored in mtu2_pwm_usertbl1[][] is
used for cycle and duty.
Sample operation 2 : Set the initial output level to "1", and respective
output level of TGRA_4 compare match and
TGRB_4 compare match to "1" and "0"
The information stored in mtu2_pwm_usertbl2[][] is
used for cycle and duty.
Convert into the register values to output PWM waveform using the cycle (µs)
and duty (%) information.
Convert the contents of the cycle and duty setting table into the register
setting values, and store them in the setting table for TGRA_4 and TGRB_4
registers.
Initialize MTU2
R_MTU2_PWM1_Init()
Initialize MTU2 to run the specified channel, count clock and TGRA and
TGRB compare match operation.
Initialize PORT
MTU2_PWM1_PORT_Init()
Initialize the PORT used to output PWM waveforms.
In the sample code, TIOC4A pin is set to output PWM waveforms.
After setting the initial output level of TIOC4A pin by the initial setting of
MTU2, initialize the PORT.
Initialize table number in
register setting table
Start TCNT_4 count operation
R_MTU2_PWM1_Open()
Initialize the values of variable which indicate the table number in the setting table for
TGRA_4 and TGRB_4 registers. When the first TGRA_4 interrupt processing is
executed, the contents of the specified table number is set to the MTU2 buffer register.
The initial value of the table number varies depending on the amount of the cycle and
duty table information.
When the amount of table information is 3 or more
: mtu2_pwm_num ← 2
When the amount of table information is 2
: mtu2_pwm_num ← 0
Start timer count operation of MTU2 channel 4.
return (COMMAND_SUCCESS)
Figure 6.14 Sample Function for PWM Waveform Output
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Waveform Output by Using PWM Mode 1
6.9.5
Stop Function for PWM Waveform Output
Figure 6.15 shows the flowchart of Stop Function for PWM Waveform Output.
Sample_MTU2_PWM1_Stop
Stop MTU2 timer count
R_MTU2_PWM1_Close
Stop the timer count on MTU2 channel 4.
return
Figure 6.15 Stop Function for PWM Waveform Output
6.9.6
PORT Initial Setting Function
Figure 6.16 shows the flowchart of PORT Initial Setting Function.
In the sample code, P4_4 pin is set to be used as TIOC4A function.
MTU2_PWM1_PORT_Init
Set multiplexed pin functions of
PORT4
P4-related registers
PIBC44 bit ← 0
PBDC44 bit ← 0
PM44 bit ← 1
PMC44 bit ← 0
PIPC44 bit ← 0
PBDC44 bit ← 0
PFC44 bit ← 0
PFCE44 bit ← 1
PFCAE44 bit ← 0
PMC44 bit ← 1
PM44 bit ← 0
The multiplexed pin functions required for the usage of P4_4 as TOIC4A
output pin are set to output PWM waveforms on the MTU2 channel 4.
return
Figure 6.16 PORT Initial Setting Function
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Waveform Output by Using PWM Mode 1
6.9.7
TGRA_4 Interrupt Sample Function
Figure 6.17 shows the flowchart of TGRA_4 Interrupt Sample Function, which is generated by TGRA compare match.
The settings for cycle and duty of the MTU2 channel 4 are changed in this function.
In the sample code, this function is registered as the INTC handler by using the user-defined function
Userdef_MTU2_PWM1_Ch4_Init. The variable indicating table number is initialized by using the
Sample_MTU2_PWM1_Output function.
Sample_MTU2_PWM1
_TGI4A_Interrupt
Obtain information of the next cycle
and duty
TGInA interrupt processing
R_MTU2_PWM1
_TGInA_Interrupt()
Obtain values to be set to the registers for the next cycle and duty from the
setting table for TGRA and TGRB registers.
Set the values indicated by the variable with table number in the setting table
for TGRA and TGRB registers to the buffer register on MTU2 channel 4.
Increment variables with table number
The number of
variables with table number is
equal to or exceeds the amount of
table information?
mtu2_pwm_num is less than the amount of table information
mtu2_pwm_num is equal to or exceeds the amount of table information
Initialize variables with table number
mtu2_pwm_num ← 0
Clear the variables which indicate table number to "0".
return
Figure 6.17 TGRA_4 Interrupt Sample Function
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Waveform Output by Using PWM Mode 1
6.9.8
TGRB_4 Interrupt Sample Function
Figure 6.18 shows the flowchart of TGRB_4 Interrupt Sample Function.
This is the interrupt processing generated by TGRB_4 compare match, which avoids a change in waveform output at
the next TGRA_4 compare match. When the duty of the current PWM waveform is in the range between 1 and 99%,
the waveform with the duty of 100% for the next cycle is output in sample operation 1, and the waveform with the duty
of 0% for the next cycle in sample operation 2.
In the sample code, this function is registered as the INTC handler by using the user-defined function
Userdef_MTU2_PWM1_Ch4_Init.
Sample_MTU2_PWM1
_TGI4B_Interrupt
TGInB interrupt processing
R_MTU2_PWM1
_TGInB_Interrupt()
Set the value of TGRA_4 to TGRB_4 to avoid a change in
waveform at the next TGRA_4 compare match. The duty for
the next cycle should be controlled as follows.
Sample operation 1: Duty for the next cycle is 100%
Sample operation 2: Duty for the next cycle is 0%
return
Figure 6.18 TGRB_4 Interrupt Sample Function
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Waveform Output by Using PWM Mode 1
6.9.9
Converting Cycle and Duty into Register Setting Values
Figure 6.19 to Figure 6.21 show the flowcharts for converting cycle and duty into register setting values.
The cycle (µs) and duty (%) information specified in the cycle and duty setting table is converted into the values to be
set in TGRA and TGRB registers for MTU2 compare match, and the converted values are stored in the register setting
table.
In the sample code, the converted values are stored in the table as the information to be set in TGRA_4 and TGRB_4
registers.
R_MTU2_PWM1_RegTblConv
Error in specification by channel, tior_mode, p0clk_freq, and table_num
Argument error in function?
return (DEVDRV_ERROR)
Duty on top of
specified table is
NOT 100%?
Duty when the argument tior_mode specified MTU2_CMP_MATCH_A0_B1 is 100%
(Waveform output with the initial output level of "0" and with the respective output level of
TGRA compare match and TGRB compare match of "0" and "1")
return (DEVDRV_ERROR)
When the argument tior_mode is MTU2_CMP_MATCH_A1_B0, the conditional
expression varies. DEVDRV_ERROR" is returned when the duty is 0%.
(Waveform output with the initial output level of "1" and with the respective output level
of TGRA compare match and TGRB compare match of "1" and "0")
Calculate the time (µs) can be
generated by MTU2 using
cycle and count clock
Cycle of specified
table can be generated?
Calculate the time (in µs) that can be generated by MTU2 using P0f
frequency (in Hz) specified by the argument p0clk_freq and the count clock
specified by the argument cks.
Cycle can NOT be generated by using P0f and count clock
Cycle can be generated by using P0f and count clock
Convert the cycle information into the values to be set to the registers using
the frequency of P0f specified by the argument p0clk_freq and the count
clock specified by the argument cks.
Convert cycle (µs) information into
values to be set to registers
Register setting value
for cycle is settable?
Unsettable for cycle (Larger than H'FFFD)
Settable for cycle
Store values in register setting
table as cycle information
C
Store the converted values in the specified setting table for
TGRA and TGRB registers.
A
B
Figure 6.19 Converting Cycle and Duty into Register Setting Values (1/3)
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C
B
A
Duty in the table is more than 100%
Duty in specified table
is 100% or lower?
Duty in the table is in the range between 0 and 100%
Duty when the argument tior_mode specifies MTU2_CMP_MATCH_A0_B1 is 0%,
and the next duty is 100%
(Waveform output with the initial output level of "0" and with the respective output
level of TGRA compare match and TGRB compare match of "0" and "1")
Duty is 0% and next
duty is NOT 100%?
return (DEVDRV_ERROR)
When the argument tior_mode is MTU2_CMP_MATCH_A1_B0, the conditional
expression varies. "DEVDRV_ERROR" is returned when the duty is 100% and the
next duty is 0%.
(Waveform output with the initial value of "1" and with the respective output level of
TGRA compare match and TGRB compare match of "1" and "0")
Duty in the table is in the range between 1 and 100%
Duty is 0%?
Duty in the table is 0%
Store duty information for 0% in
register setting table
Store the register setting values to make the duty 0% in the setting table
for TGRA and TGRB registers.
The value where "1" is added to the register setting value of cycle is taken
as the register setting value of duty.
When the argument tior_mode is MTU2_CMP_MATCH_A1_B0, the
above value is specified at the duty of 100%.
Duty in the table is 100%
Duty is in range
of 1 and 99%?
Duty in the table is in the range
between 1 and 99%
Calculate time (µs) for duty from the cycle (µs) and
duty (%) information
When the argument tior_mode is
MTU2_CMP_MATCH_A1_B0, the calculation
formula varies.
Convert duty (%) information
into time (µs)
Duty in specified table
can be generated?
Duty can NOT be generated by using P0f and count clock
return (DEVDRV_ERROR)
Convert duty (%) information into
values to be set to registers
Store duty information in
register setting table
G
D
Convert the duty information into the values to be
set to the registers using the frequency of P0f
specified by the argument p0clk_freq and the count
clock specified by the argument cks.
Store the converted values into the specified
setting table for TGRA and TGRB registers.
E
F
Figure 6.20 Converting Cycle and Duty into Register Setting Values (2/3)
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G
D
E
F
Next duty in
table is 100%?
Next duty in the table is in the range
between 0 and 99%
Next duty in the table is 100%
Store duty information for 100%
in register setting table
Store duty information for 100%
in register setting table
Increment table index of
cycle and duty
Store the register setting values to make the duty
100% in the setting table for TGRA and TGRB
registers.
The same value as the register setting value of
cycle is stored as the register setting value of duty.
(When the argument tior_mode is
MTU2_CMP_MATCH_A1_B0, the above value is
specified at the next duty of 0%)
Store the register setting value to make the duty
100% in the setting table for TGRA and TGRB
registers.
The value where "2" is added to the register setting
value of cycle is stored as the register setting value
of duty.
(When the argument tior_mode is
MTU2_CMP_MATCH_A1_B0, the above value is
specified at the next duty in the range between 1
and 100%)
Increment the table index to convert the next cycle and duty information into
the register setting values.
Register values
of all information in table
have been converted?
return (ret)
Figure 6.21 Converting Cycle and Duty into Register Setting Values (3/3)
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6.9.10
MTU2 Initial Settings
Figure 6.22 shows the flowchart of MTU2 Initial Setting Function.
The values that can be specified for the argument cks differ depending on the channels because the selectable count
clocks vary by channel. See Chapter 4 "Peripheral Functions" for more details.
R_MTU2_PWM1_Init
Error in specification by channel,cks, and tior_mode
Argument error in function?
return (DEVDRV_ERROR)
Channel?
channel = 0
MTU2 channel 0 initial settings
Userdef_MTU2_PWM1
_Ch0_Init()
channel = 3
MTU2 channel 3 initial settings
Userdef_MTU2_PWM1
_Ch3_Init()
Initialize MTU2 by using the count clock specified by the
argument cks in operation state of TGRA and TGRB specified
by the argument tior_mode.
When the channel 0, 3, or 4 is specified for the argument
channel, the user-defined function corresponding to each
channel is called.
In the sample code, the MTU2 channel 4 and the interrupts of
TGRA channel 4 and TGRB channel 4 are initialized by using
the user-defined function Userdef_MTU2_PWM1_Ch4_Init
The user-defined functions for the MTU2 channel 0, 3, and
4 have been prepared, but the following functions are not
used in the sample code.
Userdef_MTU2_PWM1_Ch0_Init
Userdef_MTU2_PWM1_Ch3_Init
channel = 4
MTU2 channel 4 initial settings
Userdef_MTU2_PWM1
_Ch4_Init()
default
return (DEVDRV_SUCCESS)
Figure 6.22 MTU2 Initial Setting Function
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6.9.11
MTU2 Timer Count Start Function
Figure 6.23 shows the flowchart of MTU2 Timer Count Start Function.
R_MTU2_PWM1_Open
Argument error in function?
Error in specification by channel
return (DEVDRV_ERROR)
Channel?
channel = 0
Start MTU2 channel 0 timer count
TSTR register
CST0 bit ← 1
: Start TCONT_0 count operation
TSTR register
CST3 bit ← 1
: Start TCONT_3 count operation
TSTR register
CST4 bit ← 1
: Start TCONT_4 count operation
channel = 3
Start MTU2 channel 3 timer count
channel = 4
Start MTU2 channel 4 timer count
default
return (DEVDRV_SUCCESS)
Figure 6.23 MTU2 Timer Count Start Function
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6.9.12
MTU2 Timer Count Stop Function
Figure 6.24 shows the flowchart of MTU2 Timer Count Stop Function.
R_MTU2_PWM1_Close
Argument error in function?
Error in specification by channel
return (DEVDRV_ERROR)
Channel?
channel = 0
Stop MTU2 channel 0 timer count
TSTR register
CST0 bit ← 0
: Stop TCONT_0 count operation
TSTR register
CST3 bit ← 0
: Stop TCONT_3 count operation
TSTR register
CST4 bit ← 0
: Stop TCONT_4 count operation
channel = 3
Stop MTU2 channel 3 timer count
channel = 4
Stop MTU2 channel 4 timer count
default
return (DEVDRV_SUCCESS)
Figure 6.24 MTU2 Timer Count Stop Function
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6.9.13
TGInA Interrupt Function
Figure 6.25 shows the flowchart of TGInA Interrupt Function.
R_MTU2_PWM1_TGInA_Interrupt
Error in specification by channel
Argument error in function?
return (DEVDRV_ERROR)
Set next cycle to register
TGRC register ← cycle_reg
Set the register value for the cycle specified by the argument cycle_reg to the buffer register.
Set next duty to register
TGRD register ← duty_reg
Set the register value of the duty specified by the argument duty_reg to the buffer register.
Next duty is 100% (or 0%)?
duty_reg and cycle_reg are equal, or
duty_reg and the value where "2" is added to cycle_reg are equal
When the initial settings are made by using the R_MTU2_PWM1_Init function, the conditional
expression varies depending on the contents specified by the argument tior_mode.
MTU2_CMP_MATCH_A0_B1 is specified
: Next duty in the table is 100%
MTU2_CMP_MATCH_A1_B0 is specified
: Next duty in the table is 0%.
Read TGRA and TGRB registers
The values in the compare match registers are read to obtain duty
information of current waveform.
Obtain duty information of
current waveform
Duty of current
waveform is in the range
between 1 and 99%?
Duty of current waveform is 0% or 100%
Duty of current waveform is in the range between 1 and 99%
Clear interrupt source flag of
TGRB interrupt
Perform a dummy read of
TGRB interrupt source flag
Enable TGRB interrupt
Clear interrupt source flag of
TGRA interrupt
Perform a dummy read of
TGRA interrupt source flag
TSR register
TGFB bit ← 0
: Clear interrupt source flag of TGRB interrupt
TGFB is read (dummy read) before TGFB is cleared.
TSR register
Perform a dummy read of TGFB bit
TIER register
TGIEB bit ← 1
: Enable interrupt request generated by TGFB bit (TGIB)
TSR register
TGFA bit ← 0
: Clear interrupt source flag of TGRA interrupt
TGFA is read (dummy read) before TGFA is cleared.
TSR register
Perform a dummy read of TGFA bit
return (DEVDRV_SUCCESS)
Figure 6.25 TGInA Interrupt Function
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6.9.14
TGInB Interrupt Function
Figure 6.26 shows the flowchart of TGInB Interrupt Function.
R_MTU2_PWM1_TGInB_Interrupt
Argument error in function?
Error in specification by channel
return (DEVDRV_ERROR)
Set values to avoid a change in waveform
output at TGRA compare match
Disable TGRB interrupt
Clear interrupt source flag of
TGRB interrupt
Performa a dummy read of
TGRB interrupt source flag
TGRB register ← TGRA register
Set the vale of TGRA register to TGRB register to avoid a change in
waveform output at the next TGRA compare match.
TIER register
TGIEB bit ← 0
: Disable interrupt request generated by TGFB bit (TGIB)
TSR register
TGFB bit ← 0
: Clear TGRB interrupt source flag
TGFB is read (dummy read) before TGFB is cleared.
TSR register
Perform a dummy read of TGFB bit
return (DEVDRV_SUCCESS)
Figure 6.26 TGInB Interrupt Function
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6.9.15
MTU2 Channel 4 Initial Settings
Figure 6.27 to Figure 6.29 show the flowcharts of MTU2 Channel 4 Initial Settings. The API functions are used to
register the MTU2 channel 4 interrupt function as the INTC handler, to set the interrupt priority level, and to enable
interrupts. Refer to the RZ/A1H group application note Example of Initialization for details about the API functions
R_INTC_RegistIntFunc, R_INTC_SetPriority, and R_INTC_Enable for the INTC interrupts.
The functions for the MTU2 channel 0 and channel 3 have also been provided, but not used in the sample code. When
other channel except channel 4 is used, initial settings should be made by using the function of the channel used.
Userdef_MTU2_PWM1_Ch4_Init
MTU2 module standby
mode has not been cancelled?
MTU2 module standby mode has been cancelled
MTU2 module standby mode has not been cancelled
Cancel MTU2 module standby mode
Stop MTU2 channel 4 timer count
Clear MTU2 channel 4 timer counter
Select counter clock
STBCR3 register
MSTP33 bit ← 0
: Supply a clock to MTU2
TSTR register
CST4 bit ← 0
: Stop TCNT_4 count operation
TCNT_4 register ← H'0000
: Initialize timer count
TCR_4 register
: Set the count clock to the clock source specified by the argument cks
TPSC bit ← cks
In the sample code, P0f/64 is used as count clock.
Select edge of input clock
TCR_4 register
CKEG bit ← b'00
: Set the count by selecting rising edge of input clock
Select source for counter clear
TCR_4 register
CCLR bit ← b'001
: Clear TCNT at TGRA compare match
TOER register
OE4A bit ← 1
: Enable PWM waveform of TIOC4A pin to be output
Enable TIOC4A pin output settings
Set TGRA_4 and TGRB_4
operations
TIORH_4 register ← tior_mode
In the sample code, the output levels of TIOC4A pin are specified as follows
depending on the contents specified by the argument tior_mode.
When the argument tior_mode specifies MTU2_CMP_MATCH_A0_B1,
IOA bit ← b'0001
: Initial output level is "0", and output level at TGRA_4
compare match is "0"
IOB bit ← b'0010
: Output level at TGRB_4 compare match is "1"
When the argument tior_mode specifies MTU2_CMP_MATCH_A1_B0,
: Initial output level is "1", and output level at TGRA_4
IOA bit ← b'0110
compare match is "1"
IOB bit ← b'0101
: Output level at TGRB_4 compare match is "0"
A
Figure 6.27 MTU2 Channel 4 Initial Settings (1/3)
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A
TGRA_4 register ← mtu2_pwm_regtbl[0][0]
TGRB_4 register ← mtu2_pwm_regtbl[0][1]
Set the first cycle and duty information in the setting table for TGRA and TGRB registers
(mtu2_pwm_regtbl[][]).
The cycle value and the duty value are specified to TGRA_4 and TGRB_4 registers respectively.
In the sample code, the values are specified as follows.
Sample operation 1 : Set cycle to 10ms, and duty to 70%
Sample operation 2 : Set cycle to 10ms, and duty to 30%
Set cycle and duty to be output first
Set buffer operation
TMDR_4 register
BFA bit ← 1
BFB bit ← 1
: Combine TGRA and TGRC and set it to buffer operation
: Combine TGRB and TGRD and set it to buffer operation
Set transfer timing from
buffer register to TGR
TBTM_4 register
TTSA bit ← 1
TTSB bit ← 1
: Transfer to TGRA_4 register when TCNT_4 is cleared
: Transfer to TGRB_4 register when TCNT_4 is cleared
TGRC_4 register ← mtu2_pwm_regtbl[1][0]
TGRD_4 register ← mtu2_pwm_regtbl[1][1]
Set the second cycle and duty information in the setting table for TGRA and TGRB registers
(mtu2_pwm_regtbl[][]).
The cycle value and the duty value are specified to TGRC_4 and TGRD_4 registers respectively.
In the sample code, the values are specified as follows.
Sample operation 1 : Set cycle to 12ms, and duty to 10%
Sample operation 2 : Set cycle to 12ms, and duty to 90%
Set cycle and duty to be
secondly output
TMDR_4 register
MD bit ← b'0010
: Set to PWM mode 1
Set TCNT independent operation
TSYR register
SYNC4 bit ← 0
: TCNT_4 performs independent operation to other channels (0 to 3)
Enable TGRA_4 interrupt
TIER_4 register
TGIEA bit ← 1
: Enable interrupt request generated by TGFA bit (TGIA)
Set PWM mode
Second duty is not 100% (or 0%)
Second duty is
100% (or 0%)?
Second duty is 100% (or 0%)
Enable TGRB_4 interrupt
The conditional expression varies depending on the
contents specified by the argument tior_mode.
MTU2_CMP_MATCH_A0_B1
: Duty is 100%
MTU2_CMP_MATCH_A1_B0
: Duty is 0%
Disable TGRB_4 interrupt
The second duty is 100% when the argument tior_mode specifies MTU2_CMP_MATCH_A0_B1
The second duty is 0% when the argument tior_mode specifies MTU2_CMP_MATCH_A1_B0
TIER_4 register
TGIEB bit ← 1
:Enable interrupt request generated by TGFB bit (TGIB)
B
The second duty is in the range between 0 and 99% when the argument tior_mode specifies MTU2_CMP_MATCH_A0_B1
the second duty is in the range between 1 and 100% when the argument tior_mode specifies MTU2_CMP_MATCH_A1_B0
TIER_4 register
TGIEB bit ← 0
: Disable interrupt request generated by TGFB bit (TGIB)
Figure 6.28 MTU2 Channel 4 Initial Settings (2/3)
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B
Register TGI4A
interrupt handler
R_INTC_RegistIntFunc()
Set TGI4A interrupt
priority level
R_INTC_SetPriority()
Enable TGI4A interrupt
R_INTC_Enable()
Register TGI4B
interrupt handler
R_INTC_RegistIntFunc()
Set TGI4B interrupt
priority level
R_INTC_SetPriority()
Enable TGI4B interrupt
R_INTC_Enable()
Register MTU2 compare match 4A interrupt handler.
In the sample code, the handler function Sample_MTU2_PWM1_TGI4A_Interrupt is
registered to change the cycle and duty for the PWM waveform to be output next.
Set the priority level of MTU2 compare match 4A interrupt.
In the sample code, the interrupt priority level is set to "1".
Enable MTU2 compare match 4A interrupt.
Register MTU2 compare match 4B interrupt handler.
In the sample code, the handler function Sample_MTU2_PWM1_TGI4B_Interrupt is
registered to avoid a change in the waveform at the next TGRA compare match.
Set the interrupt priority level for MTU2 compare match 4B interrupt.
In the sample code, the interrupt priority level is set to "1".
Enable MTU2 compare match 4B interrupt.
return
Figure 6.29 MTU2 Channel 4 Initial Settings (3/3)
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6.10
Running Sample Code
The sample code is started by command input from the terminal on the host PC connected to the GENMAI board via
the serial interface.
After supplying power to the GENMAI board, the messages (1) in Figure 6.30 are output. To start the MTU2_PWM1
sample code, input "MTU2_PWM1" + "Enter" keys subsequent to "SAMPLE>" prompt. When the message (2) is
output, input "1" + "Enter" keys for the sample operation 1, or "2" + "Enter" keys for the sample operation 2 subsequent
to "MTU2_PWM1 SAMPLE>" prompt.
The sample code information (3) in Figure 6.30 is displayed when "HELP" + "Enter" keys are input. The MTU2 count
operation is stopped when "STOP" + "Enter" keys are input. The operation of the MTU2 PWM1 sample code is
terminated when "EXIT" + "Enter" keys are input. Switching between sample operation 1 and sample operation 2 and
terminating the MTU2_PWM1 sample code by "EXIT" + "Enter" keys should be done after the count operation has
been stopped by "STOP" + "Enter keys.
Ver.X.XX in Figure 6.30 indicates the version of the sample code main processing, and Ver.Y.YY indicates the version
of MTU2 PWM1 sample code.
Display messages
RZ/A1H CPU Board Sample Program. Ver.X.XX
Copyright (C) 2015 Renesas Electronics Corporation. All rights
reserved.
(1)
select sample program.
SAMPLE>
RZ/A1H Multi-Function Timer Pulse Unit2(MTU2) Sample Program. Ver.Y.YY
Copyright (C) 2015 Renesas Electronics Corporation. All rights
reserved.
(2)
select sample program.
MTU2_PWM1 SAMPLE>
MTU2_PWM1 SAMPLE> help
: PWM waveform output
- Initial output
- TGRA compare match
- TGRB compare match
2
: PWM waveform output
- Initial output
- TGRA compare match
- TGRB compare match
STOP : Stop MTU2_PWM1 sample
EXIT : Exit MTU2_PWM1 sample
(3)
1
: Output 0
: Output 1
: Output 1
: Output 1
: Output 0
: Output 0
MTU2_PWM1 SAMPLE>
Figure 6.30 Terminal Display when Sample Code in MTU2 PWM mode 1 is Startup
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Waveform Output by Using PWM Mode 1
7.
Notes
In the sample code, PWM waveforms for cycle and duty can be output by changing the contents of the cycle and duty
setting table (mtu2_pwm_usertbl1[][] in sample operation 1, and mtu2_pwm_usertbl2[][] in sample operation 2).
When changing the cycle and duty setting table, change the contents of the amount of the table information (constant
MTU2_USER_TABLE_NUM) at the same time. When changing the P0f frequency, change the content of constant
MTU2_P0_CLOCK_FREQ_Hz.
The following shows notes for changing cycle and duty values.
7.1
7.1.1
Notes for Changing Cycle and Duty Setting Values
Specifying Duty Value
The following shows notes for setting duty values.
• Sample operation 1
 The duty of initial output should not be 100%.
 The duty cannot be changed from 0% to 100%. It should pass through the range between 1 and 99% until the
duty is changed from 0% to 100%. The duty value in the table should be specified in order of 0% → 1 to 99% →
100%.
 Two or more sets of cycle and duty information should be prepared for the cycle and duty setting table. Sample
operation 1 cannot be performed when the amount of cycle and duty information is one.
• Sample operation 2
 The duty of initial output should not be 0%.
 The duty cannot be changed from 100% to 0%. It should pass through the range between 1 and 99% until the
duty is changed from 100% to 0%. The duty value in the table should be specified in order of 100% → 1 to 99%
→ 0%.
 Two or more sets of cycle and duty information should be prepared for the cycle and duty setting table. Sample
operation 2 cannot be performed when the amount of cycle and duty information is one.
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7.1.2
Time Calculated in Cycle and Duty Setting
P0f/1, P0f/4, P0f/16, and P0f/64 in channel 0, and P0f/1, P0f/4, P0f/16, P0f/64, P0f/256, and P0f/1024 in channels
3 and 4 can be specified for the MTU2 count clock. These can also be customized using the sample code.
In this sample code, cycles can be set in microsecond (μs) units to the cycle and duty setting table. The usable unit of
time and the maximum value for setting cycles differ depending on the count clock used.
• Usable unit of time for setting cycles
The usable unit of time for setting cycles is changed depending on the specified count clock. It can be calculated
using the following expression.
Usable unit of time (µs) for setting cycles
*1
= (uint32_t)( Calculated value (μs) for one count in sample code ) + 1
(Expression 1)
*1: Calculated value (μs) for one count in sample code
6
= (1 ÷ (uint32_t)( P0f (Hz) ÷ Division value of count clock ) ) × 10^
• Settable maximum value for cycles
The value to be set for cycles should satisfy the following expression that relates to the cycle setting value.
Cycle setting value (μs) ÷ Calculated value (μs) for one count in sample code - 1
*2
< ( Maximum value for cycle setting register(H'FFFD ) + 1 )
(Expression 2)
*2: When the duty outputs PWM waveforms with 0% or 100%, the value where 1 or 2 is added to the
cycle setting register is set to the duty setting register. Therefore, H'FFFD is set as the maximum
value of the cycle setting register and setting H'FFFE or a larger value is prohibited.
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Table 7.1 shows the usable unit of time and maximum value for setting cycles for each count clock when the P0f
frequency is 33.33MHz. In this sample code, the P0f frequency is set to 33.33MHz at the initial condition. The P0f
frequency varies depending on the settings of the input clock and the clock pulse generator. When using this sample
code with the P0f frequency other than 33.33MHz, the value to be set for cycles should be determined after the settable
time is calculated using the above expressions.
Table 7.1
Usable Unit of Time and Maximum Value for Setting Cycles when P0f is 33.33MHz
(about 33333333Hz)
Usable unit of time for setting cycles
Settable maximum value (μs)*
(µs)
P0f/1
1
1966
P0f/4
1
7864
P0f/16
1
31456
P0f/64
2
125826
P0f/256
8
503304
P0f/1024
31
2013233
Note: * The settable maximum value is the max value of integral multiples of the usable unit of time for
setting cycles that satisfies expression 2.
Count clock
When determining the values to be set in the cycle and duty setting table, it is recommended that the cycle values be set
so that the time for duty with 1% calculated from the cycle has multiples of "Usable unit of time for setting cycles"
shown in Table 7.1. The above setting allows the differences of the duty (%) set in the table to be within less than 1%
compared to the cycle.
There is a value that can be set as operable time (minimum value) to output PWM waveforms as well as "Usable unit of
time for setting cycles" and "Settable maximum value". It depends on the time occupied by TGRA_4 and TGRB_4
interrupt processing. Refer to the later described "7.1.4 TGRA_4 and TGRB_4 Interrupt Processing Time" to determine
the operable minimum value, usable unit of time for setting cycles, and maximum value for the system used. Note that
the values to be set to the cycle and duty setting table should also be determined.
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7.1.3
Differences between Cycle and Duty Setting Values and Output Waveforms
In this sample code, the register values to determine the MTU2 cycle and duty are calculated from the cycle (in
microsecond (μs) units) and duty (in 1% units) set in the table and used for operation, so there may be differences
between the setting values and the actual output waveform.
Causes of differences are as follows.
 Differences between setting values (μs) and count clock cycles
Differences may occur when the count clock is a divided P0f clock so that its cycle is not an exact
value of μs while the setting value is a period of increments of μs or 1% increments of the setting
value.
 Differences between actual count clock cycles and periods for one count used for calculation in sample code
Differences may occur when calculation in sample code is performed in integers and the calculated
value is rounded down so that it is different from the actual count clock cycle.
To calculate the cycle of the actual output waveform corresponding to the setting value, the following expressions are
used.
• Cycle setting value and cycle of waveform to be output
In this sample code, "Cycle (μs) of waveform to be output" can be calculated by obtaining "Cycle register value"
(register value to be set in TGRA_4) and multiplying with the period of one count with MTU2, using the following
expressions.
Cycle register value
*1
6
= (uint64_t)( ( (uint64_t)( MTU2 count clock (Hz) ) × Cycle (μs) ) ÷ 10^ )
-1
(Expression 3)
*1: MTU2 count clock (Hz) = ( P0f (Hz) ÷ Division value of count clock )
Cycle (μs) of waveform to be output
*2
= ( Cycle register value + 1 ) × Period (μs) for one count with MTU2
6
*2: Period (μs) for one count with MTU2 = ( 1 ÷ MTU2 count clock (Hz) ) × 10^
(Expression 4)
For example, if the P0f frequency is 33.33MHz (about 33333333Hz) and the division ratio is divided by 64, when the
cycle is set to 10000μs to run this sample code, "Cycle register value" and "Cycle (μs) of waveform to be output" can be
calculated as follows, using expression 3 and expression 4.
Cycle register value
6
= (uint64_t)( ( ( (uint64_t)( 33333333 (Hz) ÷ 64 ) × 10000 (µs) ) ÷ 10^ ) - 1
6
= (uint64_t)( ( 520833 (Hz) × 10000 (µs) ) ÷ 10^ ) - 1
= (uint64_t)( 5208.33 ) - 1
= 5207
Cycle (μs) of waveform to be output
6
≅ ( 5207 + 1 ) × ( 1 ÷ 520833.32 (Hz) ) × 10^
-6
6
≅ 5208 × ( 1.92 × 10^ ) × 10^
≅ 9999.36 (µs)
Although the setting value is 10000μs, the cycle of the waveform to be output is 9999.36μs because "(uint64_t)
(5208.33) - 1" is rounded down to 5207 when calculating the cycle register value.
This difference is "Period (μs) for one count with MTU2" at a maximum, so it becomes smaller when the count clock is
set to a shorter cycle.
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
• High width (μs) of waveform to be output and high width (μs) calculated from duty setting value
The duty of this sample code is used to determine the percentage (%) of High width per cycle. "High width (μs)
converted from duty setting value" can be calculated by the following expression.
High width (μs) converted from duty setting value
*1
= Cycle setting value (μs) × (Duty setting value (%) ÷ 100)
(Expression 5)
*1: In the above calculation, the value is rounded up to an integer in sample operation 1, and
rounded down in sample operation 2. This is because the register value that sets the first-half
Low of the cycle is obtained by rounding down (High is rounded up as the result) in sample
operation 1, and the register value that sets the first-half High of the cycle is obtained by
rounding down the value in sample operation 2.
The register value to be set in TGRB_4 to generate a waveform with the specified duty is calculated using the same
approach as the above expression 3.
At this time, in sample operation 2, "Cycle (μs)" in expression 3 should be replaced with the High width (μs)
converted from "Duty setting value" calculated by expression 5. In sample operation 1, this value is the first-half
Low with of the cycle.
"High width (μs) of waveform to be output" is also calculated using the same approach as expression 4.
At this time, in sample operation 1, "Cycle register value" is replaced with the register value to be set in TGRB_4 to
generate a waveform with the specified duty.
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
7.1.4
TGRA_4 and TGRB_4 Interrupt Processing Time
In this sample code, when MTU2 is set to buffer operation, TGRC_4 and TGRD_4 are used as buffer registers for
TGRA_4 and TGRB_4. In the TGRA_4 compare match interrupt processing, the setting values of cycle and duty are
obtained from the setting table for TGRA_4 and TGRB_4 registers every time an interrupt occurs to perform PWM
waveform output by using sequential updating of the buffer registers.
Note that when the duty of the current cycle is in the range between 1 and 99% and the duty for the next cycle is 100%,
the value of TGRA_4 is set to TGRB_4 during TGRB_4 interrupt processing for the current cycle to avoid a change in
the output level of the waveform at the time of switching to the next cycle, and PWM waveform with the duty of 100%
can be output accordingly (in sample operation 2, PWM waveform is output when the current cycle is in the range
between 1 and 99% and the duty for the next cycle is 0%).
For these reasons, the time information* of cycle and duty specified for "cycle and duty setting table" should be
specified to satisfy the relational expression described later.
Figure 7.1 shows the Processing Time and Compare Match Generation Timing using TGRB_4 and TGRB_4 Interrupts.
Note: *
The duty in "cycle and duty setting table" is shown in % unit, but it should be converted into time
information to consider the time occupied by interrupt.
Figure 7.1
Interrupts
Processing Time and Compare Match Generation Timing using TGRB_4 and TGRB_4
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
The respective time period indicated by "a", "b", "c", and "d" shown in Figure 7.1 defines the interrupt processing time,
the period of low width in the cycle, and duty time information. The cycle and duty should be set to satisfy the
conditions below.
Setting for cycle
Setting for duty
:
:
c + d < cycle
(c < a) & (d < b)
Note that the interrupt processing time depends on memory allocation of a program, CPU, and operating frequency of a
memory, therefore, the settings for cycle and duty should be decided in consideration of these conditions. If an interrupt
request with higher priority level than TGRA_4 and TGRB_4 interrupts is generated during the interrupt processing, the
time period for such interrupt processing should be taken into account.
When this sample code is operated under the conditions listed in Section 2 "Operation Confirmation Conditions", the
TGRA_4 and TGRB_4 interrupt processing time in initial state of the sample code should be;
c (TRGA_4 interrupt processing time): about 90μs
d (TGRB_4 interrupt processing time): about 60μs
The above information can be applied as a reference to review the settings of cycle and duty.
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
8.
Sample Code
Sample code can be downloaded from the Renesas Electronics website.
9.
Reference Documents
User's Manual: Hardware
RZ/A1H Group User's Manual: Hardware
The latest version can be downloaded from the Renesas Electronics website.
R7S72100 RTK772100BC00000BR (GENMAI) User's Manual
The latest version can be downloaded from the Renesas Electronics website.
ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition Issue C
The latest version can be downloaded from the ARM website.
ARM Generic Interrupt Controller Architecture Specification Architecture version 1.0
The latest version can be downloaded from the ARM website.
ARM CortexTM-A9 (Revision: r3p0) Technical Reference Manual
The latest version can be downloaded from the ARM website.
ARM CoreLinkTM Level 2 Cache Controller L2C-310 (Revision: r3p2) Technical Reference Manual
The latest version can be downloaded from the ARM website.
Technical Update/Technical News
The latest information can be downloaded from the Renesas Electronics website.
User's Manual: Development Tools
ARM Software Development Tools (ARM Compiler toolchain, ARM DS-5 etc.) can be downloaded from the ARM
website.
The latest version can be downloaded from the ARM website.
R01AN1979EJ0100 Rev.1.00
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Multi-Function Timer Pulse Unit 2
Waveform Output by Using PWM Mode 1
Website and Support
Renesas Electronics Website
http://www.renesas.com/
Inquiries
http://www.renesas.com/contact/
All trademarks and registered trademarks are the property of their respective owners.
R01AN1979EJ0100 Rev.1.00
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Revision History
Rev.
Rev.0.81
Rev.1.00
Date
Aug 08, 2014
Oct 16, 2015
Page
-
P22
P23
P24
P42
Description
Summary
First edition issued
Reflected the update contents of "RZ/A1H Group Example of
Initialization Rev.1.01" application note.
• Table 6.6 Sections Used (1/2)
Changed the execution area for the CODE_IO_REGRW
section in the table from "FLASH" to "LRAM".
• Table 6.7 Sections Used (2/2)
Added the CODE_CACHE_OPERATION section to the
table.
Added precautions about the CODE_CACHE_OPERATION
section to Note 3.
• Figure 6.10 Section Assignment
Provided information due to the CODE_IO_REGRW section
arrangement being changed and the
CODE_CACHE_OPERATION section being added.
• Figure 6.14 Sample Function for PWM Waveform Output
In order to initialize the PORT after setting the initial output
level of TIOC4A pin, change the processing procedure to
call the MTU2_PWM1_PORT_Init function after calling the
R_MTU2_PWM1_Init function.
A-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that
have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accordance with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation with an
unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an
associated shoot-through current flows internally, and malfunctions occur due to the false
recognition of the pin state as an input signal become possible. Unused pins should be handled as
described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register settings and
pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins
are not guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function
are not guaranteed from the moment when power is supplied until the power reaches the level at
which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do not access
these addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become stable.
When switching the clock signal during program execution, wait until the target clock signal has
stabilized.
 When the clock signal is generated with an external resonator (or from an external oscillator)
during a reset, ensure that the reset line is only released after full stabilization of the clock signal.
Moreover, when switching to a clock signal produced with an external resonator (or by an external
oscillator) while program execution is in progress, wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to a product with a different part number, confirm
that the change will not lead to problems.
 The characteristics of an MPU or MCU in the same group but having a different part number may
differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect
the ranges of electrical characteristics, such as characteristic values, operating margins, immunity
to noise, and amount of radiated noise. When changing to a product with a different part number,
implement a system-evaluation test for the given product.
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
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3.
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assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
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Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
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9.
Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
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contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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