NCVDES-2011 at CSIR-CEERI, Pilani
(October 12-14, 2011)
Time Slots for the Presentation of the Papers
P. 6B.1 P. 6B.2 P. 6B.3 P. 6B.4 P. 6B.5 P. 6B.6 P. 6B.7 Conference Room P. 6A.1 P. 6A.2 P. 6A.3 P. 6A.4 P. 6A.5 P. 6A.6 P. 6A.7 Old Auditorium TEA/ COFFEE LUNCH P. 9B.1 P. 9B.2 P. 9B.3 P. 9B.4 P. 9B.5 P. 9B.6 P. 9B.7 P. 9B.8 TEA/ COFFEE INVITED LECTURE INVITED LECTURE PANEL DISCUSSION Conference Room Conference Room LUNCH Old Auditorium P. 7A.1 P. 7B.1 P. 7A.2 P. 7B.2 P. 7A.3 P. 7B.3 P. 7A.4 P. 7B.4 P. 7A.5 P. 7B.5 P. 7A.6 P. 7B.6 P. 7B.7 TEA/COFFEE P. 8A.1 P. 8B.1 P. 8A.2 P. 8B.2 P. 8A.3 P. 8B.3 P. 8A.4 P. 8B.4 P. 8A.5 P. 8B.5 P. 8A.6 P. 8B.6 P. 8A.7 P. 9A.1 P. 9A.2 P. 9A.3 P. 9A.4 P. 9A.5 P. 9A.6 P. 9A.7 Conference Room PRESENTATION FROM EXHIBITORS DAY 3 : Oct. 14, 2011 Old Auditorium INVITED LECTURE Old Auditorium INVITED LECTURE Old Auditorium DAY 2 : Oct. 13, 2011 Old Auditorium Main Auditorium Old Auditorium Old Auditorium Main Auditorium Time Slot DAY 1 : Oct. 12, 2011
08:45 – 09:00 REGISTRATION 09:00 – 09:15 09:15 – 09:30 INAUGURATION 09:30 – 09:45 09:45 – 10:00 10:00 – 10:15 10:15 – 10:30 10:30 – 10:45 10:45 – 11:00 11:00 – 11:15 HIGH TEA 11:15 – 11:30 11:30 – 11:45 INVITED LECTURE 11:45 – 12:00 12:00 – 12:15 INVITED LECTURE 12:15 – 12:30 12:30 – 12:45 P.2.1 12:45 – 01:00 P.2.2 01:00 – 01:15 P.2.3 01:15 – 01:30 P.2.4 01:30 – 01:45 LUNCH 01:45 – 02:00 02:00 – 02:15 02:15 – 02:30 INVITED LECTURE 02:30 – 02:45 02:45 – 03:00 INVITED LECTURE 03:00 – 03:15 03:15 – 03:30 P. 3.1 03:30 – 03:45 P. 3.2 03:45 – 04:00 P. 3.3 04:00 – 04:15 P. 3.4 04:15 – 04:30 TEA/COFFEE 04:30 – 04:45 FELICITATION 04:45 – 05:00 PROGRAMME 05:00 – 05:15 BY IETE PILANI 05:15 – 05:30 CENTRE 05:30 – 05:45 05:45 – 06:00 06:00 – 06:15 06:15 – 06:30 DEPARTURE OF DELEGATES 1 Presentation
Slot No.
Paper Ref.
No.
Paper Title
P.2.1
NCVDES_S05_35
P.2.2
NCVDES_S01_12
P.2.3
NCVDES_S01_29
Next Generation Real
Time Distributed
Embedded Systems
Design and Analysis of
Optimum Performance
Memory Decoders
Optimization of
Compression and Scan
Power with Adaptive Bit
Filling and Dijkstra
Algorithm Based
Reordering
Design of A
Reconfigurable Zero IF
Filter For Wireless
Applications
Author (s)
Affiliation (s)
Session 2: Embedded Systems – I
P.2.4
NCVDES_S01_32
P.3.1
NCVDES_S05_24
P.3.2
NCVDES_S05_28
P.3.3
NCVDES_S04_30
P.3.4
NCVDES_S01_13
P. C. Jain
C-DAC, Noida, Uttar Pradesh.
Paurush Bhulania1,
Arti Noor2, Sampath
Kumar V3
Harikrishna Parmar1,
Usha Mehta2,
1
N.M. Devashrayee2
V.Ramakrishna,
P.Eswara Rao,
W.S Khokle
ASET, Amity University,
Noida, 2CDAC,
Noida, 3 JSS, Noida.
1
C.K.Pithawalla college of
Engineering & Technology,
Surat, 2 Nirma University,
Ahmedabad.
VNIT Nagpur.
Session 3: VLSI Architectures
Design and
Implementation of AES
RTL model in SystemC
and verification in System
Verilog
Moving Object Tracking
using Kernel based Mean
Shift
M.Nagaraju,
B.Srinivasu
National Institute of
Technology, Calicut,
Kerala.
Manoj Pandey1,
P C Upadhayay2,
Kota Solomon Raju3,
Nirankar Pandey1
1
Design, interface and
implementation of IEEE754 FPU on AHB in
LEON3
Design of High Speed
Booth Wallace Multiply
and Accumulate Unit
Nagendra Gajjar1, K
S Dasgupta2, N M
Devashrayee1
Naveen Kumar,
Manu Bansal
B K Birla Institute of
Engineering & Technology,
Pilani, 2Sant Longowal Institute
of Engineering & Technology,
Sangrur, Punjab, 3CSIR-CEERI,
Pilani.
1
Nirma University, Ahmedabad,
2
Indian Institute of Space
Science and Technology,
Thiruvananthapuram.
Thapar University, Patiala.
Session 6A: Embedded Wireless & Sensor Networks
P.6A.1
NCVDES_S05_39
Implementation of MultiChannel GPS Receiver
Base Band Modules
Kota Solomon Raju2,
Y. Pratap1, Virendra
Patel1, Gaurav
Kumar2, P. Bhanu
Prasad2, S. Mohan
Naidu1, Amit
Patwardhan1,
Rabinder Henry1
1
IIIT, Pune, 2CSIR-CEERI,
Pilani.
P.6A.2
NCVDES_S05_40
Industrial Ball Mill Control
Using Wireless Sensor
Network
Satish Mohanty,
Vikrant Mishra,
Vipin Kumar, P.
Bhanu Prasad,
Kota Solomon Raju
CSIR-CEERI, Pilani.
2 P.6A.3
NCVDES_S06_52
P.6A.4
NCVDES_S06_53
P.6A.5
NCVDES_S06_55
P.6A.6
NCVDES_S06_56
P.6A.7
NCVDES_S05_45
P.6B.1
NCVDES_S02_14
New High performance
BiCMOS Inverter
P.6B.2
NCVDES_S02_15
Design of Read-Out
Integrated Circuit for
ISFET based pH sensor
with On-Chip Temperature
compensation for
Biomedical Applications
A Novel topology of
CMOS second generation
current conveyor
An Area Efficient Inverter
Based Comparator Design
for Pipeline ADC in
0.35um CMOS
Technology
Low power, Low cost and
Faster Flash ADC
Node Properties Dependent
Analysis of Sensor
Network for Battlefield
Application
Energy Aware WSN Node
- For Agricultural
Application
WSN and GSM based
Smart Energy Management
System
WSN Based TMR Security
System for Sanitation
Workers
Mine-wide Wireless
Communication System for
Underground Coal Mines
Gourav Verma,
Deepika Ramaiya
Northen India Engineering
College, Delhi.
Kshitij Shinghal1,
Arti Noor2, Neelam
Srivastava3, Raghuvir
Singh4
G S S Chalapathi,
Debabrata Sikdar,
V K Chaubey
Debabrata Sikdar, G
S S Chalapathi, V K
Chaubey
Srinath K., Santosh,
Ravindra S. Chauhan,
S. Kumar,
AH Kiranmayee,
PC Panchariya,
P. Bhanuprasad,
S. Raghunath
1
M.I.T, Moradabad, 2C-DAC,
Noida, 3I.E.T, Lucknow,
4
Shobhit University, Meerut.
BITS-Pilani.
BITS-Pilani.
CSIR- CEERI, Pilani.
Session 6B: Analog and Mixed Signal Design – I
P.6B.3
NCVDES_S02_16
P.6B.4
NCVDES_S02_17
P.6B.5
NCVDES_S02_18
P.6B.6
NCVDES_S02_19
P.6B.7
NCVDES_S03_07
P.7A.1
NCVDES_S01_10
P.7A.2
NCVDES_S01_11
High Resolution, High
Speed And Low Power
CMOS Comparator
Timing Analysis of Buffer
Driven RLC Interconnect
In Sub-Threshold Regime
Harshit Agarwal,
Ashwani Rana, Yash
Agarwal
Megha Agrawal1,
Nidhi Agrawal1,
Anil K. Saini2,
Alpana Agarwal1
National Institute of
Technology, Hamirpur.
Amisha P.Naik,
N.M.Devashrayee
Institute of Technology, Nirma
University, Ahmedabad.
K C Behera, M
Santosh,
S C Bose
CSIR-CEERI, Pilani, Rajasthan.
Ankit R Kalband,
Divyesh Dixit, P.
Eswara Rao
Wazir Singh,
Alpana Agarwal
VNIT, Nagpur.
Rohit Dhiman,
Rajeevan Chandel
National Institute of
Technology, Hamirpur.
1
2
Thapar University, Patiala,
CSIR-CEERI, Pilani, Rajasthan.
Thapar University, Patiala.
Session 7A: Digital Logic and Circuit Design
A New Low-Power Circuit
Technique for Domino
CMOS Logic
A Low Power Circuit
Technique for Feedthrough
Logic
Preetisudha Meher,
Kamala Kanta
Mahapatra
Sauvagya Ranjan
Sahoo, Kamala Kanta
Mahapatra
National Institute of
Technology, Rourkela.
National Institute of
Technology, Rourkela
3 P.7A.3
NCVDES_S01_49
P.7A.4
NCVDES_S01_48
P.7A.5
NCVDES_S03_62
P.7A.6
NCVDES_S01_08
P.7B.1
NCVDES_S04_23
P.7B.2
NCVDES_S04_25
P.7B.3
NCVDES_S04_26
P.7B.4
NCVDES_S04_41
Development of Bitstream
Relocation Software Tool
P.7B.5
NCVDES_S05_27
P.7B.6
NCVDES_S01_09
QOS for a Hybrid Satellite
DVB Wireless Network
With Fade Mitigation
Ultra low power 32nm
SRAM cell architecture
with improved stability
P.7B.7
NCVDES_S00_68
P.8A.1
NCVDES_S03_02
Reliability Analysis of
Different Types of Fault
Tolerant Circuits
Power Efficient CMOS
Based Reversible Logic
Circuit Using Adiabatic
Switching Principles
An Exploration of VLSI
parallel Adder using
Carbon NanoTube Field
Effect Transistor
Study of performance of
Adiabatic Carry Look
Ahead Adder Using
Dynamic CMOS Logic
Deepti Shinghal
M.I.T, Moradabad.
Amit Saxena, Kshitij
Shinghal
M.I.T, Moradabad.
Sneh Lata Murotiya,
Anu Gupta
BITS, Pilani, Rajasthan
G.S.Tripathi, Shiv
Prakash Arya, Rajan
Mishra, Amit Kumar
M.M.M. Engg. College
Gorakhpur, Uttar Pradesh.
Session 7B: Embedded Architectures - I
Design of Reversible
Multiplier Architecture
using Vedic Mathematics
Design and
Implementation of a High
Performance SATA II Host
Controller IP Core
Design and
Implementation of a slot
machine using VHDL
codes
Design VHDL
Implementation of OSPA
algorithm: A Hash Based
Password Authentication
H.P.Shukla1,
A.G.Rao1,
R.K.Tiwari2
Jaya S, Sherin MA,
Krishna Kumar Rao,
Biju C. Oommen
Vineet Chabbra,
Shivam Sachdev,
Ashutosh Gupta,
Garima Bandhawakar
Wakhle
Kota Solomon Raju,
Divyam Mishra,
Vaibhawa Mishra,
Pramod Kumar
Tanwar, Kishore
Babu J.,K. Ranjit
Kumar, P. Bhanu
Prasad
Pankaj Palta, Sonia
Goyal
Geetika Srivastava1,
R.K. Chauhan2,
1
AMITY University
Uttar Pradesh,
Lucknow
Kamlesh Dutta,
Achal Maloo,
Radhika Kashyap,
Gaurav Arya
1
DOEACC Society, Gorakhpur
Centre, 2R.M.L. University
Faziabad.
Centre for Development of
Advanced
Computing,
Thiruvananthapuram.
Amity School of Engineering
and Technology, Amity
University, Uttar Pradesh.
CSIR-CEERI, Pilani.
Punjabi University, Patiala.
2
MMM Engineering College
Gorakhpur, Uttar Pradesh.
N.I.T, Hamirpur.
Session 8A: Analog and Mixed Signal Design – II
Analysis of Short Channel
Effects in MOSFET using
COMSOL and TANNER
EDA Tools
Yash Agrawal,
Rajeevan Chandel,
Rohit Dhiman,
Harshit Agarwal
National Institute of
Technology, Hamirpur.
4 P.8A.2
NCVDES_S02_20
Low Power Folding and
Interpolating ADC using
Cascaded Folding
Amplifier
Shruti Oza1,
N.M.Devashrayee2
1
P.8A.3
NCVDES_S02_50
An optimal design of low
power low phase noise LC
VCO using CMODE
P K Rout1, U K
Nanda1, D P
Acharya1, G Panda2
P.8A.4
NCVDES_S02_54
An Enhanced Recyclic
Folded Cascode OTA
NIT, Tiruchirapalli.
P.8A.5
NCVDES_S02_63
P.8A.6
NCVDES_S02_57
Improved Phase Selection
Circuit to avoid false
locking in Delay Locked
Loop
Exploration of sampling
methods for accurate
analog behavioral models
S.Kumaravel,
B.Venkataramani,
Rajendra Prasad
Ponnada,
Ramakrishna Chowtri
Mola Srinivasarao,
Sachin Maheshwari
MNIT, Jaipur, Rajasthan.
P.8A.7
NCVDES_S02_65
A Fully Differential GainBoosted Folded-Cascode
OPAMP with Constant
Gain in ICMR
Pramod Khandelwal,
Lokesh Garg,
D. Boolchandani,
Vineet Sahula
Anil Singh, Sunny
Sharma, Alpana
Agarwal
P.8B.1
NCVDES_S04_42
Implementation of
Dynamically
Reconfigurable Systems
On Chip with Operating
System Support
P.8B.2
NCVDES_S04_37
Lossless Data Compression
Using LZ77 and Huffman
Algorithm Using LEON3
P.8B.3
NCVDES_S04_38
P.8B.4
P.8B.5
Kalol Institute of Technology &
Research Centre, Gujarat, 2ITNirma University of Science &
Technology,
Ahmedabad,
Gujarat.
1
NIT Rourkela, 2School of
Electrical Sciences, IIT,
Bhubaneswar.
BITS, Pilani, Rajasthan.
Thapar University, Patiala.
Session 8B: Embedded Architectures – II
Kota Solomon Raju,
Vaibhawa Mishra,
Pramod Kumar
Tanwar, P. Bhanu
Prasad, Divyam
Mishra, Rita Nagar,
Manipati Rajesham,
N. Sowjanya Mergu,
K. Ranjit Kumar
Ashish Mishra1,
Solomon Raju Kota2
CSIR-CEERI, Pilani.
Designing a Matrix
Multiplier for Image
Processing Applications
Preeti Mishra1,
Atanendu Sekhar
Mandal2, Ravi Saini2
1
BITS-Pilani, 2CSIR-CEERI,
Pilani.
NCVDES_S04_47
Hardware Architecture for
Memory Efficient,High
Speed and Low
Complexity 2D DWT
C. S. Birajdar,
Y. V. Joshi,
S. Subbaraman
Walchand College of
Engineering, Sangli, Maharastra.
NCVDES_S04_51
FPGA Implementation of
Viterbi Algorithm &
Adaptive Viterbi
Algorithm for normal and
turbo coded data
R.Gokul
Subramanian, Aditya
Narayan,
V.K.Chaubey
BITS, Pilani.
1
BITS-Pilani, 2CSIR-CEERI,
Pilani
5 P.8B.6
NCVDES_S04_66
P.9A.1
NCVDES_S03_01
P.9A.2
NCVDES_S03_03
P.9A.3
NCVDES_S03_04
P.9A.4
NCVDES_S03_05
P.9A.5
NCDVES_S00_67
P.9A.6
NCVDES_S03_06
P.9A.8
NCVDES_S03_59
P.9B.1
NCVDES_S05_36
RTL Synthesis of
Transmitter & Receiver for
OFDM Based WLAN
(IEEE 802.11a)
B.Srinivasu1,
M.Nagaraju2
P.9B.2
NCVDES_S05_43
Design and Development
of Embedded Real-Time
System on ARM for
Desktop Micro-factory
Control Application
P.9B.3
NCVDES_S05_44
Classification of Alcohols
Using Electronic Nose
P.9B.4
NCVDES_S04_21
A Frequency Dependent
Algorithm for
Enhancement of
Degraded Speech
Himanshu Dutt
Sharma1, Hapreet
Singh1, Harish
Maheshwari1,
Omprakash Suthar1,
Amit Tholia1, Vijay2,
Nagahanumaiha2
Ravindra Singh
Chauhan, Santosh
Kumar, AH
Kiranmayee, PC
Panchariya
Navneet Upadhyay1,
Abhijit Karmakar2
Reconfiguration
Approaches for Low
Power Design on FPGA
based systems: Case Study
of ATM Cell-Assembler
Alok Sharma, Vineet
Sahula
MNIT Jaipur.
Session 9A: Device Modeling and Process Technology
Fin-Width Variability
Comparison of Tri-Gate
And Double Gate NanoScale FinFets
Effect of Channel
Engineering on SOI
MOSFET Characteristics
using TCAD Simulation
Impact of Gate Structure
on Magnetic Field Effect
Transistor (MegFET)
Gate Engineering in
Double Gate MOSFETs to
Optimize the on/off
Current Ratio
Electro-thermal simulation
of spiral micro-heaters for
low power gas sensing
applications
Process Variation in
Nanometer Technology - A
Review
Improvement in CMOS
Nano-Scale CMOS Device
Design for Low Power
Applications
Abhimanyu Chawla1,
B. Prasad1 and S. C.
Bose2
1
Kurukshetra University,
Kurukshetra, Haryana, 2CSIRCEERI, Pilani
Madhusudan Singh,
Ashwani K. Rana
National Institute of
Technology, Hamirpur.
Rakesh Kumar,
Ashwani K. Rana
National Institute of
Technology, Hamirpur.
Vinay Kumar Yadav,
Ashwani K. Rana
National Institute of
Technology, Hamirpur.
Dinesh Kumar, B.
Prasad, Vineet
Bansal, Mukesh
Kumar
M.Sonwani,
T.Chaudharry, S.
Jagarlamudi
Shubhi Kansal,
Banasthali
Vidyapeeth
Kurukshetra University,
Haryana.
National Institute of
Technology, Hamirpur.
Banasthali, Rajasthan.
Session 9B: Embedded Systems – II
1
Shri Vishnu Engineering
College For Women,
Bhimavaram, A.P, 2National
Institute of Technology -Calicut,
Kerala.
1
CSIR-CEERI, Pilani, 2CSIRCMERI, Duragapur, West
Bengal.
CSIR-CEERI, Pilani.
1
BITS-Pilani, 2CSIR-CEERI,
Pilani.
6 P.9B.5
NCVDES_S05_46
Microcontroller based low
cost turbidity meter
P.9B.6
NCVDES_S05_31
Design and Analysis of
FPGA Based Stepper
Motor Driver
P.9B.7
NCVDES_S05_34
P.9B.8
NCVDES_S05_33
Ankur Arora, Atul
Kumar Garg, AH
Kiranmayee, PC
Panchariya
Ambuj Agarwal,
Rajeevan Chandel
CSIR-CEERI, Pilani.
RFID Based Time
Attendance System
Santosh Kumar Das,
Sucharita Jena
National Institute of Technology
Rourkela, Odisha.
Design And Analysis Of
VLSI Chips Using
Ethernet As A Protocol
Dishant Khosla,
Amandeep Kaur
Punjabi University, Patiala
National Institute of
Technology, Hamirpur.
7