// Hello World!
UP_COUNTER
`define WAY_NO1
module UP_COUNTER_hello_world(clock,reset,value_now);
input clock,reset;
output [7:0]value_now;
reg [7:0]value_now;
// Q value for flip-flops
`ifdef WAY_NO1 // 指定 D 的方法<1> -> Combinational circuit
wire [7:0]value_now_d; // D value for flip-flops
assign value_now_d=reset?8'b0:(value_now+1'b1);
// 指定 D 的方法<2> -> Combinational circuit
`else
reg [7:0]value_now_d; // D value for flip-flops
always@(reset or value_now)
begin
if(reset)
begin
vaule_now_d=8'd0;
end
else
begin
value_now_d=value_now+1'b1;
end
end
`endif
// 在 clock 的 positive edge 時, 把 D 傳給 Q, 完成暫存器轉移 -> sequential circuit
always@(posedge clock)
begin
value_now<= value_now_d;
end
module UP_COUNTER_max(clock,reset,max,value_now);
input clock,reset,max;
output [7:0]value_now;
reg [7:0]value_now;
// Q value for flip-flops
reg [7:0]value_now_d; // D value for flip-flops
always@(reset or value_now or max)
begin
if(reset)
begin
value_now_d=8'd0;
end
else if(max)
begin
value_now_d=8'd255;
end
else
begin
value_now_d=value_now+1'b1;
end
end
// 在 clock 的 positive edge 時, 把 D 傳給 Q, 完成暫存器轉移 -> sequential circuit
always@(posedge clock)
begin
value_now<= value_now_d;
end
endmodule
module UP_COUNTER_max_freeze(clock,reset,max,freeze,value_now);
input clock,reset,max,freeze;
output [7:0]value_now;
reg [7:0]value_now;
// Q value for flip-flops
reg [7:0]value_now_d; // D value for flip-flops
always@(reset or value_now or max or freeze)
begin
if(reset)
begin
value_now_d=8'd0;
end
else if(freeze)
begin
value_now_d=value_now; // 把 Q 又 assign 給 D
end
else if(max)
begin
value_now_d=8'd255;
end
else
begin
value_now_d=value_now+1'b1;
end
end
// 在 clock 的 positive edge 時, 把 D 傳給 Q, 完成暫存器轉移 -> sequential circuit
always@(posedge clock)
begin
value_now<= value_now_d;
end
endmodule
module
UP_COUNTER_max_freeze_pre_load(clock,reset,max,freeze,pre_load,pre_load_val,
value_now);
input clock,reset,max,freeze,pre_load;
input [7:0]pre_load_val;
output [7:0]value_now;
reg [7:0]value_now;
// Q value for flip-flops
reg [7:0]value_now_d;
// D value for flip-flops
always@(reset or value_now or max or freeze or pre_load or pre_load_val)
begin
if(reset)
value_now_d=8'd0;
else if(freeze)
value_now_d=value_now; // 把 Q 又 assign 給 D
else if(max)
value_now_d=8'd255;
else if(pre_load)
value_now_d=pre_load_val;
else
value_now_d=value_now+1'b1;
end
// 在 clock 的 positive edge 時, 把 D 傳給 Q, 完成暫存器轉移 -> sequential circuit
always@(posedge clock)
begin
value_now<= value_now_d;
end
endmodule
`timescale 1ns/1ps
module test_up_counter;
reg clock,reset,max,freeze,pre_load;
reg [7:0]pre_load_val;
wire [7:0]value_now;
UP_COUNTER_max_freeze_pre_load
MY_COUNTER(clock,reset,max,freeze,pre_load,pre_load_val,value_now);
initial
begin
clock=1; reset=1; max=0; freeze=0; pre_load=0; pre_load_val=0;
#81
reset=0;
end
always #10 clock=~clock;
always@(posedge clock)
begin
#5
$display("Present value of the up counter=%d",value_now);
end
endmodule
Handout: (Two Weeks)
1. Write an 8-bit up/down counter module with Verilog hardware description with
following additional functions:
◆ Maximize output at next clock
◆ Freeze at any clock
◆ Pre-load a value to internal flip-flops
Please write a test bench to verify all the functions. You could display the results in
the console or show them with the waveform (Drawn with the waveform viewer built
in Modelsim or other CAD tools)
2. (Bonus) Make the up/down counter in problem 1 could be given with a user
defined counting step. That is, it can increase or decrease with the defined step.