SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
LOGIC CIRCUIT DESIGN
FOR VENDING MACHINE
STUDENT
: CHEN JUNHAO (E0706681)
SUPERVISOR
: DR TANG KAH MENG
PROJECT CODE : JUL2009/ENG/018
A project report submitted to SIM University
in partial fulfillment of the requirements for the degree of
Bachelor of Electronics Engineering
MAY 2010
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Abstract
Vending machines have been in existence as early as 1880s, the first commercial coinoperated vending machines were introduced in London, England selling post cards. The
main advantages of the vending machines over conventional purchasing
method/mechanism are its better accessibility and practicality. Vending machine can be
seen everywhere in our daily life fulfilling our daily needs, especially in big city where
product demands are high.
The objective of this project is to study, design and develop an FPGA based vending
machine prototype using VHDL (Very High Speed Integrated Circuit Hardware
Description Language) design. The modular approach method will be employed for this
project, using simulation to test out the functionality of each individual module.
Thereafter all the individual modules are integrated to form the vending machine system.
The design is compiled and simulated using Xilinx ISE Design Suite 11.1 and Xilinx
Isim(HDL simulator) .
This paper concludes on the summary, recommendations for future work and
development for the project.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Acknowledgement
The author would like to express his gratitude to his project supervisor, Dr Tang Kah
Meng for his patience, guidance and encouragement throughout the project. He has
always been approachable at all times when he needs to seek for valuable comments and
suggestions. He is very grateful to Dr Tang for understanding the difficulties faced as a
part-time student.
He would like to sincerely thank his employer, Hewlett Packard (Singapore) Pte Ltd and
his supervisor Mr Wong Kim Soon for his understanding and support throughout the
author’s studies. Secondly, he would like to thank his friends, colleagues and family for
their excellent support and care.
Lastly, he would like to thank those who have
contributed their valuable advice and comments for this project. Thank you.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Table of Contents
ABSTRACT ................................................................................................................................................... I
ACKNOWLEDGEMENT .......................................................................................................................... II
TABLE OF CONTENTS ........................................................................................................................... III
LIST OF FIGURES ......................................................................................................................................V
LIST OF TABLES .....................................................................................................................................VII
1. INTRODUCTION .................................................................................................................................... 1
1.1
1.2
1.3
1.4
BACKGROUND AND MOTIVATION ..................................................................................... 1
OBJECTIVES OF THE PROJECT ............................................................................................. 2
SCOPE OF THE PROJECT ........................................................................................................ 2
THESIS ORGANISATION......................................................................................................... 2
2. REVIEW OF THEORY AND PREVIOUS WORK.............................................................................. 3
2.1
OVERVIEW OF VENDING MACHINE .................................................................................... 3
2.1.1
HISTORY OF VENDING MACHINE .................................................................................. 3
2.1.2
OPERATION OF A TYPICAL VENDING MACHINE ....................................................... 3
2.2
OVERVIEW OF FPGA ............................................................................................................... 4
2.2.1
HISTORY OF FPGA[16] ....................................................................................................... 4
2.2.2
ARCHITECTURE OF FPGA................................................................................................. 5
2.3
REVIEW OF FPGA SOFTWARE .............................................................................................. 7
2.3.1
REVIEW OF VHDL AND VERILOG .................................................................................. 7
3. PROJECT PLANNING ........................................................................................................................... 8
4. DESIGN IMPLEMENTATION HARDWARE AND ENVIRONMENT ..........................................10
4.1
4.2
4.3
XILINX FPGA – SPARTAN 3A STARTER KIT ......................................................................10
XILINX FOUNDATION ISE 11 SOFTWARE ..........................................................................11
HARDWARE DESIGN AND DEVELOPMENT ......................................................................11
5. DESIGN APPROACH FOR VENDING MACHINE ..........................................................................14
5.1
5.2
5.2
5.3
5.4
INTRODUCTION ......................................................................................................................14
BLOCK DIAGRAM FOR VENDING MACHINE ....................................................................14
SPECIFICATIONS OF VENDING MACHINE ........................................................................15
FLOWCHART OF VENDING MACHINE ...............................................................................16
SOLUTION APPROACH FOR VENDING MACHINE ...........................................................17
6. DESIGN IMPLEMENTATION FOR VENDING MACHINE ...........................................................22
6.1
MODULE DESIGN ...................................................................................................................22
6.1.1
MODULE 1: COIN COUNTER............................................................................................22
6.1.2
MODULE 2: ITEM PROCESSOR ........................................................................................24
6.1.3
MODULE 3: CHANGE RETURN ........................................................................................29
6.1.4
MODULE 4: ITEM TRACKER ............................................................................................32
6.1.5
MODULE 5: REVENUE COUNTER ...................................................................................34
6.1.6
MODULE 6: CLOCK DIVIDER ..........................................................................................36
6.1.7
MODULE 7: LCD CONTROLLER ......................................................................................38
6.1.8
MODULE 8: VENDINGMACH MODULE .........................................................................43
7. SIMULATION RESULTS ......................................................................................................................45
7.1 SIMULATION RESULT: COIN COUNTER .....................................................................................45
7.2 SIMULATION RESULT: ITEM PROCESSOR .................................................................................47
7.3 SIMULATION RESULT: CHANGE RETURN ................................................................................49
7.4 SIMULATION RESULT: ITEM TRACKER .....................................................................................49
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
7.5 SIMULATION RESULT: REVENUE COUNTER ............................................................................50
7.6 SIMULATION RESULT: CLOCK DIVIDER ...................................................................................50
7.7 SIMULATION RESULT: VENDINGMACH ....................................................................................51
8. HARDWARE REALIZATION..............................................................................................................54
8.1 DOWNLOAD OF PROGRAM TO FPGA..........................................................................................54
8.2 EXPANSION THROUGH 6-PIN ACCESSORY HEADER ..............................................................57
8.3 LED CIRCUIT TO ACCESSORY HEADER .....................................................................................58
8.4 MAPPING OF USER INPUTS AND OUTPUTS ...............................................................................60
8.5 PREPARING AN SPI PROM FILE ....................................................................................................62
8.6 CONFIGURING SPI FLASH PROM .................................................................................................66
9 CONCLUSION AND RECOMMEDATION .........................................................................................68
9.1 CONCLUSION ...................................................................................................................................68
9.2 RECOMMEDATION FOR FUTURE STUDY ..................................................................................68
10 REFLECTION ........................................................................................................................................69
APPENDICE ................................................................................................................................................71
SOURCE CODE ..........................................................................................................................................71
REFERENCE ............................................................................................................................................109
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
List of Figures
Figure 2.1: FPGA Structure[4] ........................................................................................... 5
Figure 2.2: A typical logic block[5] .................................................................................... 6
Figure 2.3: Top down view of a simple generic FPGA architecture[5].............................. 6
Figure 3.1: Gantt Chart For Project .................................................................................. 10
Figure 4.1: Programmable logic design process[9] .......................................................... 12
Figure 5.1: Block Diagram Of Vending Machine ............................................................ 14
Figure 5.2: Flowchart Of The Vending Machine.............................................................. 16
Figure 5.3: Coin Counting ................................................................................................ 17
Figure 5.4: Money Return ................................................................................................. 18
Figure 5.5: Excess money ................................................................................................. 18
Figure 5.6: Item processor ................................................................................................ 19
Figure 5.7: Change calculate............................................................................................. 19
Figure 5.8: Change Return ................................................................................................ 20
Figure 5.9: Item Tracker ................................................................................................... 20
Figure 5.10: Total Revenue............................................................................................... 21
Figure 6.1: Flowchart of Coin Counter At State 0 ............................................................ 22
Figure 6.2: Flowchart of Coin Counter At State 10 .......................................................... 23
Figure 6.3: Coin Counter Module ..................................................................................... 23
Figure 6.4: Flow Chart Of Item Processor ........................................................................ 25
Figure 6.5: Item Processor Module ................................................................................... 27
Figure 6.6: Flow Chart Of Change Return........................................................................ 29
Figure 6.7: Change Return Module .................................................................................. 30
Figure 6.8: Flow Chart Of Item Tracker ........................................................................... 32
Figure 6.9: Item Tracker Module ...................................................................................... 33
Figure 6.10: Flow Chart Of Total Revenue Counter ........................................................ 34
Figure 6.11: Revenue Counter Module ............................................................................. 35
Figure 6.12: Flow Chart Of Clock Divider ....................................................................... 36
Figure 6.13: Clock Divider Module .................................................................................. 36
Figure 6.14: Character LCD interface[11] ........................................................................ 38
Figure 6.15: Initialization by Instruction ( 8 bit-interface)[12] ........................................ 39
Figure 6.16: LCD Character Display Command Set Part 1 [11] ...................................... 39
Figure 6.17: LCD Character Display Command Set Part 2 [11] ...................................... 40
Figure 6.18: LCD Character Set [11] ................................................................................ 40
Figure 6.19: LCD Character Display Address [11] .......................................................... 41
Figure 6.20: LCD Controller Module ............................................................................... 41
Figure 6.21: VendingMach Module .................................................................................. 43
Figure 7.1: Coin Counter Simulation 1 ............................................................................. 45
Figure 7.2: Coin Counter Simulation 2 ............................................................................. 46
Figure 7.3: Coin Counter Simulation 3 ............................................................................. 46
Figure 7.4: Item Processor Simulation 1........................................................................... 47
Figure 7.5: Item Processor Simulation 2........................................................................... 47
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Figure 7.6: Item Processor Simulation 3........................................................................... 48
Figure 7.7: Change Return Simulation 1 .......................................................................... 49
Figure 7.8: Change Return Simulation 2 .......................................................................... 49
Figure 7.8: Item Tracker Simulation 1 .............................................................................. 49
Figure 7.9: Revenue Counter Simulation 1....................................................................... 50
Figure 7.10: Clock Divider Simulation 1.......................................................................... 50
Figure 7.11: VendingMach Simulation 1.......................................................................... 51
Figure 7.12: VendingMach Simulation 2.......................................................................... 52
Figure 7.13: VendingMach Simulation 3.......................................................................... 52
Figure 7.14: VendingMach Simulation 4.......................................................................... 53
Figure 8.1: Processes Window .......................................................................................... 54
Figure 8.2: ISE IMPACT Window1 ................................................................................. 55
Figure 8.3: ISE IMPACT Window 2 ................................................................................ 55
Figure 8.4: ISE IMPACT Window 3 ................................................................................ 56
Figure 8.5: ISE IMPACT Window 4 ................................................................................ 56
Figure 8.6: Expansion Port[11] ......................................................................................... 57
Figure 8.7: FPGA Connections To J18 Accessory Header............................................... 57
Figure 8.8: LED Circuit Diagram [13] ............................................................................. 58
Figure 8.9: Circuit Implementation on Bread Board. ....................................................... 59
Figure 8.10: Locations Of Push Buttons ........................................................................... 60
Figure 8.11: Locations Of Slide Switches ........................................................................ 60
Figure 8.12: Locations Of LEDs For Individual Return Out ............................................ 61
Figure 8.13: Locations Of LEDs ....................................................................................... 61
Figure 8.14: Information Display On LCD....................................................................... 62
Figure 8.15: Process Panel ................................................................................................ 62
Figure 8.16: iMPACT Flows Panel .................................................................................. 63
Figure 8.17: PROM File Formatter Window .................................................................... 64
Figure 8.18: Add Device Window 1 ................................................................................. 64
Figure 8.19: Add Device Window 2 ................................................................................. 65
Figure 8.20: iMPACT Processes Window ........................................................................ 65
Figure 8.16: Generate Succeeded ..................................................................................... 65
Figure 8.21: SPI Jumper J1 Setting................................................................................... 66
Figure 8.22: SPI Jumper J26 Settings ............................................................................... 67
Figure 8.23: SPI Jumpers J23, J25 and J16 Settings ........................................................ 67
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
List of tables
Table 2.1: VHDL VS Verilog ........................................................................................... 7
Table 3.1: Task List .......................................................................................................... 9
Table 6.1: Description Of I/O on Coin Counter ........................................................... 24
Table 6.2: Items Price List Table................................................................................... 24
Table 6.3: Description Of I/O on Item Processor......................................................... 28
Table 6.3: Description Of I/O on Change Return ........................................................ 31
Table 6.4: Description Of I/O on Item Tracker ........................................................... 33
Table 6.5: Description Of I/O on Revenue Counter .................................................... 35
Table 6.6: Description Of I/O on Clock Divider .......................................................... 37
Table 6.7: Description Of I/O on LCD Controller ....................................................... 42
Table 6.8: Description Of I/O on VendingMach .......................................................... 44
Table 8.1: Components List For LED Circuit.............................................................. 58
Table 8.2: Connections Pin Out From LED Circuit To FPGA .................................. 59
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
1. INTRODUCTION
1.1
BACKGROUND AND MOTIVATION
Vending machines have been in existence as early as 1880s, the first commercial coinoperated vending machines were introduced in London, England selling post cards. The
first vending machine in the U.S. was built in 1888 by the Thomas Adams Gum
Company, selling gum on train platforms. [1]
In our present days, vending machines can be found everywhere in our everyday life. For
example, vending machine can be found at the train stations selling train tickets. In the
schools and offices vending can drinks and snacks. The mode of trading also changes
from the coins and notes system to cashless transaction with the introduction of cash card
or credit cards. One of the greatest selling point of a vending machine is its availability to
the customers at all time of the day.
The advantage of the FPGA (Field Programmable Gate Array) is that the chip is
completely programmable and can be re-programmed. In this way it becomes a large
logic circuit that can be configured according to a design, but if changes are required it
can be re-programmed with an update. Thus if circuit card or board is manufactured and
contains an FPGA as part of the circuit, this is programmed during the manufacturing
process, but can later be re-programmed to reflect any changes. [2]
FPGA implementation is chosen because of its shorter time to market, ability to reprogram in the field to fix bugs, and lower non-recurring engineering costs.
The purpose of this project is to design and implement a prototype vending machine with
a FPGA design.
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Logic Circuit Design For A Vending Machine
1.2
Name :Chen Junhao
Stud ID:E0706681
OBJECTIVES OF THE PROJECT
The overall objective of this project is to study the system design of the vending machine
and incorporate the learning of digital logic and programming along with user inputs.
The academic goal of this project is to develop the research, design, programming, testing
and evaluation skills of the student. The student also has the opportunity to learn on
report writing, project management, presentation skills and communication skills.
1.3
SCOPE OF THE PROJECT
The scope of the project is to design a prototype of Vending Machine using FPGA. The
main tasks of the project include:

Background study and Literature review on vending Machine and FPGA.

Research and study on the operation of a vending machine.

Research and implement the architecture of vending machine using VHDL and
FPGA as the platform.

Learn and familiarize with the evaluation kit (Spartan 3A) and programming
language (VHDL).

Testing and simulation to verify the vending machine prototype design using
simulation tool.

1.4
Writing of technical report.
THESIS ORGANISATION
Chapter 2 describes about the overview of the vending machine and FPGA.
Chapter 3 describes on project planning according to critical task.
Chapter 4 describes on the design implementation platform and environment of the
vending machine.
Chapter 5 describes on the design approach of the vending machine.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Chapter 6 describes the design implementation using VHDL.
Chapter 7 describes on the simulation.
Chapter 8 describes on the hardware realization of the project.
Chapter 9 and 10 provides the conclusion, recommendations and reflection on the project.
Appendix A contains the source code of the project.
2. REVIEW OF THEORY AND PREVIOUS WORK
2.1
OVERVIEW OF VENDING MACHINE
2.1.1 HISTORY OF VENDING MACHINE
The history of vending machine can go back the first century. The vending machine
found in the work of Hero of Alexandria, a first-century engineer and mathematician. His
machine accepted a coin and then dispensed a fixed amount of holy water.[3]
The first modern coin-operated vending machine came about in the early 1880s vending
postcards in London, England. The first vending machine in US was built in 1888 by the
Thomas Adams Gum Company ,selling gum on train platforms.
The growth of the vending business took off from there. Vending machines can be seen
almost anywhere in big cities, vending drinks and snacks. Daily neccessities like train
tickets and stamps, are also vended through these machines.
2.1.2 OPERATION OF A TYPICAL VENDING MACHINE
The basic operation of a Vending Machine is as followed:

When the user put in money, the coin mechanism tells the computer the amount
of money that is inserted.

When the user presses the button to purchase the item that the user wants, the
computer turns on the motor and dispenses the product.
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Logic Circuit Design For A Vending Machine

2.2
Name :Chen Junhao
Stud ID:E0706681
The machine will return the user the change if there is any.
OVERVIEW OF FPGA
2.2.1 HISTORY OF FPGA[16]
It was around the beginning of the 1980s, many have realise that there was a gap in the
digital IC. The programmable devices like SPLDs and CPLDs are highly configurable
and had fast design and modification times. But as the design gets more complex, the
current devices were unable to cope with it.
While the ASICs were able to support the large and complex design, it came with a price.
As the design cost was very expensive and also the time to design is quite lengthy. On top
of that, once the design had been implemented, it is effectively “frozen” in silicon. This
means that future expansions and design changes will require a re-design of the whole
system.
Xilinx was the first to develop the field programmable gate array (FPGA) and release to
the market in 1985, the XC2064 by Xilinx Co-Founders, Ross Freeman and Bernard
Vonderschmitt.
Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s, when
competitors sprouted up, eroding significant market-share. By 1993, Actel was serving
about 18 percent of the market.
The 1990s were an explosive period of time for FPGAs, both in sophistication and the
volume of production. In the early 1990s, FPGAs were primarily used in
telecommunications and networking. By the end of the decade, FPGAs found their way
into consumer, automotive, and industrial applications.
FPGAs got a glimpse of fame in 1997, when Adrian Thompson merged genetic algorithm
technology and FPGAs to create a sound recognition device. Thomson’s algorithm
allowed an array of 64 x 64 cells in a Xilinx FPGA chip to decide the configuration
needed to accomplish a sound recognition task.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
2.2.2 ARCHITECTURE OF FPGA
The most common FPGA architecture consists of an array of configurable logic blocks
(CLBs), I/O pads, and routing channels. Generally, all the routing channels have the same
width (number of wires). Multiple I/O pads may fit into the height of one row or the
width of one column in the array
The picture below shows a typical FPGA structure.
Figure 2.1: FPGA Structure[4]
The FPGA logic block consists of a 3-input look-up table (LUT), a multiplexer and a flipflop, as shown below. The multiplexer feeding the flip-flop can be configured to accept
the output from the LUT or a separate input to the logic block. The LUT can be
configured to represent any 3-input logical function.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Figure 2.2: A typical logic block[5]
The complete FPGA consists of a large number of programmable logic blocks “islands”
surrounded by a “sea” of programmable interconnects shown below. The logic blocks can
be programmed to duplicate the functionality of basic logic gates such as AND, OR,
XOR, NOT or more complex combinational functions such as decoders or simple
mathematical functions. In most FPGAs, these programmable logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of memories.
The individual blocks are interconnected by a matrix of wires and programmable
switches. The switches and wires allow the logic blocks of an FPGA to be
interconnected as needed by the system designer. These logic blocks and interconnects
can be programmed after the manufacturing process by the customer/designer to
implement any logical function.[7]
Figure 2.3: Top down view of a simple generic FPGA architecture[5]
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Logic Circuit Design For A Vending Machine
2.3
Name :Chen Junhao
Stud ID:E0706681
REVIEW OF FPGA SOFTWARE
2.3.1 REVIEW OF VHDL AND VERILOG
The decision on the selection of programming language to use on the FPGA, are not
based solely on the capability. There are three factors that the user can consider:
1) Personal preferences, 2) EDA tool availability, 3) Commercial, business and marketing
issues. [6]
Below is a table showing the main differences between the two.
Aspect
Level Construct
Simulation
Speed
Easiest to Learn
Design
reusability
Procedures and
tasks
Standards
VHDL
Weaker in low level design,
but superior in higher and
system level design.
Verilog
Has very good acceptance in
ASIC, particularly lower level
designs.
Simulation is slower.
Very flexible, more difficult to
learn without knowledge.
Simulation is faster.
Relatively simple, easier to grasp
and understand.
Procedures and functions may
be placed in a package.
Allows concurrent procedure
calls.
No concept of packages in
Verilog.
Does not allow concurrent task
calls.
IEEE standard 1076
IEEE standard 1364
Table 2.1: VHDL VS Verilog
The choice of the programming language will be determine in the later chapters.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
3. PROJECT PLANNING
This chapter will explain how the project plan is constructed. Gantt project is used as the
tools to draw out the planned Gantt chart. Basically, the project tasks are divided into six
sections:
1) Project Planning and Management
2) Initial work & Literature Review
3) Learning Programming language, structure and tools
4) Design Implementation
5) Simulation, Verification and Debugging
6) Thesis, Poster and Presentation
No
1
2
3
4
5
6
Task
Logic Circuit Design For Vending Machine using
FPGA
Project Planning and Management
Literature review and research
Preparation for TMA 01
Initial work & Literature Review
Research of hardware kit and programming
Design Specification
Design Flowchart
Derive Logic Equations From Flowchart
Interim report
Learning Programming language, structure and
tools
Learn FPGA and VHDL documents
Design Implementation
Program circuits
Coding of Modules
Simulation, Verification and Debugging
Design and write testbench
Run simulation, verification and debugging
Thesis, Poster and Presentation
Report writing
Poster Preparation
Oral presentation Preparation
8
Start
End
8/3/09
8/3/09
8/31/09
8/17/09
8/31/09
8/17/09
8/19/09
8/31/09
9/7/09
9/19/09
8/29/09
9/19/09
9/19/09
9/19/09
8/19/09
8/22/09
9/26/09
9/26/09
10/5/09
10/5/09
1/4/10
1/4/10
2/15/10
3/15/10
3/15/10
3/29/10
3/1/10
3/1/10
4/26/10
5/5/10
10/5/09
10/5/09
3/13/10
2/13/10
3/13/10
5/1/10
3/27/10
5/1/10
5/14/10
5/14/10
5/14/10
5/14/10
Logic Circuit Design For A Vending Machine
Table 3.1: Task List
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Name :Chen Junhao
Stud ID:E0706681
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Figure 3.1: Gantt Chart For Project
4.
DESIGN
ENVIRONMENT
IMPLEMENTATION
HARDWARE
AND
4.1 XILINX FPGA – SPARTAN 3A STARTER KIT
The Xilinx Spartan 3A starter kit is the platform selected for the implementation of the
project. It is chosen for its competitive pricing and the specifications of the board. Also
the Xilinx Starter Kit comes with the development board, power supply, Xilinx ISE®
WebPACK™ or ISE Foundation™ evaluation software and a programming cable. The
project will require some user inputs from the user/customer, in the form of switches or
push button .Apart from that, some outputs to indicate to the user/customer on the status
of the purchase or the amount of coins inserted, which can be displayed with the LEDs on
board or by message display on the LCD panel.
Below are some of the key features of the FPGA development board [8]:
Key Features
Xilinx Devices


Spartan-3A (XC3S700A-FG484)
Platform Flash (XCF04S-VOG20C)
Clocks


50 Hz crystal oscillator on-board
Open slot for optional user-installed clock
Memory




Mbit Platform Flash PROM
32M x 16 DDR2 SDRAM
32 Mbit parallel Flash
2-16 Mbit SPI Flash devices
Analog Interface Devices


4-channel D/A converter
2-channel A/D converter
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Logic Circuit Design For A Vending Machine

Name :Chen Junhao
Stud ID:E0706681
Signal amplifier
Connectors and Interfaces












Ethernet 10/100 PHY
JTAG USB download port
Two 9-pin RS-232 serial port
PS/2-style mouse/keyboard port
15-pin VGA connector capable of 4,096 colors
One FX2 100-pin and two 6-pin expansion connectors
20 user I/O available on standard header pins
Stereo mini-jack for PWM audio
Rotary/push button function switch
Eight individual LED outputs
Four slider switches
Four push-button switches
Display

16 character, 2-Line LCD
4.2 XILINX FOUNDATION ISE 11 SOFTWARE
The Xilinx ISE 11 software will be use to implement the project. The development board
is supported by this version of software. The Xilinx ISE is an integrated development
environment for Xilinx FPGAs and CPLDs.
This software is designed for FPGA and CPLD design offering HDL synthesis and
simulation, implementation, device fitting, and JTAG programming.
4.3 HARDWARE DESIGN AND DEVELOPMENT
The process of creating digital logic is similar to the embedded software development
process. A description of the hardware's structure and behavior is written in a high-level
hardware description language (usually VHDL or Verilog) and that code is then compiled
and downloaded prior to execution. Although schematic capture can be used for design
entry, but due to more complex designs and the improvement of the language-based tools
it has become less popular.
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Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
The overall process of hardware development for programmable logic is shown in Figure
4.1 and described in the paragraphs that follow.
The most distinct difference between hardware and software design is the way a
developer must think about the problem. Software developers tend to think sequentially,
even when they are tasked to program a multithreaded application. Most of the time , the
source code are always executed in that order.
At the design entry phase, hardware designers must think and program in parallel. All of
the input signals are processed in parallel, inside each one is a series of macrocells and
interconnections routed toward their destination output signals. Therefore, the statements
of a hardware description language create structures, all of which are process at the very
same time. (Normally the link between each macrocell to another macrocell is usually
synchronized to some other signal, like a common clock.)
Figure 4.1: Programmable logic design process[9]
In a typical design, after each design entry is completed the next step is to perform
periods of functional simulation. This is where a simulator comes in place. It is use to
execute the design and confirm that the correct/required outputs are produced for a given
set of test inputs.
This step is to ensure the designer that his/her logic is functionally correct before going
on to the next stage of development. This is a good practice as compared to simulating an
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Logic Circuit Design For A Vending Machine
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Stud ID:E0706681
integrated full scale design entry. As the design entry gets more complex, the
troubleshooting process will be much more difficult and time consuming.
Once the correct representation of the hardware exists, compilation can be done. This
hardware compilation comprises of two parts. This first part is called synthesis and the
result is a representation called a netlist. The netlist generated is device independent, so
its contents do not depend on the particulars of the FPGA or CPLD. Normally it is stored
in a standard format called the Electronic Design Interchange Format (EDIF).
The second part in the translation process is called place & route. This step involves
mapping the logical structures described in the netlist onto actual macrocells,
interconnections, and input and output pins.
This process is similar to the equivalent step in the development of a printed circuit
board, and it may likewise allow for either automatic or manual layout optimizations. The
output result of the place & route process is a bitstream. This name is used generically,
despite the fact that each CPLD or FPGA (or family) has its own, usually proprietary,
bitstream format. The bitstream is the binary data that must be loaded into the FPGA chip
to execute a particular hardware design. [9]
13
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
5. DESIGN APPROACH FOR VENDING MACHINE
5.1 INTRODUCTION
This project focuses on the design of the software for a vending machine. A vending
machine can be described using modular design. Using this concept, the designer will
program the machine in the selected application platform and then implement it on an
FPGA.
5.2
BLOCK DIAGRAM FOR VENDING MACHINE
Figure 5.1: Block Diagram Of Vending Machine
The picture above shows the block diagram of the vending machine. The vending
machine comprises of 7 different modules interconnecting to each another. The input
14
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
device for the prototype comes in the form of switches and push buttons. For the output
devices, the onboard LEDs and LCD display is used to display the output of the system.
5.2
SPECIFICATIONS OF VENDING MACHINE
The vending machine will simulate an actual real life vending machine and below are the
features:

Takes in coins of denominator : 10 cents, 20 cents,50 cents, 1 dollar coins

Vends the item selected if money inserted is more than or equal to the item’s
price.

Ask the user to insert more money if the price of the item selected exceeds the
amount inserted.

Calculates and return the change if there is excess change.

The machine will take in a maximum of 1 dollar coins in total and return the
excess money inserted.

The machine will be able to vend four products. (Item A, item B, item C and item
D.)

The machine will keep track of the quantity for each of the products sold.

When the product is sold out, the machine will signal a sold out indication when
that particular product is selected.

The machine will keep track of the total revenue made.
15
Logic Circuit Design For A Vending Machine
5.3
Name :Chen Junhao
Stud ID:E0706681
FLOWCHART OF VENDING MACHINE
Start
N
Coins
Added
FLOW CHART FOR VENDING MACHINE
Y
Coin
Counter
Y
Dispense
Change
<40p
N
Y
Y
>=40p &
<50p
1 Product
Avail.
Coins
Added
N
N
Y
N
P1
Selected
Y
N
Reset
Dispense
P1
Change
Required?
N
Complete
Y
Dispense
Change
Y
N
Y
>=50p &
<80p
Y
2 Products
Avail.
Coins
Added
N
N
P2
Selected
Reset
Y
Dispense
P2
Change
Required?
N
Complete
Y
N
Dispense
Change
Y
>=80p &
<100p
Y
3 Products
Avail.
Coins
Added
N
N
N
Y
P3
Selected
Reset
Dispense
P3
Change
Required?
N
Complete
N
Dispense
Change
Y
Y
>=100p
4 Products
Avail.
N
>100p
Y
Coins
Added
N
Y
N
Reset
P4
Selected
Y
Dispense
P4
N
Change
Required?
Complete
Y
Return
Excess
Change
Figure 5.2: Flowchart Of The Vending Machine
The figure above shows the flowchart of the vending machine. It describes how the
vending machine operates in sequence. The normal flow of the vending machine is
described below:
1) The user inserts coins into the vending machine.
2) The vending machine will count the coins inserted.
3) When the amount inserted is sufficient for purchase, the products will be available
for selection.
4) The user will then choose the item which he/she wants.
5) The machine will dispense the product selected.
6) Change will be return if the amount inserted is more than the product’s cost.
16
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
7) After change is dispensed, the process is completed.
Another possible flow of the vending machine is as followed:
1) The user inserts coins into the vending machine.
2) The vending machine will count the coins inserted.
3) When the amount inserted is sufficient for purchase, the products will be available
for selection.
4) The user decides that he/she do not want to make a purchase and pressed the coin
return button.
5) The machine will return the amount inserted to the user.
6) After the coins are returned, the process is completed, goes back to the initial
state.
5.4
SOLUTION APPROACH FOR VENDING MACHINE
With the design requirements for the vending machine, the next step is to analyse the
various functions related to the vending machine. In this section, the main functions
will be discussed.
1. Coin counting: The function “coin counter” of the vending machine is shown in
Figure 5.2.
TenCent
TwentyCent
count_out
FiftyCent
Coin Counting
Dollar
Figure 5.3: Coin Counting
17
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
2. Money Return: The vending machine will return change if the button, “return
change” is selected. (Refer to Figure 5.3).
Return_money
Return_money_out
Money Return
Figure 5.4: Money Return
3. Excess money: The vending machine will return excess money if the amount
exceeds one dollar or 100 cents. (Refer to Figure 5.4).
count_out > 10
excess_money
Excess money
Figure 5.5: Excess money
4. Item selection: The item will be delivered when the customer selects an item and
the amount deposited into the vending machine is equal to or greater than the
price of the item selected. It also check whether the items are sold out, which is
monitored by another function Item Tracker. (Refer to Figure 5.5).
18
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Item_select
Item_out
Item_processor
totalamount
Figure 5.6: Item processor
5. Change calculation: If the customer inserted in more money than the price of the
item selected, the vending machine needs to calculate the change. The change is
equal to the total amount inserted to the vending machine minus away the price of
the selected item. (Refer to Figure 5.6).
Item_select
change
Change Calculate
totalamount
Figure 5.7: Change calculate
6. Change return: After the vending machine has calculated the amount of change,
this function will determine the number of coins of different coin denominator to
return. (Refer to Figure 5.7).
19
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
TenCent_out
TwentyCent_out
change
Change Return
FiftyCent_out
Dollar_out
Figure 5.8: Change Return
7. Item Tracker: This function will update the quantities of the product left in the
vending machine. Updating will be done after the item is sold. (Refer to Figure
5.8).
Item_out
Update item count
Item Tracker
Figure 5.9: Item Tracker
8. Total Revenue: This function keep tracks of the total revenue of the vending
machine. Update is done after the item is sold. (Refer to Figure 5.9).
20
Logic Circuit Design For A Vending Machine
Item_out
Name :Chen Junhao
Stud ID:E0706681
Update total revenue
Total Revenue
Figure 5.10: Total Revenue
9. Lcd Display: This function controls the text and the values needed to be displayed
to the user/customer.
21
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
6. DESIGN IMPLEMENTATION FOR VENDING MACHINE
6.1
MODULE DESIGN
In this section, the design will be split into 7 different modules covering the functions
mentioned in the previous chapter. VHDL logic will be used to describe the behaviour of
each individual module.
6.1.1 MODULE 1: COIN COUNTER
The main function of this module is to count the total amount of coins that are inserted
into the vending machine. Prior to this, the coin counter will also return excess money
more than a dollar or 100 cents. In order to accomplished this objective, finite state
machine is used to model this function.
The figure below illustrates how the state machine determines the next state and output
the total amount and excess coin when required.
0
S0
Total
Amount = 0
Ten Cent
0
Twenty Cent
0
Fifty Cent
0
Dollar
1
1
1
1
S1
Total
Amount = 10
S2
Total
Amount = 20
S5
Total
Amount = 50
S10
Total
Amount
=100
Excess Coin = 0
Excess Coin = 0
Excess Coin = 0
Excess Coin = 0
Figure 6.1: Flowchart of Coin Counter At State 0
At state 0, if any of the inputs (Ten cent, Twenty cent, Fifty cent or Dollar) is valid, it
will go to the respective next state as shown in Figure 6.1 and output the excess coin.
Basically the flow for the other states will be similar to the one shown above.
22
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
0
S10
Total
Amount =
100
Ten Cent
0
Twenty Cent
0
Fifty Cent
0
Dollar
1
1
1
1
S10
Total
Amount =
100
S10
Total
Amount =
100
S10
Total
Amount =
100
S10
Total
Amount
=100
Excess Coin =
0001
Excess Coin =
0010
Excess Coin =
0101
Excess Coin =
1010
Figure 6.2: Flowchart of Coin Counter At State 10
At state 10, if any of the inputs (Ten cent, Twenty cent, Fifty cent or Dollar) is valid, it
will update the next state value. As mentioned in the specification of the project, the
maximum amount which the vending machine will allow is 1 dollar or 100 cents. The
excess value inserted to the machine will be returned to the customer through the excess
coin. This can be seen in the figure above, after the machine updates the next state, it
outputs the excess coin amount.
Inputs
Outputs
clk
reset
count_out(3:0)
tencent
twentycent
Coincounter
fiftycent
dollar
excess_money(3:0)
clearcount
changedone
Figure 6.3: Coin Counter Module
23
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
There are a total of 8 inputs and 2 outputs in this module.
Name of input/output
Description Of Signal
clk
System clock
reset
Reset bit for sequence reset
tencent
A bit to indicate ten cent coin is inserted
twentycent
A bit to indicate twenty cent coin is inserted
fiftycent
A bit to indicate fifty cent coin is inserted
dollar
A bit to indicate dollar cent coin is inserted
clearcount
A bit to clear the value of count_out.
changedone
A bit to indicate that change is done.
count_out(3:0)
The total amount inserted into the machine.
excess_money(3:0)
The amount of excess money.
Table 6.1: Description Of I/O on Coin Counter
6.1.2 MODULE 2: ITEM PROCESSOR
The item processor accepts purchase request and determines if the money inserted is
enough to purchase an item. In addition to that it will also check for the stock of each
item, before it processes the transaction. Upon successful transaction, it will send a
request for an update on quantity of the items to another module and calculate the change
amount to return to the customer.
If the user/customer presses the reset button, the total amount will be assigned to the
change. This change signal is directed to another module (change return) to return all the
coins inserted to the customer. The prices of the items are listed below.
Item
Price(Cents)
A
40
B
50
C
60
D
70
Table 6.2: Items Price List Table
24
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Productsel Flag
= ‘0’
T
Write enable = '0';
item_out = '0';
F
Item Select
Valid
T
Total amount >
itemprice And
item_count >0
T
item_out = '1';
waddr =
itemaddress;
tmp_data =
item_count - 1;
Write enable = '1';
Change = Total
amount –
itemprice
Productsel flag =
‘1’
Total amount =
itemprice
clearcount = '1';
F
Total amount >
itemprice And
item_count = 0
T
item_soldout = '1';
T
requirecoins = '1';
F
F
Total amount <
itemprice
item_out = '0'
item_soldout = '0'
waddr <= "1000"
tmp_data = ‘0’
Write enable= ‘0’
Productsel_flag = '0'
change = "0000"
clearcount = '0'
requirecoins <= '0'
Figure 6.4: Flow Chart Of Item Processor
25
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
The figure above shows how the item processor module functions. The sequence of the
process is as follow:
Firstly, it checks for valid item selected ( itemA is represented by “0001” ,itemB is
“0010”, itemC is “0100” and itemD is “1000” ). If none of the items is selected or valid,
it will clear all the outputs as stated in the flowchart.
Then if item selected is valid, it move to the next check. At this stage it checks for the
total amount inserted is greater than the item’s price and also item count is greater than
zero to ensure that the product is not sold out.
If the conditions are not fulfilled, it will proceed to the next level of check. If the total
amount inserted is more than or equal to item’s price and item count is zero, it will then
set output the item_soldout signal to ‘1’. This is to indicate to the customer or user that
the item is soldout. If the total amount inserted is less than to item’s price, the
requirecoins signal is set to ‘1’ to indicate more coins are needed for the purchase.
If the conditions are fulfilled, there are 3 concurrent process executed.
Firstly, the change amount will be updated and the product select flag signal will be set to
‘1’. The next process, it checks whether the product select flag signal is equal to ‘0’, this
check is important as this determines whether the machine will update the item count
quantity. If valid, the machine will output the selected product and updates the item count
quantity for that selected item. The last process is to check whether the total amount is
equal to the item’s price. If it satisfies the condition, the clearcount signal will be set to
‘1’. This signal is fed back to the coin counter module to reset the total amount.
26
Logic Circuit Design For A Vending Machine
Inputs
Name :Chen Junhao
Stud ID:E0706681
Outputs
itemA_out
clk
itemB_out
reset
itemC_out
item_select(3:0)
itemD_out
change(3:0)
itemA_count(7:0)
Item Processor
clearcount
itemB_count(7:0)
item_soldout
itemC_count(7:0)
requirecoins
we
itemD_count(7:0)
data_count(7:0)
total_amount(3:0)
waddr(3:0)
Figure 6.5: Item Processor Module
Name of Input/Output
Description Of Signal
clk
System clock
reset
Reset bit for sequence reset
item_select(3:0)
An array of bits representing the product selected
itemA_count(7:0)
An array of bits representing the quantity of itemA
itemB_count(7:0)
An array of bits representing the quantity of itemB
itemC_count(7:0)
An array of bits representing the quantity of itemC
itemD_count(7:0)
An array of bits representing the quantity of itemD
total_amount(3:0)
The total amount inserted into the machine
itemA_out
A bit to represent itemA dispensed.
itemB_out
A bit to represent itemB dispensed.
itemC_out
A bit to represent itemC dispensed.
itemD_out
A bit to represent itemD dispensed.
change(3:0)
An array of bits to represent the change required to return.
clearcount
A bit to clear the value of count_out.
27
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
item_soldout
A bit to indicate that the item is sold out.
requirecoins
A bit to indicate that coins is insufficient for purchase.
we
A bit to represent write enable.
data_count(7:0)
An array of bits to represent the item’s quantity
waddr(3:0)
An array of bits to represent the write address.
Table 6.3: Description Of I/O on Item Processor
28
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
6.1.3 MODULE 3: CHANGE RETURN
This module provides the change to the customer. Returned change is in coin
denominators of 10 cent, 20 cent, 50 cents and 1 dollar.
Reset
State
1110
Change is not
zero
T
State = Change
F
T
State = “0000”
T
State
0000
changeret =
"0000"
dollar_out = ‘0'
fifty_out = '0'
twenty_out = '0'
ten_out = '0'
donestatus := '0'
State
0001
changeret =
"0001"
dollar_out = ‘0'
fifty_out = '0';
twenty_out = '0'
ten_out = '1'
donestatus := '0'
State
0010
changeret =
"0010"
dollar_out = ‘0'
fifty_out = '0'
twenty_out = '1'
ten_out = '0'
donestatus := '0'
State
0011
changeret =
"0011"
dollar_out = ‘0'
fifty_out = '0'
twenty_out = '1'
ten_out = '1'
donestatus := '0'
State
0100
changeret =
"0100"
dollar_out = ‘0'
fifty_out = '0'
twenty_out = '1'
ten_out = '0'
donestatus := '0'
State
0101
changeret =
"0101"
dollar_out = ‘0'
fifty_out = '1'
twenty_out = '0'
ten_out = '0'
donestatus := '0'
State = “1111”
T
State
1111
changeret =
"0000"
dollar_out = ‘0'
fifty_out = '0';
twenty_out = '0';
ten_out = '0';
donestatus := '1';
State
1010
changeret =
"1010"
dollar_out = ‘1'
fifty_out = '0'
twenty_out = '0'
ten_out = '0'
donestatus := '0'
State
1001
changeret =
"1001"
dollar_out = ‘0'
fifty_out = '1'
twenty_out = '1'
ten_out = '0'
donestatus := '0'
State
1000
changeret =
"1000"
dollar_out = ‘0'
fifty_out = '1'
twenty_out = '1'
ten_out = '1'
donestatus := '0'
State
0111
changeret =
"0111"
dollar_out = ‘0'
fifty_out = '1'
twenty_out = '1'
ten_out = '0'
donestatus := '0'
State
0110
changeret =
"0110"
dollar_out = ‘0'
fifty_out = '1'
twenty_out = '0'
ten_out = '1'
donestatus := '0'
F
State = “0001”
T
F
State = “1011”
T
F
State = “0010”
T
F
State = “1001”
F
State = “0011”
F
T
State = “1000”
F
State = “0100”
T
F
T
State = “0111”
F
State = “0101”
T
T
F
T
State = “0110”
T
F
Figure 6.6: Flow Chart Of Change Return
29
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
The change is determined by the current register state. Every state has its own output
values for the different coin denominators. The initial state begins at state “1110”. At this
state, it will check whether the change is greater than zero. If the condition do not
satisfies, it will loop back to state “1110” again.
If the condition satisfies, the next state will be equal to the change. Upon the next clock
cycle, it will move to the next state. For example, if the change is “0011”, it will move to
state 0011, it will output the twenty_out and ten_out with a ‘1’. The machine returns 30
cents change to the customer. Upon that the machine move to the next state which is
“1111” (end state), at this state, it will set the donestatus to ‘1’. This is to indicate that all
change has been returned. After this it goes back to the initial state “1110” to restart a
new cycle.
Inputs
Outputs
ten_centout
twenty_centout
clk
fifty_centout
reset
Change Return
change(3:0)
dollar_out
changeret(3:0)
changedone
Figure 6.7: Change Return Module
30
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
Name of Input/Output
Description Of Signal
clk
System clock
reset
Reset bit for sequence reset
change(3:0)
An array of bits to represent the change required to return.
ten_centout
A bit to indicate ten cent coin is returned
twenty_centout
A bit to indicate twenty cent coin is returned
fifty_centout
A bit to indicate fifty cent coin is returned
dollar
A bit to indicate dollar cent coin is returned
changeret(3:0)
An array of bits to represent the state.
changedone
A bit to indicate that change is done.
Table 6.3: Description Of I/O on Change Return
31
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
6.1.4 MODULE 4: ITEM TRACKER
The purpose of this module is to read data from various addresses and update the data to
the address when required. Basically this module serves as a multiple read ports (4 read
ports) and single write ports RAM. Inside the RAM, initial values have been pre-defined.
These values indicate the number of items available in the vending machine. In the figure
below, shows the flowchart of the item tracker.
Item Tracker
If (Clock’event
and clk =’1')
T
If (WriteEnable
=’1')
T
RAM(conv_integer
(writeaddress)) =
datain
dout1 =
RAM(conv_integer
(read address1))
dout2 =
RAM(conv_integer
(read address2))
dout3 =
RAM(conv_integer
(read address3))
dout4 =
RAM(conv_integer
(read address4))
Figure 6.8: Flow Chart Of Item Tracker
The data will be read from the respective addresses of the item to the dout signals (dout1,
dout2, dout3 and dout4). The data is retrieved from the RAM array, as the read address is
defined in binary; a binary to integer conversion is needed.
If the clock’event and clk =’1’ and when WriteEnable (we) = ‘1’, the item tracker will
write the data (datain) to the assigned write address (wa). All the three signals are output
from the item processor module.
32
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
For a more detail on multiple read ports and single write port RAM and other type of
RAM configurations, reader can refer to the Xilinx XST manual.[10]
Inputs
Outputs
clk
d_out1(7:0)
ra1(3:0)
d_out2(7:0)
ra2(3:0)
d_out3(7:0)
ra3(3:0)
ra4(3:0)
Item Tracker
d_out4(7:0)
we
waddr(3:0)
datain(7:0)
Name of Input/Output
Figure 6.9: Item Tracker Module
Description Of Signal
clk
System clock
ra1(3:0)
An array of bits to represent the read address1.
ra2(3:0)
An array of bits to represent the read address2.
ra3(3:0)
An array of bits to represent the read address3.
ra4(3:0)
An array of bits to represent the read address4.
we
A bit to represent write enable.
waddr (3:0)
An array of bits to represent the write address.
datain(7:0)
An array of bits to represent the item’s quantity.
d_out1(7:0)
An array of bits to represent the data (item’s quantity).
d_out2(7:0)
An array of bits to represent the data (item’s quantity).
d_out3(7:0)
An array of bits to represent the data (item’s quantity).
d_out4(7:0)
An array of bits to represent the data (item’s quantity).
Table 6.4: Description Of I/O on Item Tracker
33
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
6.1.5 MODULE 5: REVENUE COUNTER
This module is to keep track of the total revenue of the vending machine. For every
product sold, the price will be updated to this counter. The flowchart of the revenue
counter is as shown below.
Revenue Counter
Clock’ Event
and Clock = ‘1’
itemA_out
T
totalrevenue =
totalrevenue +
itemA_price
T
totalrevenue =
totalrevenue +
itemB_price
T
totalrevenue =
totalrevenue +
itemC_price
T
totalrevenue =
totalrevenue +
itemD_price
F
itemB_out
F
itemC_out
F
itemD_out
F
others
totalrevenue =
totalrevenue
Figure 6.10: Flow Chart Of Total Revenue Counter
When clock’event and clock = ‘1’, it checks whether any of the item_out bit(itemA,
itemB, itemC and itemD) is turned on. If condition is true, it will add the item’s price to
the totalrevenue signal. If none of the item_out bit is selected, there will be no changes to
the totalrevenue.
34
Logic Circuit Design For A Vending Machine
Inputs
Name :Chen Junhao
Stud ID:E0706681
Outputs
clk
totalrev(7:0)
itemA_out
itemB_out
itemC_out
itemD_out
Revenue Counter
Figure 6.11: Revenue Counter Module
Name of Input/Output
Description Of Signal
clk
System clock
itemA_out
A bit to represent itemA dispensed.
itemB_out
A bit to represent itemB dispensed.
itemC_out
A bit to represent itemC dispensed..
itemD_out
A bit to represent itemD dispensed.
totalrev(7:0)
An array of bits to represent the total revenue.
Table 6.5: Description Of I/O on Revenue Counter
35
Logic Circuit Design For A Vending Machine
Name :Chen Junhao
Stud ID:E0706681
6.1.6 MODULE 6: CLOCK DIVIDER
This module is a clock divider. The onboard system clock is 50MHz, the clock period
work out to be around 20ns. We need to generate a clock with clock period of 1 second,
which works out to be 1 Hz.
Clk @ 50Mhz
Divide By
25
Clk @ 1MHz
Divide By
5
Clk @ 200KHz
Divide By
10
Clk @ 1KHz
Divide By
10
Clk @ 1Hz
Divide by 10
Clk @ 20KHz
Divide By
2
Clk @ 10KHz
Divide By
10
Clk @ 100 Hz
Divide By
10
Clk @ 10Hz
Figure 6.12: Flow Chart Of Clock Divider
Inputs
Outputs
Clk_25MHz
Clk_100KHz
clk_50MHz
Clk_10KHz
Clk_2KHz
Clk_1KHz
Clock Divider
Clk_200Hz
Clk_100Hz
Clk_10Hz
Clk_1Hz
Figure 6.13: Clock Divider Module
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Name of Input/Output
Description Of Signal
Clk_50MHz
System clock @ 50MHz
Clk_25MHz
Clock @ 25MHz
Clk_100KHz
Clock @ 100KHz
Clk_10KHz
Clock @ 10KHz
Clk_2KHz
Clock @ 2KHz
Clk_1KHz
Clock @ 1KHz
Clk_200Hz
Clock @ 200Hz
Clk_100Hz
Clock @ 100Hz
Clk_10Hz
Clock @ 10Hz
Clk_1Hz
Clock @ 1Hz
Name :Chen Junhao
Stud ID:E0706681
Table 6.6: Description Of I/O on Clock Divider
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6.1.7 MODULE 7: LCD CONTROLLER
This module will process the data and sent the characters to the LED display panel.
Figure 6.14: Character LCD interface[11]
Above shown is the character LCD interface, it shows how the pins of the FPGA are
connected to the Character LCD Display. In order to use the LCD display, it must be first
initialise. Below shows the procedure of initialising the LCD, eight bit data interface will
be used in this project.
After the power-on initialization is completed, the four-bit interface is established. The
next part of the sequence configures the display:
1. Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3A/3AN Starter Kit board.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically increment
the address pointer.
3. Issue a Display On/Off command, 0x0C to turn the display on and disable the cursor
and blinking.
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4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles)
after issuing this command.
Figure 6.15: Initialization by Instruction ( 8 bit-interface)[12]
Figure 6.16: LCD Character Display Command Set Part 1 [11]
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Figure 6.17: LCD Character Display Command Set Part 2 [11]
Figure 6.18: LCD Character Set [11]
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Figure 6.19: LCD Character Display Address [11]
Above shows the Character display address for the LCD. In the non-shifting mode, a total
of 32 characters can be displayed. (16 characters on each row). The user can choose the
address where he/she wants write the character to by using the set DD RAM address
function. The address starts from Hex “00” to “0F” for row 1. The address starts from
Hex “40” to “4F” for row 2.
Next the user will specify the data bits DB7 to DB0 corresponding to the character that
the user wants to display. The LCD_RS set to 1 and LCD_RW set to 0 using the Write
data to DD RAM function from LCD character display command set shown in figure
6.11.
Inputs
Outputs
clk
rst
sf_d(7:0)
coin_in(3:0)
control(2:0)
change(3:0)
productselect(3:0)
LCD CONTROLLER
Figure 6.20: LCD Controller Module
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Name of Input/Output
Description Of Signal
Clk
System clock
rst
A bit for reset.
coin_in(3:0)
An array of bits to represent the total coin inserted.
Change(3:0)
An array of bits to represent the change required.
Productselect(3:0)
An array of bits to represent the product selected.
Sf_d(7:0)
An array of bits to represent the data to the LCD controller
Control(2:0)
An array of bits to represent the control bits to LCD
controller.
Table 6.7: Description Of I/O on LCD Controller
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6.1.8 MODULE 8: VENDINGMACH MODULE
This module interlinks all the 7 different modules to operation as a complete vending
machine. Basically it maps the inputs and outputs to the respective modules. Below is the
model of the vending machine. This block is retrieved from the “View RTL schematics”.
Figure 6.21: VendingMach Module
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Name of Input/Output
Description Of Signal
clk
System clock
Item_select(3:0)
An array of bits representing the product selected.
tencent
A bit representing ten cent coin inserted.
twentycent
A bit representing twenty cent coin inserted.
fiftycent
A bit representing fifty cent coin inserted.
dollar
A bit representing dollar coin inserted.
reset
A bit representing reset.
control(2:0)
An array of bits representing the control bits to LCD.
sf_d(7:0)
An array of bits representing the data bits to LCD.
totalrev(7:0)
An array of bits representing the total revenue.
ten_centout
A bit representing ten cent coin returned.
twenty_centout
A bit representing twenty cent coin returned.
fifty_centout
A bit representing fifty cent coin returned.
dollar_out
A bit representing dollar coin returned.
change(3:0)
An array of bits representing the total change returned.
changeret(3:0)
An array of bits representing the state of change.
count_out(3:0)
An array of bits representing the total amount inserted.
excess_money(3:0)
An array of bits representing the excess money.
changedone
A bit representing the change return is done.
clearcount
A bit indicating to clear the total amount.
itemA_out
A bit representing itemA is dispensed.
itemB_out
A bit representing itemB is dispensed.
itemC_out
A bit representing itemC is dispensed.
itemD_out
A bit representing itemD is dispensed.
item_soldout
A bit representing item has been sold out.
requirecoins
A bit representing more coins is required for purchase.
Table 6.8: Description Of I/O on VendingMach
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7. SIMULATION RESULTS
In order to test out the modules’ functionalities, simulations have to be done to observe
the way each individual module behaves. The program used for simulation is ISim which
comes along with the Xilinx ISE 11 software. In order to simulate the module, testbench
have to be written to model the inputs in actual operating. Example like forcing an input
for a period of time and observe the change for output. Below are the simulation results
for the modules.
7.1 SIMULATION RESULT: COIN COUNTER
Test One: Simulate the insertion of 5 ten cent coins.
Figure 7.1: Coin Counter Simulation 1
The output signal count_out indicates a value of “0101” in binary with is 5 in decimal. It
has been shown that the counting is correct.
Test Two: Simulate insertion of 1 ten cent coin, 1 twenty cent coins and 1 fifty cent
coins.
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Figure 7.2: Coin Counter Simulation 2
The figure shows the insertion of 1 ten cent, 1 twenty cent, 1 fifty cent. The output
count_out shows a value of “1000” in binary which represent 8 in decimal.
Test Three: Simulate the insertion of 1 dollar coin, followed by a 1 fifty cent coin, 1
twenty cent, 1 ten cent.
Figure 7.3: Coin Counter Simulation 3
The result shows that when the count_out value exceed one dollar, the excess money will
be return. The values are shown in the excess_money output signal. First it returns the 50
cents (“0101”), follow by 20 cents (“0010”) and lastly 10 cents (“0001”).
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7.2 SIMULATION RESULT: ITEM PROCESSOR
Test One: Setting the total amount to zero. Set the item_select by sequence starting from
item1 to item4.
Figure 7.4: Item Processor Simulation 1
The result from the simulation shows that when the item_select is set, the requirecoins
output signals a ‘1’.
Test Two: Setting the total amount to 1 dollar (“1010”) and set the itemA_count to ‘0’.
Set the item_select to itemA (“0001”).
Figure 7.5: Item Processor Simulation 2
Based on the result of the simulation, the item_soldout signal is set to ‘1’ after the
item_select signal is set to “0001” (selection of itemA). This result adheres to the
expected outcome of the test.
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Test Three: Setting the total amount to 1 dollar (“1010”) and set the itemA_count to 3.
Set the item_select to itemA (“0001”).
Figure 7.6: Item Processor Simulation 3
The result shows that the module sets the itema_out signal to ‘1’ after itemA(“0001”) is
selected. Change is also updated, with totalamount of one dollar minus off the itemA’s
price of 40 cents, the resultant change is 60 cents (“0110”). Once the itema_ out signal is
turn on, the write enable (we) signal, the write address(waddr) and input data
(data_count) is updated.
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7.3 SIMULATION RESULT: CHANGE RETURN
Test One: Setting the change to 80 cents.
Figure 7.7: Change Return Simulation 1
The module set the ten_centout , twenty_centout and fifty_centout to ‘1’ for a clock cycle.
The return amount adds up to the total change amount of 80 cents.
Test Two: Setting the change to 40 cents.
Figure 7.8: Change Return Simulation 2
From the result of the simulation, the twenty_centout signal is on for 2 clock cycles,
which totals up to 40 cents of change return.
7.4 SIMULATION RESULT: ITEM TRACKER
Test One: Setting the read address 1(ra1) to “0000”, the read address 2(ra2) to “0001”,
the read address 3(ra3) to “0010”, the read address 4(ra4) to “0011”, write enable (we)
signal to ‘1’ and write address (wa) to “0001”, and input data (datain) to “00000010”.
Figure 7.8: Item Tracker Simulation 1
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As expected, the dout2 is updated once the write enable(we) signal is turn on. Storing the
value from input data (datain) to the respective write address (wa) as specified.
7.5 SIMULATION RESULT: REVENUE COUNTER
Test One: In this test, all the item_out (itemA_out to itemD_out) signals are set to ‘1’ for
one clock cycle sequentially. The expected outcome of the total revenue is the sum of
itemA’ price, itemB’price, itemC’price and itemD’price. The total revenue should add
up to a value of 10 (“1010”), this value (totalrev) is the same as shown in the figure
below.
Figure 7.9: Revenue Counter Simulation 1
With the result shown above, this module is functioning properly as per designed.
7.6 SIMULATION RESULT: CLOCK DIVIDER
Test One: In this test, the clock in is set to 50Mhz , 20 ns clock cycle.
Figure 7.10: Clock Divider Simulation 1
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The delta between the first rising edge to the next rising edge is 1,000,000,000,000 ps,
which equals to 1 sec. With the reading shown, the clock divider module had proven that
it can generate the 1 Hz clock cycle with high accuracy.
7.7 SIMULATION RESULT: VENDINGMACH
This simulation test checks on the functionality of the vendingmach module. This module
is the top module for the rest of the seven modules.
Test One: Simulate the user inserting one fiftycent coin and select itemA.
The expected result: itemA_out will be on, change of 10 cent to be returned and update
the itemA_count, the total revenue is also updated.
Figure 7.11: VendingMach Simulation 1
The results from the simulation matches the expected results stated above.
Test Two: Simulate the user inserting one fiftycent coin and select itemC.
The expected result: No transaction will be processed, the requirecoins signal will be on
for one clock cycle.
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Figure 7.12: VendingMach Simulation 2
The results from the simulation matches the expected results stated above and pass this
test.
Test Three: Simulate the user inserting one fiftycent coin and select itemA, but itemA
count is zero.
The expected result: No transaction will be processed, the item_soldout signal will be on
for one clock cycle.
Figure 7.13: VendingMach Simulation 3
This simulated result and the expected result matches.
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Test Four: Simulate the user inserting one dollar coin. Pressing of the reset button.
The expected result: No transaction will be processed, the amount inserted one dollar will
be returned.
Figure 7.14: VendingMach Simulation 4
On the simulation waveform, once the reset signal is turn on, the total amount inserted is
returned. One dollarout signal is turn on and clear the count_out value.
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8. Hardware Realization
8.1 DOWNLOAD OF PROGRAM TO FPGA.
Below listed are the steps to be followed in order to download the program into the
FPGA.
Figure 8.1: Processes Window
1) Double-click on the Synthesize-XST. Once done the orange question mark
will turn into a green indicator.
2) Double-click on the Implement Design. Wait for the process to finish.
3) Double-click on the Generate Programming File. When done proceed to next
step.
4) Double-click on the Configure Target Device. The ISE IMPACT window will
pop up shown below.
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Figure 8.2: ISE IMPACT Window1
1) Click on the icon button as shown.
Figure 8.3: ISE IMPACT Window 2
1) Click on the first radio button.
2) Click OK button.
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Figure 8.4: ISE IMPACT Window 3
1)Right click on the XC3A700A and select the assign new configuration.
Figure 8.5: ISE IMPACT Window 4
A new window will appear. Select the bit file to be loaded into the FPGA as shown.
Then press on the Open button as shown in Figure 8.4.
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After this the program will be loaded into the FPGA.
8.2 EXPANSION THROUGH 6-PIN ACCESSORY HEADER
Figure 8.6: Expansion Port[11]
Although the Spartan 3A Starter Kit has 8 discrete LEDs on board, it is insufficient to
output the required signals. Therefore additional LEDs are added through the 6 pin
accessory header to fulfill the requirement.
Figure 8.7: FPGA Connections To J18 Accessory Header
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8.3 LED CIRCUIT TO ACCESSORY HEADER
Figure 8.8: LED Circuit Diagram [13]
This circuit is implemented on a bread board. The table below shows the list of
components used to construct the circuit. In table 8.2 shows the pin connections from the
circuit to FPGA.
Components
Reference:
Green LEDs
LD0,LD1,LD2,LD3
100 Ohms Resistor
R1,R2,R3,R4
2.2K Ohms Resistor
R5,R6,R7,R8
NPN Transistor (2N3904)
Q1,Q2,Q3,Q4
Table 8.1: Components List For LED Circuit
The value of R1 is obtained using Ohm’s Law. The supply voltage (Vcc) is 3.3V. The
voltage drop of the LED(Vf) is 1.8V, the operating current(Ic) for the LED is 15mA.[14]
R1 = (Vcc – Vf)/Ic = (3.3 – 1.8)/ 15mA = 100 Ohms.
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Figure 8.9: Circuit Implementation on Bread Board.
Connections From Circuit
To FPGA Pin
LD0
AA21
LD1
AB21
LD2
AA19
LD3
AB19
GND
GND
VCC
VCC
Table 8.2: Connections Pin Out From LED Circuit To FPGA
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8.4 MAPPING OF USER INPUTS AND OUTPUTS
Below stated is the mapping of user input and output used VendingMach design:
Figure 8.10: Locations Of Push Buttons
The button that simulates the insertion of 10 cent is “T16”(BTN_SOUTH).
The button that simulates the insertion of 20 cent is “T14”.(BTN_NORTH).
The button that simulates the insertion of 50 cent is “T15”.(BTN_EAST)
The button that simulates the insertion of 1 dollar is “U15”.(BTN_WEST)
The button that simulates the coin return is “R13”.(ROT_CENTER)
Figure 8.11: Locations Of Slide Switches
The slide switch that simulates the selection of itemA is SW3(T9)
The slide switch that simulates the selection of itemB is SW2(U8)
The slide switch that simulates the selection of itemC is SW1(U10)
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The slide switch that simulates the selection of itemD is SW0(V8)
Figure 8.12: Locations Of LEDs For Individual Return Out
The LED that indicates the signal ten_centout is AA21.
The LED that indicates the signal twenty_centout is AB21.
The LED that indicates the signal fifty_centout is AA19.
The LED that indicates the signal one_dollarout is AB19.
Figure 8.13: Locations Of LEDs
The LED that indicates the signal requirecoins is LED7(W21).
The LED that indicates the signal item_soldout is LED6(Y22).
The LED that indicates the signal excess_money (bit 3) is LED3(U19).
The LED that indicates the signal excess_money (bit 2) is LED2(U20).
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The LED that indicates the signal excess_money (bit 1) is LED1(T19).
The LED that indicates the signal excess_money (bit 0) is LED0(R20).
Figure 8.14: Information Display On LCD
The picture above shows the information display on the LCD. At the top, it displays the
total amount inserted, on the second line of the LCD it displays the total change return,
the product selected and the total revenue of the machine. Refer to the pins mapping as
discussed in the previous chapters.
8.5 PREPARING AN SPI PROM FILE
The following steps graphically describe how to create an SPI-formatted PROM file
using IMPACT from within the ISE Project Navigator.
1. From within the ISE Project Navigator, double-click Generate PROM, ACE, or JTAG
File from within the Process pane, as shown below.
Figure 8.15: Process Panel
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2. Double click on the Create PROM File(PROM File Format.)
.
Figure 8.16: iMPACT Flows Panel
3. Click on the Configure Single FPGA under the SPI Flash.
4. Click on the next arrow.
5. Select “16M” from the drop list menu.
6. Click on the next arrow.
7. Input a file name at the textbox beside “Output File Name”.
8. Click Ok button.
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Figure 8.17: PROM File Formatter Window
9. Click Ok button on the Add Device window.
Figure 8.18: Add Device Window 1
10. Browse to the directory and select the .bit file to download and click on the Open
button.
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Figure 8.19: Add Device Window 2
11. Double click on the Generate File in the iMPACT Processes window.
Figure 8.20: iMPACT Processes Window
12. The screen will show a Generate Succeeded.
Figure 8.16: Generate Succeeded
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8.6 CONFIGURING SPI FLASH PROM
Direct Programming Method [15]
The iMPACT software supports direct programming of select SPI serial Flash. The
Spartan-3A/3AN Starter Kit board primarily supports direct programming using the
embedded USB JTAG programmer included on the board.
Using Embedded USB JTAG Programmer [15]
Follow these steps to prepare the board for direct SPI Flash programming using the
embedded USB JTAG programmer included on the board.
1. Disconnect power to the board.
2. Connect either a USB cable between the board and the PC.
3. Locate the J1, J23, and J25 jumpers in the upper right corner of the board.
The J1 jumper block defines which SPI Flash PROM is connected to the FPGA for
Master SPI mode configuration.
Figure 8.21: SPI Jumper J1 Setting
Set the J1 Jumper Block to the pointed setting, the STMicro M25P16 will be used.
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Figure 8.22: SPI Jumper J26 Settings
Set the Jumper J26 as shown above, to set it to Master SPI mode.\
4. Insert a jumper in jumper block J1. The figure shows the setting to program the
STMicro M25P16 PROM.
5. Insert four jumpers between jumper blocks J25 and J23.
These jumpers connect the embedded USB JTAG programmer on the J25 jumper pins to
the SPI PROM via the J23 jumper pins.
Figure 8.23: SPI Jumpers J23, J25 and J16 Settings
6. Set the FPGA mode select pins for Master SPI mode using jumper J26.
7. Disable the Platform Flash PROM by removing jumper J46.
8. For direct programming, the FPGA’s PROG_B pin must be held Low. Insert a jumper
in jumper J16.This holds all the FPGA’s I/O in three-state to allow the JTAG
programmer full access to the SPI PROM pins.
9. Re-apply power to the board.
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9 CONCLUSION AND RECOMMEDATION
9.1 CONCLUSION
The objectives of the project set during the initial phase of the project are met. The
developed prototype vending machine fulfills all the specifications stated in the earlier
chapter. This vending machine kept tally of its four items and total revenue. It vended the
item requested and returned change.
To indicate special cases such as ‘soldout’ and ‘require more money’. The hardware
implementation of the vending machine had a LCD display enabling the user to note the
money inserted, change returned and total revenue. The amount of change is indicated by
LEDs on the board.
9.2 RECOMMEDATION FOR FUTURE STUDY
The developed prototype vending machine stills have rooms for improvement.
As the values of the register is implemented on volatile memory, once it is power off, the
data is lost. For future development, one should look into storing the important data into
non-volatile memory,(FLASH Memory) which is available on the Spartan 3A board.
The change amount is designed in a predefined method. They can look into ways to keep
track of the change left inside the machine and dispense accordingly while ensuring there
is enough coins for the change.
Another area of modification is to find a way to communicate to a PC through the
Ethernet port to send and receive data. The data might be the quantities of goods left in
the vending or sending a request to replenish the vending machine.
Another suggestion is to interface it with card reader or RFID reader. As cashless
transaction is the “in thing” nowadays because it is fast and hassle free.
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10 REFLECTION
Building a vending machine prototype with FPGA is a new and challenging project for
me. The first step is always the hardest, the project starts with literature research. This is
also one of the most important tasks of the project. I have started with no knowledge on
FPGA and VHDL through the World Wide Web, the main source of information and
books from the library. I have picked up adequate knowledge through the literature
research and also improve my skills on picking out useful information.
After this, I prepared my project initial report which includes project objectives,
investigation of project background, project management, proposed approaches and
methods to be employed as well as skills review. As initial planning is important in order
to complete the objectives, proposed approaches were systematically analyzed and
selected. These works improve my project management skills and provide a roadmap on
the project implementation.
During the project development, I encountered numerous problems and difficulties.
When problem arises, frustration is bound to present. Problem solving skills is one of the
critical skills that is essential to develop in order to keep the project constantly moving.
At times I have to resolve the problems independently which in some scenario, I had to
seek for the right resources and supports. I have learned to be more resourceful and to
work more independently as well.
Another challenge for me is to manage time effectively. Besides doing this project, I have
to cope with my other modules and heavy work load at work. The initial development
phase for the project is lagging against the projected timeline. Knowing that I must
improve on this drawback, I tried to finish the scheduled task before the projected
timeline. It has also taught me a lesson that good time management plays an important
role in planning and ensuring all tasks are running as smoothly as scheduled.
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In conclusion, this is a very fruitful practical hands-on experience to equip me with better
understanding and knowledge. Most importantly, the skill sets (technical and
management) learned during this project can be applied to future work.
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APPENDICE
Source Code
-- Module Name: vendingmach - Behavioral
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vendingmach is
port ( clk : in std_logic;
reset : in std_logic;
tencent : in std_logic;
twentycent : in std_logic;
fiftycent : in std_logic;
dollar : in std_logic;
count_out : inout std_logic_vector(3 downto 0);
excess_money : inout std_logic_vector(3 downto 0);
changeret : inout std_logic_vector(3 downto 0);
item_select : in STD_LOGIC_vector(3 downto 0);
itemA_out : inout STD_LOGIC;
itemB_out : inout STD_LOGIC;
itemC_out : inout STD_LOGIC;
itemD_out : inout STD_LOGIC;
change : inout std_logic_vector(3 downto 0) ;
clearcount: inout STD_LOGIC;
ten_centout : out STD_LOGIC;
twenty_centout : out STD_LOGIC;
fifty_centout : out STD_LOGIC;
one_dollarout : out STD_LOGIC;
changedone : inout STD_LOGIC;
requirecoins: inout STD_LOGIC;
item_soldout: inout STD_LOGIC;
totalrev : inout std_logic_vector(7 downto 0);
control : out std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 0)
);
end vendingmach;
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architecture Behavioral of vendingmach is
component clkdivider is
port ( clk : in std_logic;
slow_clk : out std_logic);
end component;
component revenuecounter is
Port(
clk : IN std_logic;
itemA_out : IN std_logic;
itemB_out : IN std_logic;
itemC_out : IN std_logic;
itemD_out : IN std_logic;
totalrev : OUT std_logic_vector(7 downto 0));
end component;
component ram is
Port( clk : in std_logic;
we : in std_logic;
wa : in std_logic_vector(3 downto 0);
ra1 : in std_logic_vector(3 downto 0);
ra2 : in std_logic_vector(3 downto 0);
ra3 : in std_logic_vector(3 downto 0);
ra4 : in std_logic_vector(3 downto 0);
datain : in std_logic_vector(7 downto 0);
dout1 : out std_logic_vector(7 downto 0);
dout2 : out std_logic_vector(7 downto 0);
dout3 : out std_logic_vector(7 downto 0);
dout4 : out std_logic_vector(7 downto 0));
end component;
component lcd_control is
Port ( rst
: in STD_LOGIC;
clk
: in STD_LOGIC;
coinin : in std_logic_vector (3 downto 0);
change : in std_logic_vector (3 downto 0);
productselect : in std_logic_vector (3 downto 0);
totalrev: in std_logic_vector (7 downto 0);
control
: out std_logic_vector (2 downto 0); -- LCD_RS,
LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 0)); --LCD data bus
end component;
component counter is
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Port( clk : in std_logic;
reset : in std_logic;
tencent : in std_logic;
twentycent : in std_logic;
fiftycent : in std_logic;
dollar : in std_logic;
count_out : out std_logic_vector(3 downto 0);
excess_money : out std_logic_vector(3 downto 0);
changedone : in STD_LOGIC;
clearcount: in STD_LOGIC);
end component;
component itemprocessor is
Port( clk : in STD_LOGIC;
reset : in STD_LOGIC;
item_select : in STD_LOGIC_vector(3 downto 0);
total_amount : in std_logic_vector(3 downto 0);
itemA_count: in std_logic_vector(7 downto 0);
itemB_count: in std_logic_vector(7 downto 0);
itemC_count: in std_logic_vector(7 downto 0);
itemD_count: in std_logic_vector(7 downto 0);
itemA_out : out STD_LOGIC;
itemB_out : out STD_LOGIC;
itemC_out : out STD_LOGIC;
itemD_out : out STD_LOGIC;
clearcount: out STD_LOGIC;
item_soldout: out STD_LOGIC;
requirecoins: out STD_LOGIC;
we: out std_logic;
waddr :
out std_logic_vector(3 downto 0);
data_count: out std_logic_vector(7 downto 0);
change : out std_logic_vector(3 downto 0));
end component;
component changereturn is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
change : in std_logic_vector(3 downto 0);
changeret : inout std_logic_vector(3 downto 0);
ten_centout : out STD_LOGIC;
twenty_centout : out STD_LOGIC;
fifty_centout : out STD_LOGIC;
one_dollarout : out STD_LOGIC;
changedone : out STD_LOGIC);
end component;
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Stud ID:E0706681
signal we :std_logic;
signal wa :std_logic_vector(3 downto 0);
signal ra1 :std_logic_vector(3 downto 0):="0000";
signal ra2 :std_logic_vector(3 downto 0):="0001";
signal ra3 :std_logic_vector(3 downto 0):="0010";
signal ra4 :std_logic_vector(3 downto 0):="0011";
signal clk_slow : std_logic;
signal datain,cout1,cout2,cout3,cout4 :std_logic_vector(7 downto 0);
begin
slowclk : clkdivider
Port map ( clk => clk,
slow_clk => clk_slow);
coincounter: counter
Port map ( clk => clk_slow,
--clk => clk,
reset => reset,
tencent => tencent,
twentycent => twentycent,
fiftycent => fiftycent,
dollar => dollar,
count_out => count_out,
excess_money => excess_money,
changedone => changedone,
clearcount => clearcount);
itemsselect:itemprocessor
Port map (
clk => clk_slow,
--clk => clk,
reset => reset,
item_select =>item_select,
total_amount => count_out,
itemA_count => cout1,
itemB_count => cout2,
itemC_count => cout3,
itemD_count => cout4,
itemA_out => itemA_out,
itemB_out => itemB_out,
itemC_out => itemC_out,
itemD_out => itemD_out,
clearcount => clearcount,
requirecoins => requirecoins,
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item_soldout => item_soldout,
we => we,
waddr => wa,
data_count => datain,
change => change);
change_generate:changereturn
Port map (
clk => clk_slow,
--clk => clk,
reset => reset,
change => change,
ten_centout => ten_centout,
twenty_centout => twenty_centout,
fifty_centout => fifty_centout,
one_dollarout => one_dollarout,
changeret => changeret,
changedone => changedone);
lcd_display:lcd_control
Port map(
rst => reset,
--clk => clk_slow,
clk => clk,
coinin => count_out,
change => change,
productselect => item_select,
totalrev => totalrev,
control
=> control, -- LCD_RS, LCD_RW, LCD_E
sf_d => sf_d); --LCD data bus
itemtracker:ram
Port map(
clk => clk_slow,
--clk => clk,
we => we,
wa => wa,
ra1 => ra1,
ra2 => ra2,
ra3 => ra3,
ra4 => ra4,
datain => datain,
dout1 => cout1,
dout2 => cout2,
dout3 => cout3,
dout4 => cout4);
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totalrevenue:revenuecounter
Port map(
clk => clk_slow,
--clk => clk,
itemA_out => itemA_out,
itemB_out => itemB_out,
itemC_out => itemC_out,
itemD_out => itemD_out,
totalrev => totalrev);
end Behavioral;
-- Module Name:
clkdivider - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkdivider is
port ( clk : in std_logic;
slow_clk : out std_logic);
end clkdivider;
architecture Behavioral of clkdivider is
signal clk_divider : std_logic_vector(23 downto 0) := x"000000";
begin
-- Process that makes slow clock go high only when MSB of
-- clk_divider goes high.
clk_division : process (clk, clk_divider)
begin
if (clk = '1' and clk'event) then
clk_divider <= clk_divider + 1;
end if;
slow_clk <= clk_divider(23);
end process;
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port ( clk : in std_logic;
reset : in std_logic;
tencent : in std_logic;
twentycent : in std_logic;
fiftycent : in std_logic;
dollar : in std_logic;
count_out : out std_logic_vector(3 downto 0);
excess_money : out std_logic_vector(3 downto 0);
changedone : in STD_LOGIC;
clearcount: in STD_LOGIC:= '0');
end counter;
architecture Behavioral of counter is
signal temp_count : std_logic_vector(3 downto 0) := x"0";
signal slow_clk : std_logic;
signal state_reg,next_state: std_logic_vector(3 downto 0):= X"0";
shared variable totalamount : std_logic_vector(3 downto 0);
signal tmpexcess_coins : std_logic_vector(3 downto 0);
end process;
process (clk , reset )
begin
if (reset = '1') then
elsif ( clk'event and clk = '1') then
if (changedone = '1') or (clearcount = '1') then
state_reg <= "0000";
totalamount := "0000";
else
state_reg <= next_state;
excess_money <= tmpexcess_coins;
end if;
end if ;
end process;
process ( state_reg,tencent,twentycent,fiftycent,dollar)
begin
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Stud ID:E0706681
case state_reg is
when "0000" =>
count_out <= "0000";
if tencent = '1' then
next_state <= "0001";-- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0010"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "0101"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0000";
else
next_state <= "0000";
tmpexcess_coins <= "0000";
end if;
--10 cents
when "0001" =>
count_out <= "0001";
if tencent = '1' then
next_state <= "0010"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0011"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "0110"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0001";-- Return excess coins
else
next_state <= "0001";
tmpexcess_coins <= "0000";
end if;
--20 cents
when "0010" =>
count_out <= "0010";
if tencent = '1' then
next_state <= "0011"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0100"; -- Counter increase
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tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "0111"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0010";-- Return excess coins
else
next_state <= "0010";
end if;
--30 cents
when "0011" =>
count_out <= "0011";
if tencent = '1' then
next_state <= "0100"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0101"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1000"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0011";-- Return excess coins
else
next_state <= "0011";
tmpexcess_coins <= "0000";
end if;
--40 cents
when "0100" =>
count_out <= "0100";
if tencent = '1' then
next_state <= "0101"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0110"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1001"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0100";-- Return excess coins
else
next_state <= "0100";
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tmpexcess_coins <= "0000";
end if;
--50 cents
when "0101" =>
count_out <= "0101";
if tencent = '1' then
next_state <= "0110"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "0111"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0000";
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0101";-- Return excess coins
else
next_state <= "0101";
tmpexcess_coins <= "0000";
end if;
--60 cents
when "0110" =>
count_out <= "0110";
if tencent = '1' then
next_state <= "0111"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "1000"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0001";-- Return excess coins
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0110";-- Return excess coins
else
next_state <= "0110";
tmpexcess_coins <= "0000";
end if;
--70 cents
when "0111" =>
count_out <= "0111";
if tencent = '1' then
next_state <= "1000"; -- Counter increase
tmpexcess_coins <= "0000";
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elsif twentycent = '1' then
next_state <= "1001"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0010";-- Return excess coins
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0111";-- Return excess coins
else
next_state <= "0111";
tmpexcess_coins <= "0000";
end if;
--80 cents
when "1000" =>
count_out <= "1000";
if tencent = '1' then
next_state <= "1001"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0000";
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0011";-- Return excess coins
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "1000";-- Return excess coins
else
next_state <= "1000";
tmpexcess_coins <= "0000";
end if;
--90 cents
when "1001" =>
count_out <= "1001";
if tencent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0000";
elsif twentycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0001";-- Return excess coins
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0100";-- Return excess coins
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
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tmpexcess_coins <= "1001";-- Return excess coins
else
next_state <= "1001";
tmpexcess_coins <= "0000";
end if;
--100 cents
when "1010" =>
count_out <= "1010";
if tencent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0001";
elsif twentycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0010";-- Return excess coins
elsif fiftycent = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "0101";-- Return excess coins
elsif dollar = '1' then
next_state <= "1010"; -- Counter increase
tmpexcess_coins <= "1010";-- Return excess coins
else
next_state <= "1010";
tmpexcess_coins <= "0000";
end if;
when others =>
end case;
-- Output
end process;
end Behavioral; -- End module.
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-- Module Name:
Name :Chen Junhao
Stud ID:E0706681
itemprocessor - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity itemprocessor is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
item_select : in STD_LOGIC_vector(3 downto 0);
total_amount : in std_logic_vector(3 downto 0);
itemA_count: in std_logic_vector(7 downto 0);
itemB_count: in std_logic_vector(7 downto 0);
itemC_count: in std_logic_vector(7 downto 0);
itemD_count: in std_logic_vector(7 downto 0);
itemA_out : out STD_LOGIC;
itemB_out : out STD_LOGIC;
itemC_out : out STD_LOGIC;
itemD_out : out STD_LOGIC;
clearcount: out STD_LOGIC;
requirecoins: out STD_LOGIC;
item_soldout: out STD_LOGIC;
we: out std_logic;
waddr :
out std_logic_vector(3 downto 0);
data_count: out std_logic_vector(7 downto 0);
change : out std_logic_vector(3 downto 0));
end itemprocessor;
architecture Behavioral of itemprocessor is
signal tmpcountA : std_logic_vector(7 downto 0);
signal tmpcountB : std_logic_vector(7 downto 0);
signal tmpcountC : std_logic_vector(7 downto 0);
signal tmpcountD : std_logic_vector(7 downto 0);
signal productsel_flag : std_logic ;
process(clk,item_select,total_amount,itemA_count)
constant itemA : integer := 4;
constant itemB : integer := 5;
constant itemC : integer := 6;
constant itemD : integer := 7;
variable temp :std_logic_vector(3 downto 0):= "0000";
variable tmp_waddr :std_logic_vector(3 downto 0):= "0000";
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variable tmp_data :std_logic_vector(7 downto 0):= "00000000";
variable tmp_we: std_logic;
begin
if (reset = '1') then
temp := total_amount;
elsif(clk'event and clk ='1') then
case item_select is
when "0001" =>
if(total_amount >= 4) and (itemA_count > 0) then
temp := total_amount - itemA;
productsel_flag <= '1';
if productsel_flag <= '0' then
--update count in ram memory
itemA_out <= '1';
waddr <= "0000";
tmp_data := itemA_count - 1;
we <= '1';
else
we <= '0';
itemA_out <= '0';
end if;
--if no change required
if total_amount = itemA then
clearcount <= '1';
end if;
else
if (itemA_count = 0) and (total_amount >= 4)then
item_soldout <= '1';
elsif (total_amount < itemA) then
requirecoins <= '1';
end if;
itemA_out <= '0';
temp := "0000";
end if;
--elsif (item_select = "0010") then
when "0010" =>
if(total_amount >= 5) and (itemB_count > 0) then
temp := total_amount - itemB;
--update count in ram memory
if productsel_flag <= '0' then
itemB_out <= '1';
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waddr <= "0001";
tmp_data := itemB_count - 1;
we <= '1';
productsel_flag <= '1';
else
we <= '0';
itemB_out <= '0';
end if;
--if no change required
if total_amount = itemB then
clearcount <= '1';
end if;
else
if (itemB_count = 0) and (total_amount >= 5) then
item_soldout <= '1';
else
requirecoins <= '1';
end if;
itemB_out <= '0';
temp := "0000";
end if;
--elsif (item_select = "0100") then
when "0100" =>
if(total_amount >= 6) and (itemC_count > 0) then
temp := total_amount - itemC;
if productsel_flag <= '0' then
itemC_out <= '1';
waddr <= "0010";
tmp_data := itemC_count - 1;
we <= '1';
productsel_flag <= '1';
else
we <= '0';
itemC_out <= '0';
end if;
--if no change required
if total_amount = itemC then
clearcount <= '1';
end if;
else
if (itemC_count = 0) and (total_amount >= 6) then
item_soldout <= '1';
else
requirecoins <= '1';
end if;
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itemC_out <= '0';
temp := "0000";
end if;
--elsif (item_select = "1000") then
when "1000" =>
if(total_amount >= 7) and (itemD_count > 0) then
temp := total_amount - itemD;
if productsel_flag <= '0' then
itemD_out <= '1';
waddr <= "0011";
tmp_data := itemD_count - 1;
we <= '1';
productsel_flag <= '1';
else
we <= '0';
itemD_out <= '0';
end if;
--if no change required
if total_amount = itemD then
clearcount <= '1';
end if;
else
if (itemD_count = 0) and (total_amount >= 7)then
item_soldout <= '1';
else
requirecoins <= '1';
end if;
itemD_out <= '0';
temp := "0000";
end if;
--else
when others =>
itemA_out <= '0';
itemB_out <= '0';
itemC_out <= '0';
itemD_out <= '0';
item_soldout <= '0';
--turn off write enable ram memory
waddr <= "1000";
data_count <= X"00";
we <= '0';
productsel_flag <= '0';
temp := "0000";
clearcount <= '0';
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requirecoins <= '0';
--end if;
end case;
end if;
change <= temp;
data_count <= tmp_data;
end process;
end Behavioral;
-- Module Name:
changereturn - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity changereturn is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
change : in std_logic_vector(3 downto 0);
changeret : inout std_logic_vector(3 downto 0);
ten_centout : out STD_LOGIC:='0';
twenty_centout : out STD_LOGIC:='0';
fifty_centout : out STD_LOGIC:='0';
one_dollarout : out STD_LOGIC:='0';
changedone : out STD_LOGIC);
end changereturn;
architecture Behavioral of changereturn is
signal state_reg : std_logic_vector(3 downto 0):= "1110";
signal state_next: std_logic_vector(3 downto 0):= x"0";
shared variable ten_out,twenty_out,fifty_out,dollar_out,count: std_logic;
shared variable tempchange : std_logic_vector(3 downto 0);
shared variable donestatus : std_logic;
signal slow_clk : std_logic;
begin
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process ( clk , reset )
begin
if (reset = '1') then
state_reg <= change;
changedone <= donestatus;
elsif (clk'event and clk = '1') then
if state_reg = "0000" or state_reg = "1110" then
state_reg <= change;
changedone <= donestatus;
else
state_reg <= state_next;
one_dollarout <= dollar_out;
fifty_centout <= fifty_out;
twenty_centout <= twenty_out;
ten_centout <= ten_out;
changedone <= donestatus;
end if;
end if ;
end process;
process ( state_reg,change )
begin
case state_reg is
-- when change is 0
when "0000" =>
changeret <= "0000";
dollar_out := '0';
fifty_out := '0';
twenty_out := '0';
ten_out := '0';
state_next <= "1101";
donestatus := '0';
-- when change is 1
when "0001" =>
changeret <= "0001";
dollar_out := '0';
fifty_out := '0';
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Stud ID:E0706681
twenty_out := '0';
ten_out := '1';
state_next <= "1111";
donestatus := '0';
--when change is 2
when "0010" =>
changeret <= "0010";
dollar_out := '0';
fifty_out := '0';
twenty_out := '1';
ten_out := '0';
state_next <= "1111";
donestatus := '0';
--when change is 3
when "0011" =>
changeret <= "0011";
dollar_out := '0';
fifty_out := '0';
twenty_out := '1';
ten_out := '1';
state_next <= "1111";
donestatus := '0';
--when change is 4
when "0100" =>
changeret <= "0100";
dollar_out := '0';
fifty_out := '0';
twenty_out := '1';-- return 20 cents
ten_out := '0';
state_next <= "0010"; -- go to state2 to return another 20 cents
donestatus := '0';
--when change is 5
when "0101" =>
changeret <= "0101";
dollar_out := '0';
fifty_out := '1';
twenty_out := '0';
ten_out := '0';
state_next <= "1111";
donestatus := '0';
--when change is 6
when "0110" =>
changeret <= "0110";
dollar_out := '0';
fifty_out := '1';
twenty_out := '0';
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ten_out := '1';
state_next <= "1111";
donestatus := '0';
--when change is 7
when "0111" =>
changeret <= "0111";
dollar_out := '0';
fifty_out := '1';
twenty_out := '1';
ten_out := '0';
state_next <= "1111";
donestatus := '0';
--when change is 8
when "1000" =>
changeret <= "1000";
dollar_out := '0';
fifty_out := '1';
twenty_out := '1';
ten_out := '1';
state_next <= "1111";
donestatus := '0';
--when change is 9
when "1001" =>
changeret <= "1001";
dollar_out := '0';
fifty_out := '1';
twenty_out := '1';
ten_out := '0';
--return 70 cents
state_next <= "0010";-- jump to state 2 to return 20 cents
donestatus := '0';
--when change is 10
when "1010" =>
changeret <= "1010";
dollar_out := '1';
fifty_out := '0';
twenty_out := '0';
ten_out := '0';
state_next <= "1111";
donestatus := '0';
when "1110" =>
changeret <= "1110";
dollar_out := '0';
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fifty_out := '0';
twenty_out := '0';
ten_out := '0';
donestatus := '0';
if not(change = 0) then
state_next <= change;
end if;
when "1111" =>
changeret <= "0000";
dollar_out := '0';
fifty_out := '0';
twenty_out := '0';
ten_out := '0';
donestatus := '1';
state_next <= "1110";
when others =>
end case;
end process;
end Behavioral;
===============================================================
--- Multiple-Port RAM Descriptions
-library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is
port (clk : in std_logic;
we : in std_logic;
wa : in std_logic_vector(3 downto 0);
ra1 : in std_logic_vector(3 downto 0);
ra2 : in std_logic_vector(3 downto 0);
ra3 : in std_logic_vector(3 downto 0);
ra4 : in std_logic_vector(3 downto 0);
datain : in std_logic_vector(7 downto 0);
dout1 : out std_logic_vector(7 downto 0);
dout2 : out std_logic_vector(7 downto 0);
dout3 : out std_logic_vector(7 downto 0);
dout4 : out std_logic_vector(7 downto 0));
end ram;
architecture syn of ram is
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type ram_type is array (0 to 15) of std_logic_vector (7 downto
0);
signal RAM : ram_type:= ( X"05",X"05",X"05",X"05",
X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00"
);
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
RAM(conv_integer(wa)) <= datain;
end if;
end if;
end process;
dout1 <= RAM(conv_integer(ra1));
dout2 <= RAM(conv_integer(ra2));
dout3 <= RAM(conv_integer(ra3));
dout4 <= RAM(conv_integer(ra4));
end syn;
-- Module Name: revenuecounter - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity revenuecounter is
Port ( clk : in STD_LOGIC;
itemA_out : in STD_LOGIC;
itemB_out : in STD_LOGIC;
itemC_out : in STD_LOGIC;
itemD_out : in STD_LOGIC;
totalrev : out STD_LOGIC_VECTOR (7 downto 0)
);
end revenuecounter;
architecture Behavioral of revenuecounter is
signal temp: std_logic_vector(7 downto 0):= x"00";
signal dectemp: std_logic_vector(7 downto 0):= x"00";
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begin
process(clk,itemA_out,itemB_out,itemC_out,itemD_out)
constant itemA : std_logic_vector(7 downto 0) := X"01";
constant itemB : std_logic_vector(7 downto 0) := X"02";
constant itemC : std_logic_vector(7 downto 0) := X"03";
constant itemD : std_logic_vector(7 downto 0) := X"04";
begin
if(clk'event and clk ='1') then
if itemA_out = '1' then
temp <= temp + itemA;
elsif itemB_out = '1' then
temp <= temp + itemB;
elsif itemC_out = '1' then
temp <= temp + itemC;
elsif itemD_out = '1' then
temp <= temp + itemD;
else
temp <= temp + "00000000";
end if;
end if;
if temp = "00000000" then -- 0
dectemp <= "00000000";
elsif temp = "00000001" then --1
dectemp <= "00000001";
elsif temp = "00000010" then --2
dectemp <= "00000010";
elsif temp = "00000011" then --3
dectemp <= "00000011";
elsif temp = "00000100" then --4
dectemp <= "00000100";
elsif temp = "00000101" then --5
dectemp <= "00000101";
elsif temp = "00000110" then --6
dectemp <= "00000110";
elsif temp = "00000111" then --7
dectemp <= "00000111";
elsif temp = "00001000" then --8
dectemp <= "00001000";
elsif temp = "00001001" then --9
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dectemp <= "00001001";
elsif temp = "00001010" then --10
dectemp <= "00010000";
elsif temp = "00001011" then --11
dectemp <= "00010001";
elsif temp = "00001100" then --12
dectemp <= "00010010";
elsif temp = "00001101" then --13
dectemp <= "00010011";
elsif temp = "00001110" then --14
dectemp <= "00010100";
elsif temp = "00001111" then --15
dectemp <= "00010101";
elsif temp = "00010000" then --16
dectemp <= "00010110";
elsif temp = "00010001" then --17
dectemp <= "00010111";
elsif temp = "00010010" then --18
dectemp <= "00011000";
elsif temp = "00010011" then --19
dectemp <= "00011001";
elsif temp = "00010100" then --20
dectemp <= "00100000";
end if;
totalrev <= dectemp;
end process;
end Behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd_control is
port (
rst
: in STD_LOGIC;
clk
: in STD_LOGIC;
coinin : in std_logic_vector (3 downto 0);
change : in std_logic_vector (3 downto 0);
productselect: in std_logic_vector (3 downto 0);
totalrev : in std_logic_vector (7 downto 0);
control : out std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 0)); --LCD data bus
end lcd_control;
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architecture lcd_control_arch of lcd_control is
type state_type is (waiting, init1,init2,init3,init4,init5,init6,init7,
word1,word2,word3,word4,word5,
word6,word7,
word8,word9,
wordb1,wordb2,wordb3,
wordb4,wordb5,wordb6,
wordb7,wordb8,
wordc,wordc0,
wordc1,wordc2,wordc3,
wordc4,
word_display11,word_display12,
word_display14,
word_display15,word_display16,
word_display17,word_display18,
word_display19,
word_display20,word_display21,
word_display22,word_display23,
donestate);
signal state,next_state : state_type;
signal mode_state,next_mode_state : std_logic := '1';
signal sf_d_temp
: std_logic_vector (7 downto 0) := "00000000";
signal count, count_temp : integer := 0;
signal state_flag
: std_logic := '0';
signal tmprequirecoins : std_logic := '0';
signal tmpcount : integer:= 0;
constant TIME1 : integer := 750000;
constant TIME2 : integer := 1;
constant TIME3 : integer := 210000;
constant TIME4 : integer := 420000;
constant TIME5 : integer := 999999;
begin
run : process (clk,state,count,
coinin,change
) is
begin
case state is
-- Initialization Starts -------------------------------when waiting =>
sf_d_temp <= "00000000";
control <= "000";
-- RS, RW, E
if
(count >= TIME1) then
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next_state <= init1;
state_flag <= '1';
next_state <= waiting; state_flag <= '0';
else
end if;
when init1 =>
sf_d_temp <= "00111100";
--Function set DL = 8bit, NL = 2,
Font = 5x11
if
(count = TIME4) then
next_state <= init2;
control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init1; control <= "000"; state_flag <=
'0';
else next_state <= init1; control <= "001"; state_flag <= '0';
end if;
when init2 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2,
Font = 5x11
if
(count = TIME4) then
next_state <= init3;
control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init2; control <= "000"; state_flag <=
'0';
else next_state <= init2; control <= "001"; state_flag <= '0';
end if;
when init3 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2,
Font = 5x11
if
(count = TIME4) then
next_state <= init4;
control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init3; control <= "000"; state_flag <=
'0';
else next_state <= init3; control <= "001"; state_flag <= '0';
end if;
when init4 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2,
Font = 5x11
if
(count = TIME3) then
next_state <= init5;
control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init4; control <= "000"; state_flag <=
'0';
else
next_state <= init4; control <= "001"; state_flag <= '0';
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end if;
when init5 =>
sf_d_temp <= "00001100"; --Set Display Display=on,
Cursor=off, cursor_position=off
if
(count = TIME3) then
next_state <= init6; control <= "001"; state_flag <=
'1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init5; control <= "000"; state_flag <=
'0';
else next_state <= init5; control <= "001"; state_flag <= '0';
end if;
when init6 =>
sf_d_temp <= "00000001"; --Clear Display
--set_timer_flag <= '0'; set_clock_flag <= '0'; --reset display flags
if
(count = TIME3) then
next_state <= init7; control <= "001"; state_flag <=
'1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init6; control <= "000"; state_flag <=
'0';
else next_state <= init6; control <= "001"; state_flag <= '0';
end if;
when init7 =>
sf_d_temp <= "00000110"; --Entry Mode set ID=1, S=0
if
(count = TIME3) then
next_state <= word1; control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init7; control <= "000"; state_flag <=
'0';
else next_state <= init7; control <= "001"; state_flag <= '0';
end if;
-- Initialization Ends -----------------------------------
-------------------------Write out 'COINS IN:'----------------------when wordc =>
sf_d_temp <= "00000001"; --Clear Display
--set_timer_flag <= '0'; set_clock_flag <= '0'; --reset display flags
if
(count = TIME3) then
next_state <= wordc0; control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
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next_state <= wordc; control <= "000"; state_flag
<= '0';
else next_state <= wordc; control <= "001"; state_flag <= '0';
end if;
when wordc0 =>
sf_d_temp <= "00000110"; --Entry Mode set ID=1, S=0
if
(count = TIME3) then
next_state <= wordc1; control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordc0; control <= "000"; state_flag
<= '0';
else next_state <= wordc0; control <= "001"; state_flag <= '0';
end if;
when wordc1 =>
sf_d_temp <= "01001111"; -- C
if
(count = TIME3) then
next_state <= wordc2; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordc1; control <= "100"; state_flag
<= '0';
else next_state <= wordc1; control <= "101"; state_flag <= '0';
end if;
when wordc2 =>
sf_d_temp <= "01001111"; -- O
if
(count = TIME3) then
next_state <= wordc3; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordc2; control <= "100"; state_flag
<= '0';
else next_state <= wordc2; control <= "101"; state_flag <= '0';
end if;
when wordc3 =>
sf_d_temp <= "01001111"; -- I
if
(count = TIME3) then
next_state <= wordc4; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordc3; control <= "100"; state_flag
<= '0';
else next_state <= wordc3; control <= "101"; state_flag <= '0';
end if;
when wordc4 =>
sf_d_temp <= "01001110"; -- N
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Name :Chen Junhao
Stud ID:E0706681
(count = TIME3) then
next_state <= donestate; control <= "101";
state_flag <= '1';
tmpcount <= tmpcount + 1;
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordc4; control <= "100"; state_flag
<= '0';
else next_state <= wordc4; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out 'COINS IN:'----------------------when word1 =>
sf_d_temp <= "01000011"; -- C
if
(count = TIME3) then
next_state <= word2; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word1; control <= "100"; state_flag
<= '0';
else next_state <= word1; control <= "101"; state_flag <= '0';
end if;
when word2 =>
sf_d_temp <= "01001111"; -- O
if
(count = TIME3) then
next_state <= word3; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word2; control <= "100"; state_flag
<= '0';
else next_state <= word2; control <= "101"; state_flag <= '0';
end if;
when word3 =>
sf_d_temp <= "01001001"; -- I
if
(count = TIME3) then
next_state <= word4; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word3; control <= "100"; state_flag
<= '0';
else next_state <= word3; control <= "101"; state_flag <= '0';
end if;
when word4 =>
sf_d_temp <= "01001110"; -- N
if
(count = TIME3) then
next_state <= word5; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
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next_state <= word4; control <= "100"; state_flag
<= '0';
else next_state <= word4; control <= "101"; state_flag <= '0';
end if;
when word5 =>
sf_d_temp <= "01010011"; -- S
if
(count = TIME3) then
next_state <= word6; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word5; control <= "100"; state_flag
<= '0';
else next_state <= word5; control <= "101"; state_flag <= '0';
end if;
when word6 =>
sf_d_temp <= "10100000"; -- space
if
(count = TIME3) then
next_state <= word7; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word6; control <= "100"; state_flag
<= '0';
else next_state <= word6; control <= "101"; state_flag <= '0';
end if;
when word7 =>
sf_d_temp <= "01001001"; -- I
if
(count = TIME3) then
next_state <= word8; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word7; control <= "100"; state_flag
<= '0';
else next_state <= word7; control <= "101"; state_flag <= '0';
end if;
when word8 =>
sf_d_temp <= "01001110"; -- N
if
(count = TIME3) then
next_state <= word9; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word8; control <= "100"; state_flag
<= '0';
else next_state <= word8; control <= "101"; state_flag <= '0';
end if;
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when word9 =>
sf_d_temp <= "00111010"; -- :
if
(count = TIME3) then
next_state <= wordb1; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word9; control <= "100"; state_flag
<= '0';
else next_state <= word9; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out 'CHANGE:'----------------------when wordb1 =>
sf_d_temp <= "11000000"; -- Set Address hx40
if
(count = TIME3) then
next_state <= wordb2; control <= "001"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb1; control <= "000"; state_flag
<= '0';
else next_state <= wordb1; control <= "001"; state_flag <= '0';
end if;
when wordb2 =>
sf_d_temp <= "01000011"; -- C
if
(count = TIME3) then
next_state <= wordb3; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb2; control <= "100"; state_flag
<= '0';
else next_state <= wordb2; control <= "101"; state_flag <= '0';
end if;
when wordb3 =>
sf_d_temp <= "01001000"; -- H
if
(count = TIME3) then
next_state <= wordb4; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb3; control <= "100"; state_flag
<= '0';
else next_state <= wordb3; control <= "101"; state_flag <= '0';
end if;
when wordb4 =>
sf_d_temp <= "01000001"; -- A
if
(count = TIME3) then
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next_state <= wordb5; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb4; control <= "100"; state_flag
<= '0';
else next_state <= wordb4; control <= "101"; state_flag <= '0';
end if;
when wordb5 =>
sf_d_temp <= "01001110"; -- N
if
(count = TIME3) then
next_state <= wordb6; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb5; control <= "100"; state_flag
<= '0';
else next_state <= wordb5; control <= "101"; state_flag <= '0';
end if;
when wordb6 =>
sf_d_temp <= "01000111"; -- G
if
(count = TIME3) then
next_state <= wordb7; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb6; control <= "100"; state_flag
<= '0';
else next_state <= wordb6; control <= "101"; state_flag <= '0';
end if;
when wordb7 =>
sf_d_temp <= "01000101"; -- E
if
(count = TIME3) then
next_state <= wordb8; control <= "101"; state_flag
<= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb7; control <= "100"; state_flag
<= '0';
else next_state <= wordb7; control <= "101"; state_flag <= '0';
end if;
when wordb8 =>
sf_d_temp <= "00111010"; -- :
if
(count = TIME3) then
next_state <= word_display11; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordb8; control <= "100"; state_flag
<= '0';
else next_state <= wordb8; control <= "101"; state_flag <= '0';
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end if;
--------------------------- write out
when word_display11 =>
sf_d_temp <= "10001001"; -- Set Address hx0B
if
(count = TIME3) then
next_state <= word_display12; control <= "001";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display11; control <= "000";
state_flag <= '0';
else next_state <= word_display11; control <= "001"; state_flag
<= '0';
end if;
when word_display12 => -- Display dollar of count_out
case coinin is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110000"; --0
when "0010" => sf_d_temp <= "00110000"; --0
when "0011" => sf_d_temp <= "00110000"; --0
when "0100" => sf_d_temp <= "00110000"; --0
when "0101" => sf_d_temp <= "00110000"; --0
when "0110" => sf_d_temp <= "00110000"; --0
when "0111" => sf_d_temp <= "00110000"; --0
when "1000" => sf_d_temp <= "00110000"; --0
when "1001" => sf_d_temp <= "00110000"; --0
when "1010" => sf_d_temp <= "00110001"; --1
when others => sf_d_temp <= "00110000"; --0
end case;
if
(count = TIME3) then
next_state <= word_display14; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display12; control <= "100";
state_flag <= '0';
else next_state <= word_display12; control <= "101"; state_flag
<= '0';
end if;
when word_display14 => -- Display tenth of count_out
case coinin is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
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when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when "1010" => sf_d_temp <= "00110000"; --0
when others => sf_d_temp <= "00101101"; --[-]
end case;
if
(count = TIME3) then
next_state <= word_display15; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display14; control <= "100";
state_flag <= '0';
else next_state <= word_display14; control <= "101"; state_flag
<= '0';
end if;
when word_display15 =>
sf_d_temp <= "00110000"; -- 0
-- last digit of count_out
if
(count = TIME3) then
next_state <= word_display16; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display15; control <= "100";
state_flag <= '0';
else next_state <= word_display15; control <= "101"; state_flag
<= '0';
end if;
when word_display16 =>
sf_d_temp <= "11000111"; -- Set Address hx47
if
(count = TIME3) then
next_state <= word_display17; control <= "001";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display16; control <= "000";
state_flag <= '0';
else next_state <= word_display16; control <= "001"; state_flag
<= '0';
end if;
when word_display17 => -- Display hundredths of second digit
case change is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
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Logic Circuit Design For A Vending Machine
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Stud ID:E0706681
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when "1010" => sf_d_temp <= "00110000"; --0
when others => sf_d_temp <= "00101101"; --[-]
end case;
if
(count = TIME3) then
next_state <= word_display18; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display17; control <= "100";
state_flag <= '0';
else
next_state <= word_display17; control <= "101"; state_flag
<= '0';
end if;
when word_display18 =>
sf_d_temp <= "00110000"; -- 0
if
(count = TIME3) then
next_state <= word_display19; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display18; control <= "100";
state_flag <= '0';
else
next_state <= word_display18; control <= "101"; state_flag
<= '0';
end if;
when word_display19 =>
sf_d_temp <= "11001010"; -- Set Address hx47
if
(count = TIME3) then
next_state <= word_display20; control <= "001";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display19; control <= "000";
state_flag <= '0';
else
next_state <= word_display19; control <= "001"; state_flag
<= '0';
end if;
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Logic Circuit Design For A Vending Machine
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when word_display20 =>
sf_d_temp <= "01010000"; -- P
if
(count = TIME3) then
next_state <= word_display21; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display20; control <= "100";
state_flag <= '0';
else
next_state <= word_display20; control <= "101"; state_flag
<= '0';
end if;
when word_display21 => -- Display product selected
case productselect is
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0100" => sf_d_temp <= "00110011"; --3
when "1000" => sf_d_temp <= "00110100"; --4
when others => sf_d_temp <= "00101101"; --[-]
end case;
if
(count = TIME3) then
next_state <= word_display22; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display21; control <= "100";
state_flag <= '0';
else
next_state <= word_display21; control <= "101"; state_flag
<= '0';
end if;
when word_display22 => -- Display dollar of totalrev
case totalrev(7 downto 4) is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when "1010" => sf_d_temp <= "00110000"; --0
when others => sf_d_temp <= "00101101"; --[-]
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end case;
if
(count = TIME3) then
--if requirecoins = '1' then
-next_state <= init6; control <= "001"; state_flag <=
'1';
--else
next_state <= word_display23; control <= "101";
state_flag <= '1';
--end if;
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display22; control <= "100";
state_flag <= '0';
else
next_state <= word_display22; control <= "101"; state_flag
<= '0';
end if;
when word_display23 => -- Display tens of totalrev
case totalrev(3 downto 0) is
when "0000" => sf_d_temp <= "00110000"; --0
when "0001" => sf_d_temp <= "00110001"; --1
when "0010" => sf_d_temp <= "00110010"; --2
when "0011" => sf_d_temp <= "00110011"; --3
when "0100" => sf_d_temp <= "00110100"; --4
when "0101" => sf_d_temp <= "00110101"; --5
when "0110" => sf_d_temp <= "00110110"; --6
when "0111" => sf_d_temp <= "00110111"; --7
when "1000" => sf_d_temp <= "00111000"; --8
when "1001" => sf_d_temp <= "00111001"; --9
when "1010" => sf_d_temp <= "00110000"; --0
when others => sf_d_temp <= "00101101"; --[-]
end case;
if
(count = TIME3) then
next_state <= word_display11; control <= "101";
state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_display23; control <= "100";
state_flag <= '0';
else next_state <= word_display23; control <= "101"; state_flag
<= '0';
end if;
when donestate =>
control <= "100";
sf_d_temp <= "00000000";
if
(count = TIME3) then
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Logic Circuit Design For A Vending Machine
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if tmpcount = 5 then
next_state <= init6; control <= "001"; state_flag <= '1';
tmpcount <= 0;
else
next_state <= wordc1; control <= "001"; state_flag <= '1';
else
end if;
tmpcount <= tmpcount + 1;
end if;
next_state <= donestate; state_flag <= '0';
end case;
end process run;
timing : process (rst, clk, count) is
begin
if
(rising_edge(clk)) then
sf_d <= sf_d_temp;
count <= count_temp;
if (rst = '1') then
state <= waiting;
count_temp <= 0;
elsif (state_flag = '1') then
state <= next_state;
count_temp <= 0;
else
state <= next_state;
count_temp <= count_temp + 1;
end if;
end if;
end process timing;
end lcd_control_arch;
===============================================================
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REFERENCE
[1] Inventors, “History of Vending Machine”
http://inventors.about.com/od/uvstartinventions/a/vending.htm
[2] radio-electronics, “FPGA tutorial”
http://www.radio-electronics.com/info/data/semicond/fpga/fpga.php
[3] Smithsonian, “Old World, High Tech”
http://www.smithsonianmag.com/science-nature/ancient_calendar.html
[4] Diagram of FPGA structure
http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html
[5] Clive Maxfield, "The Design Warrior's Guide to FPGAs” 2004
[6] Comparision Between VHDL and Verilog
http://www.angelfire.com/in/rajesh52/verilogvhdl.html
[7] Stephan Brown and Jonathan Rose, Architecture of FPGAs and CPLDs : A Tutorial,
University of Toronto, P7.
[8] Specifications Of Xilinx Spartan 3A Starter Kit,
http://www.xilinx.com/products/devkits/HW-SPAR3A-SK-UNI-G.htm
[9] Michael Barr , “How Programmable Logic Works”,
http://www.netrino.com/Embedded-Systems/How-To/Programmable-Logic
[10] XST User Manual, RAMs and ROMs HDL Coding Techniques
http://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf
[11] Spartan 3A/3AN FPGA Starter Kit Board User Guide, LCD Display
http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf
[12] Sitronix ST7066U LCD Display Data sheet/User Manual
[13] Digilent Inc, PmodLED schematic,
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,511&Prod=PMODLED
[14] John J. Smith, LEDs For Dummies,
http://www.techshire.com/freebies/LED4dummies.html
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Logic Circuit Design For A Vending Machine
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[15] Spartan-3 Generation Configuration User Guide , UG332 (v1.6) October 26, 2009
www.xilinx.com/support/documentation/user_guides/ug332.pdf
[16] Wikipedia, Field-programmable gate array
http://en.wikipedia.org/wiki/Field-programmable_gate_array
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