Silicon Imaging
SI-1300 MegaCamera
1.3 Million Pixel Progressive Scan Digital Camera
Revision 1.4
July 9, 2004
1.3 Million Pixels
1280 x 1024 Image Sensor
5.2 um Square Pixel
½ Optical format
Rolling Shutter
½ & ¼ Image Subsampling
20~80MHz Mhz Clock rates(- H version)
10 Bit Digital Sampling
Auto Black Level Correction
64dB Dynamic Range
CL High-Speed Interface
**** Company Confidential ****
 Silicon Imaging , Inc. 2004
Page 1 of 32
Company Confidential
MegaCamera™ SI-1300M & RGB
Silicon Imaging Inc.
1.3 Megapixel, 10-Bit, 40/80MHz
Progressive Scan Digital Camera
INTRODUCTION
Silicon Imaging is proud to continue its innovation in high-resolution
color vision camera. Driven by the growing demand for consumer Digital
Still Cameras, CMOS sensors are continuing to break technical barriers
and surpass the performance characteristics of CCD’s in many photonic,
imaging and consumer applications. By utilizing a single highly integrated
CMOS device, which incorporates Megapixel sensing areas, timing
generation, signal processing and high bandwidth outputs, Silicon Imaging
has developed a very compact, low-power, ultra high speed Megapixel
digital camera system.
1280 x 1024 Megapixel - Ultra Resolution
The SI-1300 is an all-digital CMOS camera that delivers 1.3 Million pixels
of resolution and is capable of running at over 40 frames/second at its full
1280 x 1024 resolution. The entire package is only 45 x 52 x 50mm (33 x
40mm x 22mm in PCB) and is small enough to placed on a robot for
semiconductor machine vision inspection or placed in an outdoor housing
for remote surveillance. It is ideal for live visualization and handheld
instrumentation.
10-Bits Sampling – Sub-Pixel Accuracy
The SI-1300 MegaCamera uses 10-Bit digitizers to sample the pixel
data. Converting the pixel data directly to digital at the sensor head
eliminates pixel-sampling jitter and enables accurate sub-pixel metrology,
image analysis and improved live video reconstruction. A programmable
clock which ranges from 20~40MHz or 80MHz (-H version) allows for
trade-offs in speed versus exposure time and lower noise.
150 FPS VGA Subsampling - Fast Preview
Ideal for high speed preview and focusing, the SI-1300 is capable of
generating imagery at over 100 frames per second by reducing the size of
the readout image in color subsampling mode, This entire imager is
readout by skipping pairs of pixels (4:2) to maintain color information of
neighboring bayer groups. In this way, the 640x480 accurately represents
the full size 1280x1024 image.
1000FPS or 720P Windowing
A small region of the imager can be readout at frame rates in excess of
1000fps, with speed increasing with reduced vertical and horizontal
settings. At 1280 x 720 and a 67MHz clock the output rate would be 60fps.
The window size and position can be adaptively changed on frame-byframe basis.
Automatic Black Level Correction
The SI-1300 has automatic black level calibration, which measures the
average value of 256 pixels from two dark rows of the imager for each of
the four colors. The pixels are averaged as if they were light sensitive and
passed through the appropriate color gain. This average is then digitally
filtered over many frames and compared to minimum and maximum
acceptable thresholds for automatic correction.
CameraLink Digital Interfaces (12-Bit 1-Tap)
An industry standard forum has adopted Camera Link, for low cost
connectivity and cabling of cameras and frame grabbers at very high
speeds. The SI-1300-CL utilizes the high speed CameraLink interface to
output data continuously to a frame grabber and directly into PC memory
for further processing. The single cable includes image data, vertical and
horizontal synch, LVDS Triggering and 9600 baud Serial communication.
As this camera complies with the standard, it is compatible with many
popular frame grabber and image processing hardware devices and fiberoptic extender for extended distance transmission.
 Silicon Imaging , Inc. 2004
Page 2 of 32
FEATURES
·
1280 x 1024 Resolution (1.3 Million Pixels)
·
1/2” Imaging Format , 5.2um Square Pixel
·
Rolling Shutter, Progressive scan
·
640 x 480 VGA Windowing at 150fps
·
10 Bits per Pixel, 48MHz Sampling (Nominal)
·
20 ~ 40MHz Programmable Clock (80MHz – H Version)
·
Programmable Gain, Exposure & Clocks
·
Auto Black Level Calibration
·
Monochrome & Color Bayer RGB Model
·
Custom PCB Version
·
Cameralink Interface
·
C-Mount Precision Machined Housing
Company Confidential
SI-1300 MegaCamera CameraLink Specifications
Sensor:
CameraLink Frame Grabber Control:
Optical Imaging Format
Active Pixels
Pixel Size (pitch)
Pixel Type
Aspect Ratio
Spectral Response
Peak QE
Minimum Illumination:
Responsivity
Dark Current @ 25°C
Temporal Noise
Saturation Charge
Dynamic range
Windowing (ROI)
Sub-sampling
Gain MAX
Readout Method
Black Level
Shutter
Shutter Speed / Integration
Horizontal Blanking
Minimum Row Time
Vertical Blanking
Row/Frame Time (default)
1/2” (6.83mm x 5.45mm)
1,280H x 1,024V
5.2 µm x 5.2 µm
CMOS
1:1
350 ~ 1000 nm
56% Monochrome @ 570nm
0.3 lux nominal ( SNR =1, f# = 2.8,
exposure = 100ms, daylight)
2.1 V/lux-sec
20 e-/sec
10 e40,000 e68.2 dB
Horizontal & Vertical speed increase
Full, 1/2, 1/4, 1/8
15X, min step size 0.125
Progressive Scan
Auto Black Level Calibration
Rolling Shutter and Single Frame
Variable, 1 to 16383 row times
244 Clocks/line
548 Clocks (304+ 244 Blanking)
26 Rows (15 min)
1524 clocks/row x 1050/rows = 30fps
A/D Conversion & Sampling Clock Synthesizer
A/D Conversion
Readout Rate
Vertical Resolution
Pixel Clock Frequency
Nominal 48Mhz (30fps @ 1.3MP)
20 ~ 80Mhz x 12bit format
10 Bit (CL Format = 12bit Single-Tap)
20 ~ 40 Mhz Programmable
20 ~ 80Mhz (-H option)
Serial Communication
Signaling
Asynchronous Triggers
Region-of–Interest
Programmable Modes
Gains (R,G,B,G & Global)
Setting Timing
Ext Clock Sync
RS-232 Protocol 9600bps (57.6k)
TX & RX (LVDS)
LVDS – CC1 (-CL)
TTL Trigger-In / Strobe-Out (option)
Programmable Horiz & Vertical
Exposure, Gain, Windowing, Clock
rates, Auto black, mirroring.
Individual RGB Gains
Range: 15X, MIN step size 0.125
Next top of Frame
Clock in or Clock Out (-X Option)
Power
Input Voltage
Power
Power/Trigger Connection
+5 VDC +/- 10%
2.5 Watts
Tajimi RO3-PB3M 3Pin (-CL)
Tajimi RO3-PB5M 5Pin (-X)
Mechanical
Lens Mount
Enclosure Size
Weight
Camera Mount
Cable Connector
C-Mount, 7mm Back focus Adj.
45mm W x 52mm H x 50mm L
12 oz.
¼” x 20 standard tripod mount
Cameralink MDR-26
Spectral Response Curve (Monochrome)
Digital Video Output
Readout Format
Readout Rate
CL-12 Bit (Duplicated on Ports A, B)
20~ 80MB/sec (8-bit Mode)
40~160MB/sec (12-bit Unpacked)
Frame Rate
1280 x 1024
1280 x 720
640 x 480
320 x 240
200 x200
160 x 120
Row/Frame Time (default)
48MHz
60MHz
30
43
110
334
407
654
38
54
137
417
509
817
1524 clocks/row x 1050/rows = 30fps
ORDERING INFORMATION
SI-1300-[RGB or M]-S
1.3 MP Digital Camera, 2M Cable, PCI Frame Grabber & Win NT/2K/XP Imaging Software System
SI-1300-[RGB or M]
1.3 MP Digital Camera (RGB for Color, M for Monochrome)
- CL
-X
-H
Cameralink (-CL) or High-Speed CL 80MHz (–H), Add external clock sync (-X)
FG-1300-xx
Frame Grabber PCI (32 = 32Bit PCI -64 = 64bit PCI)
CL-2M, 5M, 10M
2 / 5 / 10 Meter Digital Camera Cable
PC-3
Power Cable (3M)
 Silicon Imaging , Inc. 2004
Page 3 of 32
Company Confidential
SI-1300 Camera Architecture Overview
The MegaCamera SI-1300 consists of 6 major component sections, which are built on two circuit boards.
Camera Block Diagram
Register
Programming
uP
Control
Digital
Logic
Camaerlink
PLL & Timing
Generator
Strobe Out
1280 x 1024
Sensor
&
A/D
Converter
Trigger In
DATA (10)
FVAL
LVAL
CLOCK
Trigger
Controller
5VDC
Power
Supply
MDR-26
1.) 1.3 Megapixel Sensor
2.) Digital Clock Synthesizer
3.) Digital Control Logic
4.) Microprocessor
5.) CL Interface
6.) Power Regulation
7.) Trigger & Strobe Controls
1.)
1.3 Megapixel CMOS Image Sensor (1280 x 1024)
The MegaCamera SI-1300 utilizes a proprietary 1.3 Million pixel high-speed CMOS image sensor. Each pixel is
5.2um Square, ideal for image processing, and the entire array fits the 1/2” format for flexible optic choices. This
reduction in process geometry allows for both an increase in transistors and fill factor without compromising
performance, plus offers more advanced readout controls, greater speeds and lower power dissipation.
This new sensor technology offers a more responsive pixel design with added circuitry for increased dynamic
range, greater sensitivity, decreased fixed pattern noise and low dark current for long exposure applications.
Unlike CCD, which leak charge to adjacent pixels when the registers overflows (blooms), the SI-1300 provides
inherent anti-blooming protection in each pixel, so that there is no blooming.
 Silicon Imaging , Inc. 2004
Page 4 of 32
Company Confidential
The array has 1280 pixels on a line and 1024 rows, which result in a 4:3 aspect ratio. The sensor array design is
based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel readout scheme (aka. Rolling Shutter Method)
Analog Gain Amplifier & Offset
The imager signal path consists of two stages, a programmable gain stage and a programmable analog offset
stage. The gain settings can be independently adjusted for the colors Green1, Blue, Red, and Green2 and are
programmed through registers. A total programmable gain of 15 is available. The programmable analog offset
stage corrects for analog offset that might be present in the analog signal. The analog offset settings can be
independently adjusted for each color (R/G1/G2/B).
Automatic Black Level Compensation
The automatic black level calibration measures the average value of 256 pixels from two dark rows of the imager
for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the
appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered
average is compared to minimum and a maximum acceptable level. If the average is lower than the minimum
acceptable level, the offset correction voltage for that color is increased. If it is above the maximum level, the level
is decreased. The upper threshold is automatically adjusted upwards whenever an upward shift in the black level
from below the minimum results in a new black level above the maximum. This prevents black level oscillation
from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting
(out of all four colors), according to Register settings. This prevents clipping of the black level. After changes to
the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid
sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the
sensor registers.
2.)
10-Bit Digital Sampling System
A 10-Bit Analog-to-digital (A/D) converter samples each pixel value and quantizes it into 1024 levels inside the
sensor. Pixel clock sampling ensures precise measurement of the photonic charge without the jitter and sampling
uncertainty associated with traditional analog video systems, such as RS-170 and CCIR. This produces images
which can deliver improved photometry accuracy and sub-pixel metrology. The use of 10-bit converters versus
traditional 8-bit systems further enhances the image dynamic range. The combination of 10-bit vertical resolution
and pixel clock sampling provide precise sub-pixel measurement accuracy (ex. 1/10 pixel).
 Silicon Imaging , Inc. 2004
Page 5 of 32
Company Confidential
3.)
Digital Clock Synthesizer
A wide range a master clock frequencies (eg. 20 to 80MHz) can by precisely generated using the Digital Clock
Synthesizer. The Frame Grabber, which is used with the camera, must be capable of receiving 12bit at 40 or up
to 80Mhz to achieve the highest data rates. Without any byte packing of the 12-bit word the data rate would be
160MHz (2pixel x 2bytes/pixel x 80MHz). In standard 32Bit/33MHz PCI computers the maximum data rate
directly to host memory is usually below 120Mbytes/sec (from 132MB/sec bus) without system interrupts.
However, 100MB/sec is more reasonable rate to achieve with other system devices operating (eg. display, clock,
mouse etc.). Under these condition the 12-bit data can be mapped to 8-bits/pixel to reduce the bus traffic or the
clock rate can be reduced to and still maintain 12bits/pixel. The frequency of the clock synthesizer can be set by
serial command. A table with associated clock frequency is found in the serial programming section of the
manual. Due to minimum frequency restriction on the digital transmission link, the pixel clock frequency cannot
be lower than 20Mhz.
4.)
Embedded Microprocessor
A microprocessor in the camera provides the control interface between the PC and the functional block in the
camera (Sensor, Clock Synthesizer, Register Memory, Channel Link Interface & Serial port (CameraLink). The
Microprocessor receives commands thru the LVDS level serial port and issues commands to the other devices. It
also can store preset values for camera setting, which can be recalled with single ASCII character commands.
Several digital I/O or analog sampling signals are available on the processor from PCB header points for custom
OEM applications.
5.)
12-Bit CameraLink Interface (Base Configuration)
Camera Link is a new digital transmission method designed by imaging component manufacturers as an easy
and standard way to connect digital cameras to frame grabbers. The Camera Link specification includes greater
than 1.2Gb/sec data transmission as well as camera control and asynchronous serial communications all on a
single cable with high-density 26pin connector. Only two connections are required to quickly interface your digital
camera to a multitude of frame grabbers. This standardization will ultimately reduce cost of high performance
digital cameras through open market competition and a simple migration path to faster and higher resolution
systems.
As a standard that has been defined by industry members, Camera Link provides the following benefits:

Standard Interface: Every Camera Link product will use the same cable and signaling. Cameras and
frame grabbers can easily be interchanged using the same cable.

Simple Connection: Only two connections will be required to interface a camera and frame grabber:
Power and Camera Link.

Lower Cost: Because Camera Link is an industry-wide standard, consumers will be able to take
advantage of lower cable prices.

Smaller connectors & cables: The technology used in Camera Link reduces the number of wires
required to transmit data over traditional LVDS or RS-422 parallel interfaces, allowing for smaller cables.
Smaller cables are more robust and less prone to breakage.

Higher data rates: The technology used in Camera Link has a maximum data rate of 2.3GB/s, for use in
the most demanding high definition, high frame rate and line scan.
 Silicon Imaging , Inc. 2004
Page 6 of 32
Company Confidential
CameraLink Camera Signal
This section provides definitions for the signals used in the Camera Link interface. The standard Camera Link
cable uses a MDR 26-pin connector (3M Part# 10226-6212VC)provides the following signaling:

Video Data (4 Pairs using 28:4 Mux, 24 Video, 4 Control)

Camera control signals (1 Pair)

Serial communication (2 Pairs)
Video Data
The 24 bit image data (2 words x 12 bit) and 4 control bits are transmitted over only 4 differential pairs using a
28:4 multiplexer (National Semiconductor DS90CR285 Channel Link device). The Four enable signals are
defined as:
• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.
• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.
• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.
• Spare— A spare has been defined for future use.
All four enables are provided on the camera, via the Channel Link chip. The unused data bits are tied to a known
value by the camera. For more information on image data bit allocations, see page 11, CameraLink Base
Configuration Bit Assignment Configuration.
Communication
Two LVDS pairs have been allocated for asynchronous serial communication to and from the camera and frame
grabber. Cameras and frame grabbers should support at least 9600 baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface operates at 9600 baud, one start bit, one stop bit, no parity, and no handshaking. For
applications requiring high serial throughput, such as real time windowing update at over 200FPS, the camera
can support a serial link mode at 57kbs (not specified in CameraLink spec). The frame grabber serial
communication must be set to match this speed.
 Silicon Imaging , Inc. 2004
Page 7 of 32
Company Confidential
Camera Control Signals & Power
Four LVDS pairs are reserved for general-purpose camera control. They are defined as camera inputs and frame
grabber outputs. Camera manufacturers can define these signals to meet their needs for a particular product. The
signals are:
• Camera Control 1 (CC1) - Used to do triggered image capture
• Camera Control 2 (CC2) for external master clock (optional)
Tajimi RO3-PB3M – POWER CABLE
5VDC Power Supplies
 Silicon Imaging , Inc. 2004
Page 8 of 32
Company Confidential
3-PIN POWER & TRIGGER INPUT WIRING
PhotoEye Trigger and Power Connection
 Silicon Imaging , Inc. 2004
Page 9 of 32
Company Confidential
Power-On Communication & Presets
Initial State
When the power is first applied to the camera the camera will load its default (Preset #1) settings and will be
generating live video and a serial status message. Preset #1 can be overwritten thru programming commands.
Once Preset#1 is overwritten it will be the new power-on default setting.
If the Frame Grabber supports a serial terminal mode the following menu will appear:
100: Booted
108: CameraLink SI1300 3.12.08
120:C2010610 Sensor tag
190:66633035 Configuration code
's' - status
Returns the firmware version, clock configuration word, Sensor Tag, and FPGA Configuration code. Camera
output example:
108: CameraLink SI1300 3.06.08
110:306882 Clock
120:C2010610 Sensor tag
190:66633035 Configuration code
Default Settings
When first turned on, the SI1300 will be in the default mode, which will be 24 fps Full Frame Readout at 40MHz
master clock. See serial programming section for details on changing formats.
Full Resolution, Rolling Shutter, Single-slope, 40MHz
Resolution =
Clock =
Frame Rate =
Integration =
Global Gain =
 Silicon Imaging , Inc. 2004
1280 x 1024
40MHz
24 FPS
1022 Rows
2.0
Page 10 of 32
Company Confidential
Serial Communication & Protocol
The SI1300 is capable of mode programming through its serial interface. Commands are sent from the
CameraLink frame grabber to the camera. The commands are processed by the micro controller and
communicated to various devices in the camera including the sensor, digital clock synthesizer and the Flash
memory inside the microprocessor itself.
The communication uses an asynchronous serial format, similar to RS232, but is transferred to the camera using
LVDS as part of the CameraLink interface specification.
Format:
Rate:
Data Bits:
Parity:
Interface:
Asynchronous, ASCII
9600
8 + 2 Stop bits
No Parity
Serial LVDS (thru CameraLink)
The baud rate is set to 9600 and 8 data bits with no parity. This is the format set by the CameraLink standard.
However, faster rates can be set by the factory and coordination with the Frame Grabber supplier.
Serial Commands
There are two types of commands Single character and Register String (multiple characters followed by Carriage
Return). Once the camera receives the string ending with a <CR> it will respond. For each command, there is a
corresponding action and response from the camera.
Single Character commands
“s”
Camera status including firmware version, clock configuration word, sensor tag and
CPLD configuration codes.
“f”
Arm single frame capture. Trigger frame capture & readout if already armed.
“h”
Change to high-speed serial mode for operation at 57.6kbaud
*** Note: All commands must terminate with a <cr> (carriage return).
Register String commands
Each command may be entered through the Terminal communication mode from the frame grabber software. All
ASCII characters sent should be lower case and no spaces between characters. The string is terminated with a
carriage return <cr>. Hex numbers are sent as ASCII characters: 0Fh is sent as “0F” character. There are no
spaces between characters being sent in strings. These are multiple character string commands with a common
format.
 Silicon Imaging , Inc. 2004
Page 11 of 32
Company Confidential
Register String Commands
Command
Description
Parameters
Response
lc xxxxxx <cr>
Load Clock Register
(See clock table)
xxxxxx = 6 hex values from table
114: Clock updated
ly rr xxx <cr>
Load Sensor Registers
Loads registers 00 to ff with 16bit
values, which are sent as 4 ascii
characters representing hex.
rr = register number 00~ff
xxx = x0000~xFFFF
104: Sensor updated
le x <cr>
Load EEPROM preset value
***overwrites factory values
Load Bootup Default
x=1
le1 = stores preset #1
x = 0 or 1
ld1 = boots camera with preset #1
AA = slot (00 ~FF
YY = Memory (00-10)
XX = 14 bit value (00~ F
The first two bits (MSBs) of the first
byte and of every odd byte are not
stored.
106: Preset updated
ld x <cr>
'luAA[YYXXx16]'
Load upper/user memory
7k-Bytes. Configured in 256
slots. Each slot has 16 memory
locations of14bits for
lr xxxx
Read back user/upper memory
ln xxxx
Load new firmware
xxxx = password to enable
firmware upgrade (contact factory)
*** Note: All commands must terminate with a <cr> (carriage return). Hex characters are lower case, no spaces.
Load Sensor Command Format
The following registers for SI-1300 control the sensor readout, timing and signal output levels. These are
programmed thorough ‘ly’ register commands. The register number is represented by 2 characters. All sensor
registers are 16 bits in length and are represented by 4 characters. The ASCII command format is:
ly rr xxxx <cr> rr = register number
xxxx = values 0000 to ffff
The ly stands for load sensor array and must be sent as lower case. The “rr” is the register to be changed. The
“xxxx”, “represents four HEX values that are to be loaded into each register. The sequence must end with a
carriage return <cr>.
The following is an example of a 10-character command string
l y 0 1 0 0 6 4 <cr>
This command will load the WIDTH register “01” with hex “0064”. The resulting value loaded into the Width
register is “0064” or 101 in decimal. The actual resulting width in the image is width-, which equals 100.
 Silicon Imaging , Inc. 2004
Page 12 of 32
Company Confidential
SI-1300 Sensor Register Programming
0x00
0x01
Chip Version
Row Start
0x8421
0x8431
0x000C
(12)
0x0014
(20)
0x02
Column Start
0x03
Window Height
0x03FF
(1023)
0x04
Window Width
0x04FF
(1279)
0x05
Horizontal Blanking
0x0013
(19)
0x06
Vertical Blanking
0x0019
(25)
0x09
Exposure
0x0419
(1049)
0x0C
Shutter Delay
(Short Exposure)
0x0000
(0)
0x1E
Subsampling
& Snapshot Mode
0x80xx
(x8000)
0x20
Subsampling 2
& Scan Reversal
0x11xx
(0x1104)
0x2B
Green1 Gain
0x0008 (8)
1x gain.
0x2C
Blue Gain
0x0008 (8)
1x gain.
0x2D
Red Gain
0x0008 (8)
1x gain.
0x2E
Green2 Gain
0x0008 (8)
1x gain.
0x35
Global Gain
 Silicon Imaging , Inc. 2004
0x0008 (8)
1x gain.
(First row to be read out + 12)
(First column to be read out + 14)
Register value must be an even number.
Window height (number of rows - 1)
Min = 0x0002.
Window width (number of columns - 1)
Register value must be an odd number.
Min = 0x0003
Number of extra row blanking clocks + 19
Row Blanking = 244 clocks + (Regx05 –19)
Number of extra rows added into the vertical blanking
period. Typically used to slow down frame rate and allow
time for register updates between images.
Number of rows of integration
Number of master clocks times four that the sensor waits
before asserting the reset for a given row.
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
0 (do not change)
0 (do not change)
Column Skip 4—default is 0 (disable), 1 = enable.
Row Skip 4—default is 0 (disable), 1 = enable.
Column Skip 8—default is 0 (disable), 1 = enable.
Row Skip 8—default is 0 (disable), 1 = enable.
0 (do not change).
0 (do not change).
Snapshot Mode—default is 0 (continuous mode).1 = enable
Snaphsot TRIGGER can come from CC-1 or from serial
interface command.
No bad frames: 0 (default) = only good frames, 1 = all frames
0 (do not change)
1 (do not change)
Column skip2: 0= normal readout (default), 1= skip by 2
Row skip2:
0 = normal readout (default), 1= skip by 2
0 (do not change)
0 (do not change)
Flip Row: 0 = normal, 1= Scan reversal
1 (do not change)
Gain
Increments
1.000 to 4.000
0.125
4.25 to 8.00
0.25
9.0 to 15.0
1.0
Settings
0x08 to 0x20
0x51 to 0x60
0x61 to 0x67
This register can be used to set all four gains at once.
When read, it will return the value stored in Reg0x2B.
Page 13 of 32
Company Confidential
Digital Clock Synthesizer Programming
The SI-1300 has a Digital Clock Synthesizer capable of generating a range of frequencies from 20MHz to 60 or
80MHz. The pixel data output rate is the same as the sampling clock rate. The clock frequency is set by the “lc”
Register String command. A range of preset frequencies are listed below:
Command
Clock Rate
MHz
lc306886
lc30b689
lc37cb8f
lc35d40b
lc306882
lc35e709
lc356e03
lc34b689
lc34b688
lc36cb8f
lc344081
20
25
30
35
40
45
48
50
55
60
67
SI-1300 Frame Rate
1280x1024 1280x720
13
18
16
22
19
27
22
31
25
36
28
40
32
45
35
49
38
53
41
58
60
42
640x480
46
57
68
80
91
103
114
125
137
148
153
320x240
143
178
214
249
285
321
356
392
428
463
478
200 x200
169
211
253
296
338
380
422
465
507
549
566
160 x 120
268
335
403
470
537
604
671
738
805
872
899
100 x100
315
393
472
551
629
708
787
865
944
1023
1054
Note: The factory can generate the command to achieve a targeted clock rate.
Sample Command:
The clock frequency is programmed by the “lc” command with by 6 HEX characters. An example is:
“lc36cb8f <cr>” This will request a clock value of 60MHz.
The response to a command will be:
114: Clock updated
There are multiple setting to achieve each frequency. Some might be better than others for a particular
application.
Frame Rate Calculation
To calculate the frame rate for any clock rate the equation is estimated by:
(
clock rate(Hz)
)
=
( # of columns + 244) * ( # of rows +16) -180
Example:
# Frames Per Second (fps)
What is the frame rate, at 48MHz clock rate for an image size of 1280 x 1024?
48 x 106
( 1280 + 244) * (1024+16) -180
= 30 Frames Per Second (fps)
*** Subsampling frame rates are based on the resulting size of the sub-sampled image or window.
*** Minimum # of columns that are internally clocked is 304, even if the image window is smaller. Therefore the
minimum row time = 304 + 244 = 548 clocks.
 Silicon Imaging , Inc. 2004
Page 14 of 32
Company Confidential
Frame Timing
PARAMETER
NAME
EQUATION (MASTER CLOCK)
TIMING (48MHz)
A
Active Data Time
(Reg0x04 + 1)
P1
Frame Start Blanking
242 Clocks
P2
Frame End Blanking
(2 + Reg0x05 - 19)
(MIN Reg0x05 value = 19)
1,280 pixel clocks
= 26.7µs
242 pixel clocks
= 5.04µs
2 pixel clocks
= 0.042µs
Q= P 1+ P 2
Horizontal Blanking
244 + (Reg0x05 - 19)
(MIN Reg0x05 value = 19)
244 pixel clocks
= 5.08µs
Row_Time
Row Time
A+Q=
((Reg0x04 + 1) + (244 + Reg0x05 - 19))
Min Row_time = 244 + 304 = 548 clocks/row
1,524 pixel clocks
= 31.75µs
V
Vertical Blanking
(Reg0x06 + 1) x (A + Q)
(MIN Reg0x06 value = 15 rows, Default =25)
39,624 pixel clocks
= 825.5µs
N rows x (A + Q)
Frame Valid Time
(Reg0x03 + 1) x (Row_Time)
1,560,576 pixel clocks
= 32.51ms
F
Total Frame Time
(Reg0x03 + 1 + Reg0x06 + 1) x Row_Time
1,600,200 pixel clocks
= 33.34ms / 30fps
F’
Total Frame Time
(long integration time)
(Reg0x09 + 1) x Row_Time
1,600,200 pixel clocks
= 33.34ms / 30fps
Note: Typically, the value of Expsoure (Reg0x09) is limited to the number of rows per frame (which includes
vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased
beyond the total number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as
needed, and therby reduce the effective frame rates.
Frame Timing Registers
Register
Name
Default
0x03
Window Height
0x03FF
(1023)
0x04
Window Width
0x04FF
(1279)
0x05
Horizontal Blanking
0x0013
(19)
0x06
Vertical Blanking
0x0019
(25)
 Silicon Imaging , Inc. 2004
Description
Window height (number of rows - 1)
Min = 0x0002.
Window width (number of columns - 1)
Register value must be an odd number.
Min = 0x0003
Number of extra row blanking clocks + 19
Row Blanking = 244 clocks + (Regx05 –19)
Number of extra rows added into the vertical blanking
period. Typically used to slow down frame rate and allow
time for register updates between images.
Page 15 of 32
Company Confidential
Exposure Time (Reg09)
The exposure time is set by adjusting the number of row times in the exposure register (Reg09), up to the number
of rows in the frame. For longer exposures, the frame time can be extended beyond the normal 1024 rows by
increasing vertical blanking (Reg05).
Exposure_Time = (Row_Time x Reg09) – 180 clocks
Reg09 = Rows of integration
Row_Time
= Width + 244 + Horizontal Blanking
= (Reg04 + 1) + 244 + (Reg05 - 19)
Reg04 = Width-1
Reg05 = Vertical Blanking (min =19)
Note: Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking
rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total
number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as needed, and
therby reduce the effective frame rates.
Exposure_Time in Subsampling & Anti-Flicker
Row skip mode should have no effect on the integration time.
Column skip mode changes the effective value of Column Size (Reg0x04) as follows:
Column Skip 2 =>
Column Skip 4 =>
Column Skip 8 =>
Reg04eff = (int(Regx04 / 4) x 2) + 1
Reg04eff = (int(Regx04 / 8) x 2) + 1
Reg04eff = (int(Regx04 / 16) x 2) + 1
where the int() function truncates to the next lowest integer. R4eff in the equation for Row_Time instead of Reg04
The Exposure_Time should be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this
means Exposure_Time must be a multiple of 1/120 of a second. Under 50Hz flicker, Exposure_Time must be a
multiple of 1/100 of a second.
Short Exposure ( Less than 1 Row Time)
To set the SI1300 to an integration time less than 1 row, the shutter width register 0x09 must first be set to 1.
Shorter integration times are controlled by the shutter delay register 0x0C. The following formula shows how to
calculate the of shutter delay for a desired sub-row integration time:
fclk = 48MHz
Win_width = 1279
Win_height = 1023
Desired integration time, Tint = 15us ( equivalent to 0.472 x row_time )
shutter _ width  win _ width  1  horiz _ blank  244  Tint  f clk  180
4
6
1  1279  1  0  244  15  10  48  106  180
shutter _ delay 
 156
4
shutter _ delay 
 Silicon Imaging , Inc. 2004
Page 16 of 32
Company Confidential
Below is a table describing the maximum and minimum limitations of shutter width register exposure control for
various pixel readout frequency and frame rates:
Exposure Time Table
Shutter Width
Reg 0x09 [rows]
Exposure Time [ms]
48MHz pixel clock
Exposure time [ms]
24 MHz pixel clock
Exposure Time [ms]
12 MHz pixel clock
1 (minimum)
0.0280
0.056
0.112
2
0.0598
0.120
0.239
16
0.504
1.01
2.02
64
2.03
4.06
8.12
512
16.25
32.5
65.0
1049 (default)
33.3
66.6
133
2098
66.6
133
266
4196
133
266
533
16383 (maximum)
520
1040
2080
The table below shows examples of fine exposure control for short exposure settings:
Fine Exposure Control Table
Shutter Width
Reg 0x09
[rows]
Shutter Delay
Reg0x0C
[pixel clocks]
Exposure Time [us]
48MHz
pixel clock
1 (minimum)
0 (minimum)
28.00
1
1
27.92
1
2
27.83
1
3
27.67
---
---
---
---
---
---
1
242
7.833
1
243 (maximum)
7.750 (minimum exp)
The fine exposure table shows that the minimum integration time possible using the SI1300 with default
1280x1024 readout at 48MHz is 7.75us.
 Silicon Imaging , Inc. 2004
Page 17 of 32
Company Confidential
Window Programming – Image Size & Position
To place a 640 x 480 window in the middle of the sensor,
ly 01 xxxx
ly 02 xxxx
ly 03 xxxx
ly 04 xxxx
Set BEGIN_ROW to 256+12
Set BEGIN_COLUMN 320+14
Set HEIGHT to (480 – 1) = 479
Set WIDTH to (640– 1) = 639
(0x020Ch)
(0x014eh)
(0x01DFh)
(0x027Fh)
As shown in the adjacent picture, registers 3 and 4 set the size of
the display window. Register 2 sets the column start location and
registers 1 and 1 set the row start location. Column and Row end
do not need to be entered as they are the sum of the start and
size of the window.
Note: other custom commands can be used to move the window
at high speeds – please consult the factory.
Register
Name
Default
0x000C
(12)
(First row to be read out + 12)
Row Start
0x02
Column Start
0x0014
(20)
(First column to be read out + 14)
Register value must be an even number.
0x03
Window Height
0x03FF
(1023)
Window height (number of rows - 1)
Min = 0x0002.
0x04
Window Width
0x04FF
(1279)
Window width (number of columns - 1)
Register value must be an odd number.
Min = 0x0003
0x01
Description
The following table shows frame rates of typical image formats and pixel clock frequencies. This table assumes
that the shutter width register 0x09 is set to the number of rows in the image format + 25 rows for vertical
blanking. Note that it is possible to fine tune the desired frame rate by adjusting the horizontal blank register
0x05, vertical blank register 0x06, and the shutter delay register 0x0C:
Maximum Frame Rates For Typical Pixel Clocks and Image Output Formats
Pixel Clock
[MHz]
1280x1024
(SXGA)
[fps]
640x480
(VGA)
[fps]
352x288
(CIF)
[fps]
320x240
(QVGA)
[fps]
48
30
107
257
320
24
15
53.7
128
160
 Silicon Imaging , Inc. 2004
Page 18 of 32
Company Confidential
SubSampling / View-finder Modes
The SI1300 has several view-finder modes that skip rows and columns of data to allow readout of smaller
amounts of image data without sacrificing scene content. The following view-finder modes are available:
Mode
Default (no skip)
Skip 2 Row
Skip 4 Rows
Skip 8 Rows
Default
(no skip)
1280x1024
1280x512
1280x256
1280x128
Skip 2
Columns
640x1024
640x512
640x256
640x128
Skip 4
Columns
320x1024
320x512
320x256
320x128
Skip 8
Columns
160x1024
160x512
160x256
160x128
Note: Imager frame rate is increased for view-finder modes. Horizontal and vertical blank registers may be
increased to adjust the frame rate to desired rate.
Example: Register settings for 320x256 preview mode at 30fps
1. Set READ MODE 1 register 0x1E (bit 2 and 3) = ‘1’ to enable column skip 4 and row skip 4 readout
mode.
2. To keep frame rate at 30 fps (48MHz pixel clock), horizontal blank and vertical blank registers must be
increased to ‘fill in’ pixel clocks. This may be achieved by setting register 0x05 (horizontal blank) = 969
and register 0x06 (vertical blank) = 793
3. See diagram below for readout timing details for this example
320x256 Skip 4 View Finder Mode
Row 1
Row 2
LVAL
Increase Horizontal and Vertical Blank Time To Keep Frame
Rate Constant
LVAL is only asserted high for 320 pixels, overall line time
remains unchanged
 Silicon Imaging , Inc. 2004
Page 19 of 32
Company Confidential
GAIN CONTROL (Reg 2B, 2C, 2D, 2E, 35)
The SI1300 contains manual analog gain controls for each color channel (G1, G2, R, B). Gain values may be set
using the following registers: G1 = 0x2B [6..0], G2 = 0x2E [6..0], R = 0x2D [6..0], and B = 0x2C [6..0]. In addition,
the MI1300 contains a global gain register, 0x35 [6..0], that applies the gain value to all gain channels (G1, G2, R
,B ). When the global gain register is read it returns only the gain setting from the Green 1 channel register 0x2B.
0x2B
Green1 Gain
0x0008 (8)
1x gain.
0x2C
Blue Gain
0x0008 (8)
1x gain.
0x2D
Red Gain
0x0008 (8)
1x gain.
0x2E
Green2 Gain
0x0008 (8)
1x gain.
0x35
Global Gain
0x0008 (8)
1x gain.
Gain
1.000 to 4.000
4.25 to 8.00
9.0 to 15.0
Increments
0.125
0.25
1.0
Settings
0x08 to 0x20
0x51 to 0x60
0x61 to 0x67
Formula for gain setting:
Gain ≤8
Gain = (bit[6] + 1) x (bit[5-0] x 0.125)
Gain > 8 (bit[6] = 1 and bit[5] = 1)
Gain = 8.0 + bit[2-0]
This register can be used to set all four gains at once.
When read, it will return the value stored in Reg0x2B.
The table below shows recommended gain register settings and corresponding gain values:
Register Setting (0x2B,
0x2C, 0x2D, 0x2E, 0x35)
Decimal
Hex
8
0x08
9
0x09
10
0x0A
11
0x0B
12
0x0C
13
0X0D
14
0x0E
15
0x0F
16
0x10
17
0x11
18
0x12
19
0x13
20
0x14
21
0x15
22
0x16
23
0x17
24
0x18
25
0x19
26
0x1A
27
0x1B
28
0x1C
29
0x1D
30
0x1E
31
0x1F
 Silicon Imaging , Inc. 2004
Gain
Gain
1
1.125
1.25
1.375
1.5
1.625
1.75
1.875
2
2.125
2.25
2.375
2.5
2.625
2.75
2.875
3
3.125
3.25
3.375
3.5
3.625
3.75
3.875
Gain [dB]
0
1.0
1.9
2.8
3.5
4.2
4.9
5.5
6.0
6.5
7.0
7.5
8.0
8.4
8.8
9.2
9.5
9.9
10.2
10.6
10.9
11.2
11.5
11.8
Page 20 of 32
Register Setting (0x2B,
0x2C, 0x2D, 0x2E, 0x35)
Decimal
Hex
32
0x20
81
0x51
82
0x52
83
0x53
84
0x54
85
0x55
86
0x56
87
0x57
88
0x58
89
0x59
90
0x5A
91
0x5B
92
0x5C
93
0x5D
94
0x5E
95
0x5F
96
0x60
97
0x61
98
0x62
99
0x63
100
0x64
101
0x65
102
0x66
103
0x67
Gain
Gain
4
4.25
4.5
4.75
5
5.25
5.5
5.75
6
6.25
6.5
6.75
7
7.25
7.5
7.75
8
9
10
11
12
13
14
15
Gain [dB]
12.0
12.6
13.1
13.5
14.0
14.4
14.8
15.2
15.6
15.9
16.3
16.6
16.9
17.2
17.5
17.8
18.1
19.1
20.0
20.8
21.6
22.3
22.9
23.5
Company Confidential
Genlock Mode for Stereo Capture – ‘g’ command (-H Model)
For stereo and synchronized multi-camera applications the SI-1300-H models supports a Genlock feature.
In normal Frame Snapshot mode, an image can be captured for two cameras simultaneously by triggering the
cameras at the same time. However, this method limits the maximum frame rate to half speed as the exposure
and readout do not overlap and require two frame times per image captured. The first frame time is for Reset and
begins exposure. The second frame time for Readout and completion of exposure. The Genlock mode provides
the highest frame rate synchronization possible by allowing overlapping exposure and readout, just like
continuous ERS, while being synchronized to a triggering timebase.
Sending a ‘g’ command arms the camera for Genlock Mode. Each CC-1 trigger causes the camera to initiate
frame readout. The camera is left in an armed state, continuing exposure and can be re-triggered at anytime.
New CC-1 triggers can occur immediately after the completion of the current frame readout cycle. Note: The first
frame is improperly exposed and should not be used.
The exposure time should be set to the full frame time for consistent exposures throughout the image. However,
variable exposure times can be used if the Genlock trigger rate matches the normal Frame_Time set by image
height and Vertical Blanking.
The mode is exited by sending a ‘c’ command.
 Silicon Imaging , Inc. 2004
Page 21 of 32
Company Confidential
Response Codes
000:XXXX
Sensor Chip ID. This is sent at boot time, and also when the status
command is issued.
0XX:XXXXXX...
Sensor registers. This message gives the address and contents of a chip
register. 16 bytes of register data will be sent on each line.
100: Booted
This is the first string sent when the Camera boots. It will later be
augmented with a firmware version number.
102: Default loaded
A message sent a boot time after the sensor and clock have been
programmed.
104: Sensor updated
A response that follows the "ly..." command.
106: Preset updated
A response that follows the "le..." command.
108: CameraLink SI1300
2.12.30
Output by the ‘s’ status command.
Identifies the camera model, interface and firmware version
110: XXXXXX
Output by the ‘s’ status command. It gives the current clock setting.
Clock
114: Clock updated
A response that follows the "lc..." command.
120: XXXX
Output by the ‘s’ status command. It provides the factory serial number.
Sensor Tag
152: serial to 57.6kbaud
Response to an ‘h’ command
159: serial rate fault
A serial framing error occurred in high-speed serial mode. Camera will
return to default 9600 baud.
190: XXXX Configuration
Code
Output by the ‘s’ status command. It gives the current configuration.
501: Unrecognized
Command
The first character of the command line input is unrecognized.
503: Invalid Input
There are multiple forms of the 503 message code. They represent invalid
input other then the command specifier, such as "ly..." commands which
include to many characters of input, or not enough to fill the specified data
byte count.
Further input was given while the camera was still processing the previous
input
505: busy
601: Loaded preset #1
 Silicon Imaging , Inc. 2004
A response to “1” command. Preset #1 was loaded.
Page 22 of 32
Company Confidential
605: help menu
All of the lines of the help menu begin with code 605.
702: Single frame
This message is sent after the camera enters single frame mode, and again
after each frame is sent.
703: Leave single frame
This message is sent after the camera exits single frame mode and enters
continuous frame mode.
802: Dual Slope
This message is sent after the camera enters dual slope synchronous
shutter mode
803: Leaving Dual Slope
This message is sent after the camera exits dual slope synchronous shutter
mode and enters continuous frames normal rolling shutter mode.
Binary to Hex (ASCII) Table
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
 Silicon Imaging , Inc. 2004
Hex in ASCII
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
Page 23 of 32
Company Confidential
SI-1300
CameraLink Frame Grabber
Hardware Interface Notes
1.
Data Configuration – 12bits x Single-Tap
The 12bit data is duplicated on both A & B outputs, to simplify Frame Grabber testing and integration.
2.
LVDS Serial Interface
The standard data rate is 9600 baud. (Faster rates, up to 57kbps can be programmed).
3.
CC-1 Trigger Interface
The camera is armed for capture modes via serial command. The CC-1 trigger is used to start the snap exposure
or live video output.
4.
PCI Bandwidth
The camera can operate at 60 Million Pixels per second. In 8-bit mode, this equates to 60MB/sec a sustained
data rate. In 12-bit mode, where 2 bytes per pixel are typically used, the maximum rate is 120MB/sec and may
require the use of a 66MHz PCI system. The data rate can be adjusted thru the on-board clock synthesizer.
 Silicon Imaging , Inc. 2004
Page 24 of 32
Company Confidential
CameraLink Connection
MegaCamera to Frame Grabber Interface
26-PIN
26-PIN
CONNECTOR CONNECTOR
FROM
FRAME
CAMERA
GRABBER
SIGNAL NAME
PAIR
X0-
1-
2
25
X0+
1+
15
12
X1-
2-
3
24
X1+
2+
16
11
X2-
3-
4
23
X2+
3+
17
10
X3-
5-
6
21
X3+
5+
19
8
Xclk-
4-
5
22
Xclk+
4+
18
9
SerTC-
6-
20
7
SertTC+
6+
7
20
SerTFG-
7-
8
19
SerTFG+
7+
21
6
CC1-
8-
9
18
CC1+
8+
22
5
CC2-
9-
23
4
CC2+
9+
10
17
CC3-
10-
11
16
CC3+
10+
24
3
CC4-
11-
25
2
CC4+
11+
12
15
Gnd
Gnd
1
1
Gnd
Gnd
13
13
Gnd
Gnd
14
14
Gnd
Gnd
26
26
MDR-26 Connector
The camera uses the standard 3M MDR-26 connector specified in CameraLink specifications.
 Silicon Imaging , Inc. 2004
Page 25 of 32
Company Confidential
12-Bit CameraLink
Base Configuration Bit Assignment
CameraLink
Port Assignements
PORT/BIT
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
12-bit x 2Ch
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B8
B9
B10
B11
B0
B1
B2
B3
B4
B5
B6
B7
National
DS90CR285MTD
Signal
Name
RX-00
RX-01
RX-02
RX-03
RX-04
RX-05
RX-06
RX-07
RX-08
RX-09
RX-10
RX-11
RX-12
RX-13
RX-14
RX-15
RX-16
RX-17
RX-18
RX-19
RX-20
RX-21
RX-22
RX-23
RX-24
RX-25
RX-26
RX-27
RX-CLK
Bit
Name
DO-0
DO-1
DO-2
DO-3
DO-4
DO-5
DO-6
DO-7
DO-8
DO-9
DO-10
DO-11
DE-8
DE-9
DE-10
DE-11
DE-0
DE-1
DE-2
DE-3
DE-4
DE-5
DE-6
DE-7
DE = Even Pixels DO = Odd Pixels
The ODD and EVEN Outputs
are identical on the SI-1300.
Camera
Data Bit
DO-00
DO-01
DO-02
DO-03
DO-04
DO-07
DO-05
DO-08
DO-09
DO-10
DE-10
DE-11
D-11
DE-08
DE-09
DE-00
DE-06
DE-07
DE-01
DE-02
DE-03
DE-04
DE-05
SPARE
LVAL
FVAL
DVAL
DO-06
RX-CLK
Channel Link
Pin
27
29
30
32
33
34
35
37
38
39
41
42
43
45
46
47
49
50
51
53
54
55
1
2
3
5
6
7
26
The following are the pin numbers for the 28 signals
output from the National Semiconductor Channel
Link chip on the Frame Grabber:
 Silicon Imaging , Inc. 2004
Page 26 of 32
Company Confidential
Channel Link Interface
CameraLink Cable
CameraLink Cable Ordering
 Silicon Imaging , Inc. 2004
Page 27 of 32
Company Confidential
FRONT VIEW
REAR VIEW
SENSOR PACKAGING
 Silicon Imaging , Inc. 2004
Page 28 of 32
Company Confidential
SI-1300-CL ENCLOSURE DIMENSIONS
 Silicon Imaging , Inc. 2004
Page 29 of 32
Company Confidential
SI-1300 Spectral Response Curve
 Silicon Imaging , Inc. 2004
Page 30 of 32
Company Confidential
SI1300-RGB Cover Glass Filter Response (IRC-30)
 Silicon Imaging , Inc. 2004
Page 31 of 32
Company Confidential
Contact Information
Silicon Imaging, Inc.
www.siliconimaging.com
sales@siliconimaging.com
Ordering Information
SI-1300M-CL
SI-1300RGB-CL
SI-1300M-S
SI-1300RGB-S
-H
PS-5
PC-2
CBL-3PT
1.3 Megapixel MegaCamera, Monochrome, Cameralink Camera
1.3 Megapixel MegaCamera, Color, Cameralink Camera
1.3 Megapixel, Monochrome, Cameralink Frame Grabber, Power Supply & Cables
1.3 Megapixel, Color Cameralink Frame Grabber, Power Supply & Cables
High Speed version, 20~80MHz operation
5VDC Power Supply
Power Cable, 2-Meter
Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug
Legal Disclaimer
Silicon Imaging reserves the right to make changes to its products or to discontinue any product or service without notice, and advises
customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and
complete. No license, express or implied to any intellectual property rights is granted by this document.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY,
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SILICON IMAGING PRODUCTS ARE NOT
DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF SILICON IMAGING PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER'S RISK.
The Product described in this datasheet may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available upon request.
Copyright: Silicon Imaging, Inc., 2004
050804-Rev 1.2
 Silicon Imaging , Inc. 2004
Page 32 of 32
Company Confidential