1.1
Lab 2: Implementing a Circuit in Hardware
Purpose
In this lab you will implement a simple combinational circuit on the DE1 development board to test
and verify its operation.
Introduction
In Lab 1, you used the Block Editor to layout the circuit for an 5-bit 2-to-1 multiplexer. In this lab you
will implement this circuit onto the DE1 development board. You will test the operation of the multiplexer
in hardware and verify its operation.
1.1.1
Analysis and Synthesis
After drawing your circuit with the Block Editor, the next step is to analyze and synthesize it. During
this step, Quartus II collects all of the necessary information about your circuit, and produces a netlist for it.
A netlist is a description of all of the components used in the circuit and how these components are
connected together.
From the Quartus II menu, select Processing > Start > Start Analysis & Synthesis to synthesize the
circuit. Alternatively, you can click on the icon
in the toolbar. If there are no errors in your circuit, you
should see the message “Quartus II Analysis & Synthesis was successful” in the Message window at the
bottom. Most warnings can generally be ignored. If there are errors then they will be reported in the
Message window and highlighted in red. For some errors, you can double-click on the red error message to
see where the error is in the circuit. Go back and double check your circuit with the one shown in Error!
Reference source not found. to correct all of the errors.
1.1.2
Mapping the I/O Signals to the FPGA Pins
Since we want to implement the circuit on a FPGA, we need to assign all of the I/O signals from the
circuit to the actual pins on the FPGA. The Pin Planner is used to map each of the I/O signals from the
circuit to the pins on the Cyclone II EP2C20F484C7 chip.
From the Quartus II menu, select Assignments > Pin Planner to bring up the Pin Planner as shown in
Figure 1. Alternatively, you can click on the Pin Planner icon
on the toolbar to bring up the Pin
Planner. The actual mappings between the I/O signals and the FPGA pins are shown in the bottom half of
the Pin Planner window. The I/O signals are listed under the Node Name column, and the FPGA pin names
are listed under the Location column.
For each I/O signal name, double-click on the cell next to it under the Location column, and then click
on the down arrow to bring up a pop-up list of all of the assignable pins from the FPGA. Select the pin
number that you want to assign to that I/O signal. In Figure 1, the eight bits of signal d0 has already been
assigned to the corresponding pins on the FPGA. For example, d0[4] (bit 4 of d0) is assigned to pin W12.
Figure 1: The Pin Planner showing the mapping of the I/O signals for the circuit to the pins on the
EP2C20F484C7 chip.
Refer to Appendix A for the mappings between the actual I/O device (i.e., the switches and lights on
the development board) and the FPGA pin. Perform the following signal-to-pin assignments for the FPGA
chip. For your convenience, the pin mappings that you need to do are listed in Table 1.

d0[4..0] to SWITCH[4..0]

d1[4..0] to SWITCH[9..5]

y[4..0] to LEDR[4..0]

s to KEY0
I/O Signal Name
d0[0]
d0[1]
d0[2]
d0[3]
d0[4]
d1[0]
d1[1]
d1[2]
d1[3]
d1[4]
s
y[0]
y[1]
y[2]
y[3]
y[4]
I/O Device Name
SWITCH[0]
SWITCH[1]
SWITCH[2]
SWITCH[3]
SWITCH[4]
SWITCH[5]
SWITCH[6]
SWITCH[7]
SWITCH[8]
SWITCH[9]
KEY[0]
LEDR[0]
LEDR[1]
LEDR[2]
LEDR[3]
LEDR[4]
FPGA Pin
L22
L21
M22
V12
W12
U12
U11
M2
M1
L2
R22
R20
R19
U19
Y19
T18
Table 1: Pin mappings for the 2-to-1 multiplexer circuit.
An alternative and quicker method for mapping the pins is to edit the .qsf file directly. Instead of using
the Pin Planner to do the pin mappings, you can edit the text file mux.qsf using a text editor such as
Windows’ Notepad. (For this file name, mux is the name of the project.) For each signal to pin mapping,
insert a line such as the following to the end of the file
set_location_assignment PIN_W12 -to d0[4]
Replace W12 with the actual pin number that you want, and replace d0[4] with the signal name that you
want. The ordering and actual locations of these lines in the file do not matter. After saving this text file,
the pin numbers will be reflected in the Pin Planner.
1.1.3
Full Compilation
Now that we have synthesized and created the netlist for the circuit, and have mapped all of the I/O
signals to the actual pins on the FPGA, the next step is to perform a full compilation to fit the netlist and the
pin assignments to the FPGA chip.
From the Quartus II menu, select Processing > Start Compilation to start the full compilation of the
circuit. Alternatively, you can click on the Start Compilation icon
.
You can watch the compilation progress in the Tasks window pane, and also the Flow Summary
statistics. At the completion of the compilation, you will see in the Message window pane a message telling
you that the Quartus II full compilation was successful with 0 errors and some warnings. In most situations,
you can ignore the warnings.
1.1.4
Programming the FPGA
In the final step, we will upload the circuit onto the Microprocessor Design Trainer board by programming
the FPGA chip. Click on the Programmer button
in the toolbar to bring up the Programmer window.
Click on the Start button to upload the circuit onto the trainer board as shown in Figure 2. When the
circuit is uploaded onto the board, the progress bar at the top-right corner of the programmer window
should show 100% in green.
Figure 2: Successful programming of the logic circuit onto the trainer board.
1.1.5
Testing the Circuit in Hardware
Test and verify the operation of the multiplexer on the trainer board. Switches 8 to 15 are the 8-bit
input for d1, and switches 0 to 7 are the 8-bit input for d0. The 8-bit output y is connected to LEDs 0 to 7.
The mux select signal is connected to push button PB0. The truth table for the mux is shown next.
Input
s (KEY0)
0
1
Output
y (LED 0 to 4)
d0 (SWITCH 0 to 4)
d1 (SWITCH 5 to 9)
When KEY0 is not pressed, the five LEDs should reflect the settings of switches 0 to 4, and when KEY0 is
pressed, the LEDs should reflect the settings of switches 5 to 9.
1.1.6
Experiments
1.
Currently the 5-bit output signal y is connected to the red LEDs 0 to 4. Re-map the 5-bit output signal
y to the green LEDs 0 to 4 instead. Test the circuit with the new mappings on the trainer board.
2.
Test and verify the operation of the 4-bit adder circuit from Experiment 1 of Lab 1 on the trainer board.
Connect the adder inputs to the switches, and the adder output to the LEDs.
3.
Test and verify the operation of the 4-bit register circuit from Experiment 2 of Lab 1 on the trainer
board. Connect the 4-bit register data inputs to four switches. Connect the 4-bit register data outputs to
four LEDs. Connect the asynchronous Clear signal to PB0. Connect the Load signal to PB1. Connect
the register Clock signal to the master clock on the trainer board which is pin E2.
Set the data input switches to some value. Press PB1 and you should see the value being displayed on
the LEDs. Pressing PB0 will clear the LEDs.
4.
Test and verify the operation of the counting from 1 to 10 problem datapath circuit from Experiment 3
of Lab 1 on the trainer board. Connect the Clear signal to PB0. Connect the iLoad signal to PB1.
Connect the Clock signal to the master clock on the trainer board which is pin E2. Connect the status
signal (i  10) to LED15. Connect the Out signal to Switch 0. Connect the 4-bit Output signal to LEDs
0 to 3.
Set Switch 0 to the on position so that you will always see the output. Each time you press PB1
(iLoad), the next value from the adder should be loaded into the register, and you should see the
content of the register on the LEDs. Do you actually see each count from 1 to 10 as a binary number on
the four LEDs? Describe what you see and explain why it is so? Hint: it has to do with the speed of the
clock.
5.
There is a clock divider circuit on the DVD inside the Circuits folder for slowing down the clock.
Copy this circuit and the symbol to the project folder for Experiment 4. Add this clock divider circuit
into the counting circuit of Experiment 4. Instead of the master clock signal connecting directly to the
Clock input of the register, connect this clock divider circuit between them, so that the master clock
signal inputs to the clock divider circuit, and the output from the clock divider circuit connects to the
Clock input of the register. Now test this new circuit. Do you see each count from 1 to 10? Does the
count stop at 10, or does it continue? Why?